arch/powerpc/platforms/85xx/mpc85xx_mds.c

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
   3  *
   4  * Author: Andy Fleming <afleming@freescale.com>
   5  *
   6  * Based on 83xx/mpc8360e_pb.c by:
   7  *         Li Yang <LeoLi@freescale.com>
   8  *         Yin Olivia <Hong-hua.Yin@freescale.com>
   9  *
  10  * Description:
  11  * MPC85xx MDS board specific routines.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/major.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/initrd.h>
  31 #include <linux/module.h>
  32 #include <linux/fsl_devices.h>
  33
  34 #include <asm/of_device.h>
  35 #include <asm/of_platform.h>
  36 #include <asm/system.h>
  37 #include <asm/atomic.h>
  38 #include <asm/time.h>
  39 #include <asm/io.h>
  40 #include <asm/machdep.h>
  41 #include <asm/pci-bridge.h>
  42 #include <asm/mpc85xx.h>
  43 #include <asm/irq.h>
  44 #include <mm/mmu_decl.h>
  45 #include <asm/prom.h>
  46 #include <asm/udbg.h>
  47 #include <sysdev/fsl_soc.h>
  48 #include <sysdev/fsl_pci.h>
  49 #include <asm/qe.h>
  50 #include <asm/qe_ic.h>
  51 #include <asm/mpic.h>
  52
  53 #include "mpc85xx.h"
  54
  55 #undef DEBUG
  56 #ifdef DEBUG
  57 #define DBG(fmt...) udbg_printf(fmt)
  58 #else
  59 #define DBG(fmt...)
  60 #endif
  61
  62 /* ************************************************************************
  63  *
  64  * Setup the architecture
  65  *
  66  */
  67 static void __init mpc85xx_mds_setup_arch(void)
  68 {
  69         struct device_node *np;
  70         static u8 *bcsr_regs = NULL;
  71
  72         if (ppc_md.progress)
  73                 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
  74
  75         /* Map BCSR area */
  76         np = of_find_node_by_name(NULL, "bcsr");
  77         if (np != NULL) {
  78                 struct resource res;
  79
  80                 of_address_to_resource(np, 0, &res);
  81                 bcsr_regs = ioremap(res.start, res.end - res.start +1);
  82                 of_node_put(np);
  83         }
  84
  85 #ifdef CONFIG_PCI
  86         for_each_node_by_type(np, "pci") {
  87                 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
  88                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) {
  89                         struct resource rsrc;
  90                         of_address_to_resource(np, 0, &rsrc);
  91                         if ((rsrc.start & 0xfffff) == 0x8000)
  92                                 fsl_add_bridge(np, 1);
  93                         else
  94                                 fsl_add_bridge(np, 0);
  95                 }
  96         }
  97 #endif
  98
  99 #ifdef CONFIG_QUICC_ENGINE
 100         if ((np = of_find_node_by_name(NULL, "qe")) != NULL) {
 101                 qe_reset();
 102                 of_node_put(np);
 103         }
 104
 105         if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
 106                 struct device_node *ucc = NULL;
 107
 108                 par_io_init(np);
 109                 of_node_put(np);
 110
 111                 for ( ;(ucc = of_find_node_by_name(ucc, "ucc")) != NULL;)
 112                         par_io_of_config(ucc);
 113
 114                 of_node_put(ucc);
 115         }
 116
 117         if (bcsr_regs) {
 118                 u8 bcsr_phy;
 119
 120                 /* Reset the Ethernet PHY */
 121                 bcsr_phy = in_be8(&bcsr_regs[9]);
 122                 bcsr_phy &= ~0x20;
 123                 out_be8(&bcsr_regs[9], bcsr_phy);
 124
 125                 udelay(1000);
 126
 127                 bcsr_phy = in_be8(&bcsr_regs[9]);
 128                 bcsr_phy |= 0x20;
 129                 out_be8(&bcsr_regs[9], bcsr_phy);
 130
 131                 iounmap(bcsr_regs);
 132         }
 133
 134 #endif  /* CONFIG_QUICC_ENGINE */
 135 }
 136
 137 static struct of_device_id mpc85xx_ids[] = {
 138         { .type = "soc", },
 139         { .compatible = "soc", },
 140         { .type = "qe", },
 141         {},
 142 };
 143
 144 static int __init mpc85xx_publish_devices(void)
 145 {
 146         if (!machine_is(mpc85xx_mds))
 147                 return 0;
 148
 149         /* Publish the QE devices */
 150         of_platform_bus_probe(NULL,mpc85xx_ids,NULL);
 151
 152         return 0;
 153 }
 154 device_initcall(mpc85xx_publish_devices);
 155
 156 static void __init mpc85xx_mds_pic_init(void)
 157 {
 158         struct mpic *mpic;
 159         struct resource r;
 160         struct device_node *np = NULL;
 161
 162         np = of_find_node_by_type(NULL, "open-pic");
 163         if (!np)
 164                 return;
 165
 166         if (of_address_to_resource(np, 0, &r)) {
 167                 printk(KERN_ERR "Failed to map mpic register space\n");
 168                 of_node_put(np);
 169                 return;
 170         }
 171
 172         mpic = mpic_alloc(np, r.start,
 173                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 174                         0, 256, " OpenPIC  ");
 175         BUG_ON(mpic == NULL);
 176         of_node_put(np);
 177
 178         mpic_init(mpic);
 179
 180 #ifdef CONFIG_QUICC_ENGINE
 181         np = of_find_node_by_type(NULL, "qeic");
 182         if (!np)
 183                 return;
 184
 185         qe_ic_init(np, 0);
 186         of_node_put(np);
 187 #endif                          /* CONFIG_QUICC_ENGINE */
 188 }
 189
 190 static int __init mpc85xx_mds_probe(void)
 191 {
 192         unsigned long root = of_get_flat_dt_root();
 193
 194         return of_flat_dt_is_compatible(root, "MPC85xxMDS");
 195 }
 196
 197 define_machine(mpc85xx_mds) {
 198         .name           = "MPC85xx MDS",
 199         .probe          = mpc85xx_mds_probe,
 200         .setup_arch     = mpc85xx_mds_setup_arch,
 201         .init_IRQ       = mpc85xx_mds_pic_init,
 202         .get_irq        = mpic_get_irq,
 203         .restart        = mpc85xx_restart,
 204         .calibrate_decr = generic_calibrate_decr,
 205         .progress       = udbg_progress,
 206 #ifdef CONFIG_PCI
 207         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 208 #endif
 209 };