2 * IOMMU implementation for Cell Broadband Processor Architecture
4 * (C) Copyright IBM Corporation 2006
6 * Author: Jeremy Kerr <jk@ozlabs.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/notifier.h>
29 #include <linux/of_platform.h>
32 #include <asm/iommu.h>
33 #include <asm/machdep.h>
34 #include <asm/pci-bridge.h>
37 #include <asm/firmware.h>
38 #include <asm/cell-regs.h>
40 #include "interrupt.h"
42 /* Define CELL_IOMMU_REAL_UNMAP to actually unmap non-used pages
43 * instead of leaving them mapped to some dummy page. This can be
44 * enabled once the appropriate workarounds for spider bugs have
47 #define CELL_IOMMU_REAL_UNMAP
49 /* Define CELL_IOMMU_STRICT_PROTECTION to enforce protection of
50 * IO PTEs based on the transfer direction. That can be enabled
51 * once spider-net has been fixed to pass the correct direction
52 * to the DMA mapping functions
54 #define CELL_IOMMU_STRICT_PROTECTION
59 /* IOC mmap registers */
60 #define IOC_Reg_Size 0x2000
62 #define IOC_IOPT_CacheInvd 0x908
63 #define IOC_IOPT_CacheInvd_NE_Mask 0xffe0000000000000ul
64 #define IOC_IOPT_CacheInvd_IOPTE_Mask 0x000003fffffffff8ul
65 #define IOC_IOPT_CacheInvd_Busy 0x0000000000000001ul
67 #define IOC_IOST_Origin 0x918
68 #define IOC_IOST_Origin_E 0x8000000000000000ul
69 #define IOC_IOST_Origin_HW 0x0000000000000800ul
70 #define IOC_IOST_Origin_HL 0x0000000000000400ul
72 #define IOC_IO_ExcpStat 0x920
73 #define IOC_IO_ExcpStat_V 0x8000000000000000ul
74 #define IOC_IO_ExcpStat_SPF_Mask 0x6000000000000000ul
75 #define IOC_IO_ExcpStat_SPF_S 0x6000000000000000ul
76 #define IOC_IO_ExcpStat_SPF_P 0x4000000000000000ul
77 #define IOC_IO_ExcpStat_ADDR_Mask 0x00000007fffff000ul
78 #define IOC_IO_ExcpStat_RW_Mask 0x0000000000000800ul
79 #define IOC_IO_ExcpStat_IOID_Mask 0x00000000000007fful
81 #define IOC_IO_ExcpMask 0x928
82 #define IOC_IO_ExcpMask_SFE 0x4000000000000000ul
83 #define IOC_IO_ExcpMask_PFE 0x2000000000000000ul
85 #define IOC_IOCmd_Offset 0x1000
87 #define IOC_IOCmd_Cfg 0xc00
88 #define IOC_IOCmd_Cfg_TE 0x0000800000000000ul
91 /* Segment table entries */
92 #define IOSTE_V 0x8000000000000000ul /* valid */
93 #define IOSTE_H 0x4000000000000000ul /* cache hint */
94 #define IOSTE_PT_Base_RPN_Mask 0x3ffffffffffff000ul /* base RPN of IOPT */
95 #define IOSTE_NPPT_Mask 0x0000000000000fe0ul /* no. pages in IOPT */
96 #define IOSTE_PS_Mask 0x0000000000000007ul /* page size */
97 #define IOSTE_PS_4K 0x0000000000000001ul /* - 4kB */
98 #define IOSTE_PS_64K 0x0000000000000003ul /* - 64kB */
99 #define IOSTE_PS_1M 0x0000000000000005ul /* - 1MB */
100 #define IOSTE_PS_16M 0x0000000000000007ul /* - 16MB */
102 /* Page table entries */
103 #define IOPTE_PP_W 0x8000000000000000ul /* protection: write */
104 #define IOPTE_PP_R 0x4000000000000000ul /* protection: read */
105 #define IOPTE_M 0x2000000000000000ul /* coherency required */
106 #define IOPTE_SO_R 0x1000000000000000ul /* ordering: writes */
107 #define IOPTE_SO_RW 0x1800000000000000ul /* ordering: r & w */
108 #define IOPTE_RPN_Mask 0x07fffffffffff000ul /* RPN */
109 #define IOPTE_H 0x0000000000000800ul /* cache hint */
110 #define IOPTE_IOID_Mask 0x00000000000007fful /* ioid */
114 #define IO_SEGMENT_SHIFT 28
115 #define IO_PAGENO_BITS (IO_SEGMENT_SHIFT - IOMMU_PAGE_SHIFT)
117 /* The high bit needs to be set on every DMA address */
118 #define SPIDER_DMA_OFFSET 0x80000000ul
120 struct iommu_window {
121 struct list_head list;
122 struct cbe_iommu *iommu;
123 unsigned long offset;
125 unsigned long pte_offset;
127 struct iommu_table table;
134 void __iomem *xlate_regs;
135 void __iomem *cmd_regs;
139 struct list_head windows;
142 /* Static array of iommus, one per node
143 * each contains a list of windows, keyed from dma_window property
144 * - on bus setup, look for a matching window, or create one
145 * - on dev setup, assign iommu_table ptr
147 static struct cbe_iommu iommus[NR_IOMMUS];
148 static int cbe_nr_iommus;
150 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte,
153 unsigned long __iomem *reg;
157 reg = iommu->xlate_regs + IOC_IOPT_CacheInvd;
160 /* we can invalidate up to 1 << 11 PTEs at once */
161 n = min(n_ptes, 1l << 11);
162 val = (((n /*- 1*/) << 53) & IOC_IOPT_CacheInvd_NE_Mask)
163 | (__pa(pte) & IOC_IOPT_CacheInvd_IOPTE_Mask)
164 | IOC_IOPT_CacheInvd_Busy;
167 while (in_be64(reg) & IOC_IOPT_CacheInvd_Busy)
175 static void tce_build_cell(struct iommu_table *tbl, long index, long npages,
176 unsigned long uaddr, enum dma_data_direction direction)
179 unsigned long *io_pte, base_pte;
180 struct iommu_window *window =
181 container_of(tbl, struct iommu_window, table);
183 /* implementing proper protection causes problems with the spidernet
184 * driver - check mapping directions later, but allow read & write by
186 #ifdef CELL_IOMMU_STRICT_PROTECTION
187 /* to avoid referencing a global, we use a trick here to setup the
188 * protection bit. "prot" is setup to be 3 fields of 4 bits apprended
189 * together for each of the 3 supported direction values. It is then
190 * shifted left so that the fields matching the desired direction
191 * lands on the appropriate bits, and other bits are masked out.
193 const unsigned long prot = 0xc48;
195 ((prot << (52 + 4 * direction)) & (IOPTE_PP_W | IOPTE_PP_R))
196 | IOPTE_M | IOPTE_SO_RW | (window->ioid & IOPTE_IOID_Mask);
198 base_pte = IOPTE_PP_W | IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW |
199 (window->ioid & IOPTE_IOID_Mask);
202 io_pte = (unsigned long *)tbl->it_base + (index - window->pte_offset);
204 for (i = 0; i < npages; i++, uaddr += IOMMU_PAGE_SIZE)
205 io_pte[i] = base_pte | (__pa(uaddr) & IOPTE_RPN_Mask);
209 invalidate_tce_cache(window->iommu, io_pte, npages);
211 pr_debug("tce_build_cell(index=%lx,n=%lx,dir=%d,base_pte=%lx)\n",
212 index, npages, direction, base_pte);
215 static void tce_free_cell(struct iommu_table *tbl, long index, long npages)
219 unsigned long *io_pte, pte;
220 struct iommu_window *window =
221 container_of(tbl, struct iommu_window, table);
223 pr_debug("tce_free_cell(index=%lx,n=%lx)\n", index, npages);
225 #ifdef CELL_IOMMU_REAL_UNMAP
228 /* spider bridge does PCI reads after freeing - insert a mapping
229 * to a scratch page instead of an invalid entry */
230 pte = IOPTE_PP_R | IOPTE_M | IOPTE_SO_RW | __pa(window->iommu->pad_page)
231 | (window->ioid & IOPTE_IOID_Mask);
234 io_pte = (unsigned long *)tbl->it_base + (index - window->pte_offset);
236 for (i = 0; i < npages; i++)
241 invalidate_tce_cache(window->iommu, io_pte, npages);
244 static irqreturn_t ioc_interrupt(int irq, void *data)
247 struct cbe_iommu *iommu = data;
249 stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
251 /* Might want to rate limit it */
252 printk(KERN_ERR "iommu: DMA exception 0x%016lx\n", stat);
253 printk(KERN_ERR " V=%d, SPF=[%c%c], RW=%s, IOID=0x%04x\n",
254 !!(stat & IOC_IO_ExcpStat_V),
255 (stat & IOC_IO_ExcpStat_SPF_S) ? 'S' : ' ',
256 (stat & IOC_IO_ExcpStat_SPF_P) ? 'P' : ' ',
257 (stat & IOC_IO_ExcpStat_RW_Mask) ? "Read" : "Write",
258 (unsigned int)(stat & IOC_IO_ExcpStat_IOID_Mask));
259 printk(KERN_ERR " page=0x%016lx\n",
260 stat & IOC_IO_ExcpStat_ADDR_Mask);
262 /* clear interrupt */
263 stat &= ~IOC_IO_ExcpStat_V;
264 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat);
269 static int cell_iommu_find_ioc(int nid, unsigned long *base)
271 struct device_node *np;
276 /* First look for new style /be nodes */
277 for_each_node_by_name(np, "ioc") {
278 if (of_node_to_nid(np) != nid)
280 if (of_address_to_resource(np, 0, &r)) {
281 printk(KERN_ERR "iommu: can't get address for %s\n",
290 /* Ok, let's try the old way */
291 for_each_node_by_type(np, "cpu") {
292 const unsigned int *nidp;
293 const unsigned long *tmp;
295 nidp = of_get_property(np, "node-id", NULL);
296 if (nidp && *nidp == nid) {
297 tmp = of_get_property(np, "ioc-translation", NULL);
309 static void cell_iommu_setup_hardware(struct cbe_iommu *iommu, unsigned long size)
313 unsigned long reg, segments, pages_per_segment, ptab_size, stab_size,
314 n_pte_pages, xlate_base;
317 if (cell_iommu_find_ioc(iommu->nid, &xlate_base))
318 panic("%s: missing IOC register mappings for node %d\n",
319 __FUNCTION__, iommu->nid);
321 iommu->xlate_regs = ioremap(xlate_base, IOC_Reg_Size);
322 iommu->cmd_regs = iommu->xlate_regs + IOC_IOCmd_Offset;
324 segments = size >> IO_SEGMENT_SHIFT;
325 pages_per_segment = 1ull << IO_PAGENO_BITS;
327 pr_debug("%s: iommu[%d]: segments: %lu, pages per segment: %lu\n",
328 __FUNCTION__, iommu->nid, segments, pages_per_segment);
330 /* set up the segment table */
331 stab_size = segments * sizeof(unsigned long);
332 page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(stab_size));
334 iommu->stab = page_address(page);
335 clear_page(iommu->stab);
337 /* ... and the page tables. Since these are contiguous, we can treat
338 * the page tables as one array of ptes, like pSeries does.
340 ptab_size = segments * pages_per_segment * sizeof(unsigned long);
341 pr_debug("%s: iommu[%d]: ptab_size: %lu, order: %d\n", __FUNCTION__,
342 iommu->nid, ptab_size, get_order(ptab_size));
343 page = alloc_pages_node(iommu->nid, GFP_KERNEL, get_order(ptab_size));
346 iommu->ptab = page_address(page);
347 memset(iommu->ptab, 0, ptab_size);
349 /* allocate a bogus page for the end of each mapping */
350 page = alloc_pages_node(iommu->nid, GFP_KERNEL, 0);
352 iommu->pad_page = page_address(page);
353 clear_page(iommu->pad_page);
355 /* number of pages needed for a page table */
356 n_pte_pages = (pages_per_segment *
357 sizeof(unsigned long)) >> IOMMU_PAGE_SHIFT;
359 pr_debug("%s: iommu[%d]: stab at %p, ptab at %p, n_pte_pages: %lu\n",
360 __FUNCTION__, iommu->nid, iommu->stab, iommu->ptab,
363 /* initialise the STEs */
364 reg = IOSTE_V | ((n_pte_pages - 1) << 5);
366 if (IOMMU_PAGE_SIZE == 0x1000)
368 else if (IOMMU_PAGE_SIZE == 0x10000)
371 extern void __unknown_page_size_error(void);
372 __unknown_page_size_error();
375 pr_debug("Setting up IOMMU stab:\n");
376 for (i = 0; i * (1ul << IO_SEGMENT_SHIFT) < size; i++) {
377 iommu->stab[i] = reg |
378 (__pa(iommu->ptab) + n_pte_pages * IOMMU_PAGE_SIZE * i);
379 pr_debug("\t[%d] 0x%016lx\n", i, iommu->stab[i]);
382 /* ensure that the STEs have updated */
385 /* setup interrupts for the iommu. */
386 reg = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat);
387 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat,
388 reg & ~IOC_IO_ExcpStat_V);
389 out_be64(iommu->xlate_regs + IOC_IO_ExcpMask,
390 IOC_IO_ExcpMask_PFE | IOC_IO_ExcpMask_SFE);
392 virq = irq_create_mapping(NULL,
393 IIC_IRQ_IOEX_ATI | (iommu->nid << IIC_IRQ_NODE_SHIFT));
394 BUG_ON(virq == NO_IRQ);
396 ret = request_irq(virq, ioc_interrupt, IRQF_DISABLED,
400 /* set the IOC segment table origin register (and turn on the iommu) */
401 reg = IOC_IOST_Origin_E | __pa(iommu->stab) | IOC_IOST_Origin_HW;
402 out_be64(iommu->xlate_regs + IOC_IOST_Origin, reg);
403 in_be64(iommu->xlate_regs + IOC_IOST_Origin);
405 /* turn on IO translation */
406 reg = in_be64(iommu->cmd_regs + IOC_IOCmd_Cfg) | IOC_IOCmd_Cfg_TE;
407 out_be64(iommu->cmd_regs + IOC_IOCmd_Cfg, reg);
410 #if 0/* Unused for now */
411 static struct iommu_window *find_window(struct cbe_iommu *iommu,
412 unsigned long offset, unsigned long size)
414 struct iommu_window *window;
416 /* todo: check for overlapping (but not equal) windows) */
418 list_for_each_entry(window, &(iommu->windows), list) {
419 if (window->offset == offset && window->size == size)
427 static struct iommu_window * __init
428 cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
429 unsigned long offset, unsigned long size,
430 unsigned long pte_offset)
432 struct iommu_window *window;
433 const unsigned int *ioid;
435 ioid = of_get_property(np, "ioid", NULL);
437 printk(KERN_WARNING "iommu: missing ioid for %s using 0\n",
440 window = kmalloc_node(sizeof(*window), GFP_KERNEL, iommu->nid);
441 BUG_ON(window == NULL);
443 window->offset = offset;
445 window->ioid = ioid ? *ioid : 0;
446 window->iommu = iommu;
447 window->pte_offset = pte_offset;
449 window->table.it_blocksize = 16;
450 window->table.it_base = (unsigned long)iommu->ptab;
451 window->table.it_index = iommu->nid;
452 window->table.it_offset = (offset >> IOMMU_PAGE_SHIFT) +
454 window->table.it_size = size >> IOMMU_PAGE_SHIFT;
456 iommu_init_table(&window->table, iommu->nid);
458 pr_debug("\tioid %d\n", window->ioid);
459 pr_debug("\tblocksize %ld\n", window->table.it_blocksize);
460 pr_debug("\tbase 0x%016lx\n", window->table.it_base);
461 pr_debug("\toffset 0x%lx\n", window->table.it_offset);
462 pr_debug("\tsize %ld\n", window->table.it_size);
464 list_add(&window->list, &iommu->windows);
469 /* We need to map and reserve the first IOMMU page since it's used
470 * by the spider workaround. In theory, we only need to do that when
471 * running on spider but it doesn't really matter.
473 * This code also assumes that we have a window that starts at 0,
474 * which is the case on all spider based blades.
476 __set_bit(0, window->table.it_map);
477 tce_build_cell(&window->table, window->table.it_offset, 1,
478 (unsigned long)iommu->pad_page, DMA_TO_DEVICE);
479 window->table.it_hint = window->table.it_blocksize;
484 static struct cbe_iommu *cell_iommu_for_node(int nid)
488 for (i = 0; i < cbe_nr_iommus; i++)
489 if (iommus[i].nid == nid)
494 static unsigned long cell_dma_direct_offset;
496 static void cell_dma_dev_setup(struct device *dev)
498 struct iommu_window *window;
499 struct cbe_iommu *iommu;
500 struct dev_archdata *archdata = &dev->archdata;
502 if (get_pci_dma_ops() == &dma_direct_ops) {
503 archdata->dma_data = (void *)cell_dma_direct_offset;
507 /* Current implementation uses the first window available in that
508 * node's iommu. We -might- do something smarter later though it may
511 iommu = cell_iommu_for_node(archdata->numa_node);
512 if (iommu == NULL || list_empty(&iommu->windows)) {
513 printk(KERN_ERR "iommu: missing iommu for %s (node %d)\n",
514 archdata->of_node ? archdata->of_node->full_name : "?",
515 archdata->numa_node);
518 window = list_entry(iommu->windows.next, struct iommu_window, list);
520 archdata->dma_data = &window->table;
523 static void cell_pci_dma_dev_setup(struct pci_dev *dev)
525 cell_dma_dev_setup(&dev->dev);
528 static int cell_of_bus_notify(struct notifier_block *nb, unsigned long action,
531 struct device *dev = data;
533 /* We are only intereted in device addition */
534 if (action != BUS_NOTIFY_ADD_DEVICE)
537 /* We use the PCI DMA ops */
538 dev->archdata.dma_ops = get_pci_dma_ops();
540 cell_dma_dev_setup(dev);
545 static struct notifier_block cell_of_bus_notifier = {
546 .notifier_call = cell_of_bus_notify
549 static int __init cell_iommu_get_window(struct device_node *np,
553 const void *dma_window;
556 /* Use ibm,dma-window if available, else, hard code ! */
557 dma_window = of_get_property(np, "ibm,dma-window", NULL);
558 if (dma_window == NULL) {
564 of_parse_dma_window(np, dma_window, &index, base, size);
568 static void __init cell_iommu_init_one(struct device_node *np, unsigned long offset)
570 struct cbe_iommu *iommu;
571 unsigned long base, size;
575 nid = of_node_to_nid(np);
577 printk(KERN_ERR "iommu: failed to get node for %s\n",
581 pr_debug("iommu: setting up iommu for node %d (%s)\n",
584 /* XXX todo: If we can have multiple windows on the same IOMMU, which
585 * isn't the case today, we probably want here to check wether the
586 * iommu for that node is already setup.
587 * However, there might be issue with getting the size right so let's
588 * ignore that for now. We might want to completely get rid of the
589 * multiple window support since the cell iommu supports per-page ioids
592 if (cbe_nr_iommus >= NR_IOMMUS) {
593 printk(KERN_ERR "iommu: too many IOMMUs detected ! (%s)\n",
598 /* Init base fields */
603 snprintf(iommu->name, sizeof(iommu->name), "iommu%d", i);
604 INIT_LIST_HEAD(&iommu->windows);
606 /* Obtain a window for it */
607 cell_iommu_get_window(np, &base, &size);
609 pr_debug("\ttranslating window 0x%lx...0x%lx\n",
610 base, base + size - 1);
612 /* Initialize the hardware */
613 cell_iommu_setup_hardware(iommu, size);
615 /* Setup the iommu_table */
616 cell_iommu_setup_window(iommu, np, base, size,
617 offset >> IOMMU_PAGE_SHIFT);
620 static void __init cell_disable_iommus(void)
623 unsigned long base, val;
624 void __iomem *xregs, *cregs;
626 /* Make sure IOC translation is disabled on all nodes */
627 for_each_online_node(node) {
628 if (cell_iommu_find_ioc(node, &base))
630 xregs = ioremap(base, IOC_Reg_Size);
633 cregs = xregs + IOC_IOCmd_Offset;
635 pr_debug("iommu: cleaning up iommu on node %d\n", node);
637 out_be64(xregs + IOC_IOST_Origin, 0);
638 (void)in_be64(xregs + IOC_IOST_Origin);
639 val = in_be64(cregs + IOC_IOCmd_Cfg);
640 val &= ~IOC_IOCmd_Cfg_TE;
641 out_be64(cregs + IOC_IOCmd_Cfg, val);
642 (void)in_be64(cregs + IOC_IOCmd_Cfg);
648 static int __init cell_iommu_init_disabled(void)
650 struct device_node *np = NULL;
651 unsigned long base = 0, size;
653 /* When no iommu is present, we use direct DMA ops */
654 set_pci_dma_ops(&dma_direct_ops);
656 /* First make sure all IOC translation is turned off */
657 cell_disable_iommus();
659 /* If we have no Axon, we set up the spider DMA magic offset */
660 if (of_find_node_by_name(NULL, "axon") == NULL)
661 cell_dma_direct_offset = SPIDER_DMA_OFFSET;
663 /* Now we need to check to see where the memory is mapped
664 * in PCI space. We assume that all busses use the same dma
665 * window which is always the case so far on Cell, thus we
666 * pick up the first pci-internal node we can find and check
667 * the DMA window from there.
669 for_each_node_by_name(np, "axon") {
670 if (np->parent == NULL || np->parent->parent != NULL)
672 if (cell_iommu_get_window(np, &base, &size) == 0)
676 for_each_node_by_name(np, "pci-internal") {
677 if (np->parent == NULL || np->parent->parent != NULL)
679 if (cell_iommu_get_window(np, &base, &size) == 0)
685 /* If we found a DMA window, we check if it's big enough to enclose
686 * all of physical memory. If not, we force enable IOMMU
688 if (np && size < lmb_end_of_DRAM()) {
689 printk(KERN_WARNING "iommu: force-enabled, dma window"
690 " (%ldMB) smaller than total memory (%ldMB)\n",
691 size >> 20, lmb_end_of_DRAM() >> 20);
695 cell_dma_direct_offset += base;
697 if (cell_dma_direct_offset != 0)
698 ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup;
700 printk("iommu: disabled, direct DMA offset is 0x%lx\n",
701 cell_dma_direct_offset);
706 static int __init cell_iommu_init(void)
708 struct device_node *np;
710 /* If IOMMU is disabled or we have little enough RAM to not need
711 * to enable it, we setup a direct mapping.
713 * Note: should we make sure we have the IOMMU actually disabled ?
716 (!iommu_force_on && lmb_end_of_DRAM() <= 0x80000000ull))
717 if (cell_iommu_init_disabled() == 0)
720 /* Setup various ppc_md. callbacks */
721 ppc_md.pci_dma_dev_setup = cell_pci_dma_dev_setup;
722 ppc_md.tce_build = tce_build_cell;
723 ppc_md.tce_free = tce_free_cell;
725 /* Create an iommu for each /axon node. */
726 for_each_node_by_name(np, "axon") {
727 if (np->parent == NULL || np->parent->parent != NULL)
729 cell_iommu_init_one(np, 0);
732 /* Create an iommu for each toplevel /pci-internal node for
733 * old hardware/firmware
735 for_each_node_by_name(np, "pci-internal") {
736 if (np->parent == NULL || np->parent->parent != NULL)
738 cell_iommu_init_one(np, SPIDER_DMA_OFFSET);
741 /* Setup default PCI iommu ops */
742 set_pci_dma_ops(&dma_iommu_ops);
745 /* Register callbacks on OF platform device addition/removal
746 * to handle linking them to the right DMA operations
748 bus_register_notifier(&of_platform_bus_type, &cell_of_bus_notifier);
752 machine_arch_initcall(cell, cell_iommu_init);
753 machine_arch_initcall(celleb_native, cell_iommu_init);