2 * Copyright (C) 1995 Linus Torvalds
3 * Adapted from 'alpha' version by Gary Thomas
4 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 #include <linux/errno.h>
12 #include <linux/sched.h>
13 #include <linux/kernel.h>
15 #include <linux/stddef.h>
16 #include <linux/unistd.h>
17 #include <linux/ptrace.h>
18 #include <linux/slab.h>
19 #include <linux/user.h>
20 #include <linux/a.out.h>
21 #include <linux/tty.h>
22 #include <linux/major.h>
23 #include <linux/interrupt.h>
24 #include <linux/reboot.h>
25 #include <linux/init.h>
26 #include <linux/pci.h>
27 #include <linux/utsrelease.h>
28 #include <linux/adb.h>
29 #include <linux/module.h>
30 #include <linux/delay.h>
31 #include <linux/console.h>
32 #include <linux/seq_file.h>
33 #include <linux/root_dev.h>
34 #include <linux/initrd.h>
35 #include <linux/timer.h>
38 #include <asm/pgtable.h>
40 #include <asm/pci-bridge.h>
42 #include <asm/machdep.h>
44 #include <asm/hydra.h>
45 #include <asm/sections.h>
47 #include <asm/i8259.h>
55 void rtas_indicator_progress(char *, unsigned short);
58 EXPORT_SYMBOL(_chrp_type);
60 static struct mpic *chrp_mpic;
62 /* Used for doing CHRP event-scans */
63 DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
64 unsigned long event_scan_interval;
67 * XXX this should be in xmon.h, but putting it there means xmon.h
68 * has to include <linux/interrupt.h> (to get irqreturn_t), which
69 * causes all sorts of problems. -- paulus
71 extern irqreturn_t xmon_irq(int, void *);
73 extern unsigned long loops_per_jiffy;
75 /* To be replaced by RTAS when available */
76 static unsigned int __iomem *briq_SPOR;
79 extern struct smp_ops_t chrp_smp_ops;
82 static const char *gg2_memtypes[4] = {
83 "FPM", "SDRAM", "EDO", "BEDO"
85 static const char *gg2_cachesizes[4] = {
86 "256 KB", "512 KB", "1 MB", "Reserved"
88 static const char *gg2_cachetypes[4] = {
89 "Asynchronous", "Reserved", "Flow-Through Synchronous",
90 "Pipelined Synchronous"
92 static const char *gg2_cachemodes[4] = {
93 "Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
96 static const char *chrp_names[] = {
105 void chrp_show_cpuinfo(struct seq_file *m)
109 struct device_node *root;
110 const char *model = "";
112 root = of_find_node_by_path("/");
114 model = of_get_property(root, "model", NULL);
115 seq_printf(m, "machine\t\t: CHRP %s\n", model);
117 /* longtrail (goldengate) stuff */
118 if (model && !strncmp(model, "IBM,LongTrail", 13)) {
119 /* VLSI VAS96011/12 `Golden Gate 2' */
121 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
123 for (i = 0; i < (sdramen ? 4 : 6); i++) {
124 t = in_le32(gg2_pci_config_base+
129 switch ((t>>8) & 0x1f) {
152 seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
153 gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
156 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
157 seq_printf(m, "board l2\t: %s %s (%s)\n",
158 gg2_cachesizes[(t>>7) & 3],
159 gg2_cachetypes[(t>>2) & 3],
160 gg2_cachemodes[t & 3]);
166 * Fixes for the National Semiconductor PC78308VUL SuperI/O
168 * Some versions of Open Firmware incorrectly initialize the IRQ settings
169 * for keyboard and mouse
171 static inline void __init sio_write(u8 val, u8 index)
177 static inline u8 __init sio_read(u8 index)
183 static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
186 u8 level0, type0, active;
188 /* select logical device */
189 sio_write(device, 0x07);
190 active = sio_read(0x30);
191 level0 = sio_read(0x70);
192 type0 = sio_read(0x71);
193 if (level0 != level || type0 != type || !active) {
194 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
195 "remapping to level %d, type %d, active\n",
196 name, level0, type0, !active ? "in" : "", level, type);
197 sio_write(0x01, 0x30);
198 sio_write(level, 0x70);
199 sio_write(type, 0x71);
203 static void __init sio_init(void)
205 struct device_node *root;
208 root = of_find_node_by_path("/");
212 model = of_get_property(root, "model", NULL);
213 if (model && !strncmp(model, "IBM,LongTrail", 13)) {
214 /* logical device 0 (KBC/Keyboard) */
215 sio_fixup_irq("keyboard", 0, 1, 2);
216 /* select logical device 1 (KBC/Mouse) */
217 sio_fixup_irq("mouse", 1, 12, 2);
224 static void __init pegasos_set_l2cr(void)
226 struct device_node *np;
228 /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
229 if (_chrp_type != _CHRP_Pegasos)
232 /* Enable L2 cache if needed */
233 np = of_find_node_by_type(NULL, "cpu");
235 const unsigned int *l2cr = of_get_property(np, "l2cr", NULL);
237 printk ("Pegasos l2cr : no cpu l2cr property found\n");
240 if (!((*l2cr) & 0x80000000)) {
241 printk ("Pegasos l2cr : L2 cache was not active, "
244 _set_L2CR((*l2cr) | 0x80000000);
251 static void briq_restart(char *cmd)
255 out_be32(briq_SPOR, 0);
259 void __init chrp_setup_arch(void)
261 struct device_node *root = of_find_node_by_path("/");
262 const char *machine = NULL;
264 /* init to some ~sane value until calibrate_delay() runs */
265 loops_per_jiffy = 50000000/HZ;
268 machine = of_get_property(root, "model", NULL);
269 if (machine && strncmp(machine, "Pegasos", 7) == 0) {
270 _chrp_type = _CHRP_Pegasos;
271 } else if (machine && strncmp(machine, "IBM", 3) == 0) {
272 _chrp_type = _CHRP_IBM;
273 } else if (machine && strncmp(machine, "MOT", 3) == 0) {
274 _chrp_type = _CHRP_Motorola;
275 } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
276 _chrp_type = _CHRP_briq;
277 /* Map the SPOR register on briq and change the restart hook */
278 briq_SPOR = ioremap(0xff0000e8, 4);
279 ppc_md.restart = briq_restart;
281 /* Let's assume it is an IBM chrp if all else fails */
282 _chrp_type = _CHRP_IBM;
285 printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
288 if (rtas_token("display-character") >= 0)
289 ppc_md.progress = rtas_progress;
291 /* use RTAS time-of-day routines if available */
292 if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
293 ppc_md.get_boot_time = rtas_get_boot_time;
294 ppc_md.get_rtc_time = rtas_get_rtc_time;
295 ppc_md.set_rtc_time = rtas_set_rtc_time;
298 /* On pegasos, enable the L2 cache if not already done by OF */
301 /* Lookup PCI host bridges */
305 * Temporary fixes for PCI devices.
308 hydra_init(); /* Mac I/O */
311 * Fix the Super I/O configuration
315 pci_create_OF_bus_map();
318 * Print the banner, then scroll down so boot progress
319 * can be printed. -- Cort
321 if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
325 chrp_event_scan(unsigned long unused)
327 unsigned char log[1024];
330 /* XXX: we should loop until the hardware says no more error logs -- Cort */
331 rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
333 mod_timer(&__get_cpu_var(heartbeat_timer),
334 jiffies + event_scan_interval);
337 static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc)
339 unsigned int cascade_irq = i8259_irq();
340 if (cascade_irq != NO_IRQ)
341 generic_handle_irq(cascade_irq);
342 desc->chip->eoi(irq);
346 * Finds the open-pic node and sets up the mpic driver.
348 static void __init chrp_find_openpic(void)
350 struct device_node *np, *root;
352 int isu_size, idu_size;
353 const unsigned int *iranges, *opprop = NULL;
355 unsigned long opaddr;
358 np = of_find_node_by_type(NULL, "open-pic");
361 root = of_find_node_by_path("/");
363 opprop = of_get_property(root, "platform-open-pic", &oplen);
364 na = of_n_addr_cells(root);
366 if (opprop && oplen >= na * sizeof(unsigned int)) {
367 opaddr = opprop[na-1]; /* assume 32-bit */
368 oplen /= na * sizeof(unsigned int);
371 if (of_address_to_resource(np, 0, &r)) {
378 printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
380 iranges = of_get_property(np, "interrupt-ranges", &len);
382 len = 0; /* non-distributed mpic */
384 len /= 2 * sizeof(unsigned int);
387 * The first pair of cells in interrupt-ranges refers to the
388 * IDU; subsequent pairs refer to the ISUs.
391 printk(KERN_ERR "Insufficient addresses for distributed"
392 " OpenPIC (%d < %d)\n", oplen, len);
398 if (len > 0 && iranges[1] != 0) {
399 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
400 iranges[0], iranges[0] + iranges[1] - 1);
401 idu_size = iranges[1];
404 isu_size = iranges[3];
406 chrp_mpic = mpic_alloc(np, opaddr, MPIC_PRIMARY,
407 isu_size, 0, " MPIC ");
408 if (chrp_mpic == NULL) {
409 printk(KERN_ERR "Failed to allocate MPIC structure\n");
413 for (i = 1; i < len; ++i) {
416 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
417 iranges[0], iranges[0] + iranges[1] - 1,
419 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
422 mpic_init(chrp_mpic);
423 ppc_md.get_irq = mpic_get_irq;
429 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
430 static struct irqaction xmon_irqaction = {
432 .mask = CPU_MASK_NONE,
433 .name = "XMON break",
437 static void __init chrp_find_8259(void)
439 struct device_node *np, *pic = NULL;
440 unsigned long chrp_int_ack = 0;
441 unsigned int cascade_irq;
443 /* Look for cascade */
444 for_each_node_by_type(np, "interrupt-controller")
445 if (of_device_is_compatible(np, "chrp,iic")) {
449 /* Ok, 8259 wasn't found. We need to handle the case where
450 * we have a pegasos that claims to be chrp but doesn't have
451 * a proper interrupt tree
453 if (pic == NULL && chrp_mpic != NULL) {
454 printk(KERN_ERR "i8259: Not found in device-tree"
455 " assuming no legacy interrupts\n");
459 /* Look for intack. In a perfect world, we would look for it on
460 * the ISA bus that holds the 8259 but heh... Works that way. If
461 * we ever see a problem, we can try to re-use the pSeries code here.
462 * Also, Pegasos-type platforms don't have a proper node to start
465 for_each_node_by_name(np, "pci") {
466 const unsigned int *addrp = of_get_property(np,
467 "8259-interrupt-acknowledge", NULL);
471 chrp_int_ack = addrp[of_n_addr_cells(np)-1];
476 printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
477 " address, polling\n");
479 i8259_init(pic, chrp_int_ack);
480 if (ppc_md.get_irq == NULL) {
481 ppc_md.get_irq = i8259_irq;
482 irq_set_default_host(i8259_get_host());
484 if (chrp_mpic != NULL) {
485 cascade_irq = irq_of_parse_and_map(pic, 0);
486 if (cascade_irq == NO_IRQ)
487 printk(KERN_ERR "i8259: failed to map cascade irq\n");
489 set_irq_chained_handler(cascade_irq,
494 void __init chrp_init_IRQ(void)
496 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
497 struct device_node *kbd;
503 /* Pegasos has no MPIC, those ops would make it crash. It might be an
504 * option to move setting them to after we probe the PIC though
506 if (chrp_mpic != NULL)
507 smp_ops = &chrp_smp_ops;
508 #endif /* CONFIG_SMP */
510 if (_chrp_type == _CHRP_Pegasos)
511 ppc_md.get_irq = i8259_irq;
513 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
514 /* see if there is a keyboard in the device tree
515 with a parent of type "adb" */
516 for_each_node_by_name(kbd, "keyboard")
517 if (kbd->parent && kbd->parent->type
518 && strcmp(kbd->parent->type, "adb") == 0)
522 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
529 struct device_node *device;
530 const unsigned int *p = NULL;
536 request_region(0x20,0x20,"pic1");
537 request_region(0xa0,0x20,"pic2");
538 request_region(0x00,0x20,"dma1");
539 request_region(0x40,0x20,"timer");
540 request_region(0x80,0x10,"dma page reg");
541 request_region(0xc0,0x20,"dma2");
543 /* Get the event scan rate for the rtas so we know how
544 * often it expects a heartbeat. -- Cort
546 device = of_find_node_by_name(NULL, "rtas");
548 p = of_get_property(device, "rtas-event-scan-rate", NULL);
551 * Arrange to call chrp_event_scan at least *p times
552 * per minute. We use 59 rather than 60 here so that
553 * the rate will be slightly higher than the minimum.
554 * This all assumes we don't do hotplug CPU on any
555 * machine that needs the event scans done.
557 unsigned long interval, offset;
559 struct timer_list *timer;
561 interval = HZ * 59 / *p;
563 ncpus = num_online_cpus();
564 event_scan_interval = ncpus * interval;
565 for (cpu = 0; cpu < ncpus; ++cpu) {
566 timer = &per_cpu(heartbeat_timer, cpu);
567 setup_timer(timer, chrp_event_scan, 0);
568 timer->expires = jiffies + offset;
569 add_timer_on(timer, cpu);
572 printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
578 ppc_md.progress(" Have fun! ", 0x7777);
581 static int __init chrp_probe(void)
583 char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
584 "device_type", NULL);
587 if (strcmp(dtype, "chrp"))
590 ISA_DMA_THRESHOLD = ~0L;
591 DMA_MODE_READ = 0x44;
592 DMA_MODE_WRITE = 0x48;
597 define_machine(chrp) {
600 .setup_arch = chrp_setup_arch,
602 .show_cpuinfo = chrp_show_cpuinfo,
603 .init_IRQ = chrp_init_IRQ,
604 .restart = rtas_restart,
605 .power_off = rtas_power_off,
607 .time_init = chrp_time_init,
608 .set_rtc_time = chrp_set_rtc_time,
609 .get_rtc_time = chrp_get_rtc_time,
610 .calibrate_decr = generic_calibrate_decr,
611 .phys_mem_access_prot = pci_phys_mem_access_prot,