2 * arch/ppc/syslib/ppc4xx_pic.c
4 * Interrupt controller driver for PowerPC 4xx-based processors.
6 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
7 * Copyright (c) 2004, 2005 Zultys Technologies
9 * Based on original code by
10 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
11 * Armin Custer <akuster@mvista.com>
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
18 #include <linux/config.h>
19 #include <linux/init.h>
20 #include <linux/sched.h>
21 #include <linux/signal.h>
22 #include <linux/stddef.h>
24 #include <asm/processor.h>
25 #include <asm/system.h>
27 #include <asm/ppc4xx_pic.h>
29 /* See comment in include/arch-ppc/ppc4xx_pic.h
30 * for more info about these two variables
32 extern struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[NR_UICS]
33 __attribute__ ((weak));
34 extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak));
36 #define IRQ_MASK_UIC0(irq) (1 << (31 - (irq)))
37 #define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f)))
38 #define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq)
39 #define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq)
41 #define UIC_HANDLERS(n) \
42 static void ppc4xx_uic##n##_enable(unsigned int irq) \
44 ppc_cached_irq_mask[n] |= IRQ_MASK_UIC##n(irq); \
45 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
48 static void ppc4xx_uic##n##_disable(unsigned int irq) \
50 ppc_cached_irq_mask[n] &= ~IRQ_MASK_UIC##n(irq); \
51 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
55 static void ppc4xx_uic##n##_ack(unsigned int irq) \
57 u32 mask = IRQ_MASK_UIC##n(irq); \
58 ppc_cached_irq_mask[n] &= ~mask; \
59 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
60 mtdcr(DCRN_UIC_SR(UIC##n), mask); \
64 static void ppc4xx_uic##n##_end(unsigned int irq) \
66 unsigned int status = irq_desc[irq].status; \
67 u32 mask = IRQ_MASK_UIC##n(irq); \
68 if (status & IRQ_LEVEL) { \
69 mtdcr(DCRN_UIC_SR(UIC##n), mask); \
72 if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) { \
73 ppc_cached_irq_mask[n] |= mask; \
74 mtdcr(DCRN_UIC_ER(UIC##n), ppc_cached_irq_mask[n]); \
78 #define DECLARE_UIC(n) \
80 .typename = "UIC"#n, \
81 .enable = ppc4xx_uic##n##_enable, \
82 .disable = ppc4xx_uic##n##_disable, \
83 .ack = ppc4xx_uic##n##_ack, \
84 .end = ppc4xx_uic##n##_end, \
88 #define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC);
89 #define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
90 #define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC);
95 static int ppc4xx_pic_get_irq(struct pt_regs *regs)
97 u32 uicb = mfdcr(DCRN_UIC_MSR(UICB));
98 if (uicb & UICB_UIC0NC)
99 return 32 - ffs(mfdcr(DCRN_UIC_MSR(UIC0)));
100 else if (uicb & UICB_UIC1NC)
101 return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
102 else if (uicb & UICB_UIC2NC)
103 return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2)));
108 static void __init ppc4xx_pic_impl_init(void)
110 /* Configure Base UIC */
111 mtdcr(DCRN_UIC_CR(UICB), 0);
112 mtdcr(DCRN_UIC_TR(UICB), 0);
113 mtdcr(DCRN_UIC_PR(UICB), 0xffffffff);
114 mtdcr(DCRN_UIC_SR(UICB), 0xffffffff);
115 mtdcr(DCRN_UIC_ER(UICB), UICB_UIC0NC | UICB_UIC1NC | UICB_UIC2NC);
119 #define ACK_UIC0_PARENT
120 #define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
124 static int ppc4xx_pic_get_irq(struct pt_regs *regs)
126 u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
127 if (uic0 & UIC0_UIC1NC)
128 return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1)));
130 return uic0 ? 32 - ffs(uic0) : -1;
133 static void __init ppc4xx_pic_impl_init(void)
135 /* Enable cascade interrupt in UIC0 */
136 ppc_cached_irq_mask[0] |= UIC0_UIC1NC;
137 mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC);
138 mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]);
142 #define ACK_UIC0_PARENT
145 static int ppc4xx_pic_get_irq(struct pt_regs *regs)
147 u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0));
148 return uic0 ? 32 - ffs(uic0) : -1;
151 static inline void ppc4xx_pic_impl_init(void)
156 static struct ppc4xx_uic_impl {
157 struct hw_interrupt_type decl;
158 int base; /* Base DCR number */
160 { .decl = DECLARE_UIC(0), .base = UIC0 },
162 { .decl = DECLARE_UIC(1), .base = UIC1 },
164 { .decl = DECLARE_UIC(2), .base = UIC2 },
169 static inline int is_level_sensitive(int irq)
171 u32 tr = mfdcr(DCRN_UIC_TR(__uic[irq >> 5].base));
172 return (tr & IRQ_MASK_UICx(irq)) == 0;
175 void __init ppc4xx_pic_init(void)
178 unsigned char *eirqs = ppc4xx_uic_ext_irq_cfg;
180 for (i = 0; i < NR_UICS; ++i) {
181 int base = __uic[i].base;
183 /* Disable everything by default */
184 ppc_cached_irq_mask[i] = 0;
185 mtdcr(DCRN_UIC_ER(base), 0);
187 /* We don't use critical interrupts */
188 mtdcr(DCRN_UIC_CR(base), 0);
190 /* Configure polarity and triggering */
191 if (ppc4xx_core_uic_cfg) {
192 struct ppc4xx_uic_settings *p = ppc4xx_core_uic_cfg + i;
193 u32 mask = p->ext_irq_mask;
194 u32 pr = mfdcr(DCRN_UIC_PR(base)) & mask;
195 u32 tr = mfdcr(DCRN_UIC_TR(base)) & mask;
197 /* "Fixed" interrupts (on-chip devices) */
198 pr |= p->polarity & ~mask;
199 tr |= p->triggering & ~mask;
201 /* Merge external IRQs settings if board port
208 /* Extract current external IRQ mask */
209 u32 eirq_mask = 1 << __ilog2(mask);
211 if (!(*eirqs & IRQ_SENSE_LEVEL))
214 if (*eirqs & IRQ_POLARITY_POSITIVE)
221 mtdcr(DCRN_UIC_PR(base), pr);
222 mtdcr(DCRN_UIC_TR(base), tr);
225 /* ACK any pending interrupts to prevent false
226 * triggering after first enable
228 mtdcr(DCRN_UIC_SR(base), 0xffffffff);
231 /* Perform optional implementation specific setup
232 * (e.g. enable cascade interrupts for multi-UIC configurations)
234 ppc4xx_pic_impl_init();
236 /* Attach low-level handlers */
237 for (i = 0; i < (NR_UICS << 5); ++i) {
238 irq_desc[i].handler = &__uic[i >> 5].decl;
239 if (is_level_sensitive(i))
240 irq_desc[i].status |= IRQ_LEVEL;
243 ppc_md.get_irq = ppc4xx_pic_get_irq;