2 * arch/ppc/kernel/misc.S
6 * This file contains miscellaneous low-level functions.
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
11 * Adapted for iSeries by Mike Corrigan (mikejc@us.ibm.com)
12 * PPC64 updates by Dave Engebretsen (engebret@us.ibm.com)
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
21 #include <linux/config.h>
22 #include <linux/sys.h>
23 #include <asm/unistd.h>
24 #include <asm/errno.h>
25 #include <asm/processor.h>
27 #include <asm/cache.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cputable.h>
31 #include <asm/thread_info.h>
36 * Returns (address we were linked at) - (address we are running at)
37 * for use before the text and data are mapped to KERNELBASE.
69 #ifdef CONFIG_IRQSTACKS
70 _GLOBAL(call_do_softirq)
73 stdu r1,THREAD_SIZE-112(r3)
81 _GLOBAL(call_handle_IRQ_event)
84 stdu r1,THREAD_SIZE-112(r6)
91 #endif /* CONFIG_IRQSTACKS */
94 * To be called by C code which needs to do some operations with MMU
95 * disabled. Note that interrupts have to be disabled by the caller
96 * prior to calling us. The code called _MUST_ be in the RMO of course
97 * and part of the linear mapping as we don't attempt to translate the
98 * stack pointer at all. The function is called with the stack switched
99 * to this CPU emergency stack
101 * prototype is void *call_with_mmu_off(void *func, void *data);
103 * the called function is expected to be of the form
105 * void *called(void *data);
107 _GLOBAL(call_with_mmu_off)
108 mflr r0 /* get link, save it on stackframe */
110 mr r1,r5 /* save old stack ptr */
111 ld r1,PACAEMERGSP(r13) /* get emerg. stack */
112 subi r1,r1,STACK_FRAME_OVERHEAD
113 std r0,16(r1) /* save link on emerg. stack */
114 std r5,0(r1) /* save old stack ptr in backchain */
115 ld r3,0(r3) /* get to real function ptr (assume same TOC) */
116 bl 2f /* we need LR to return, continue at label 2 */
118 ld r0,16(r1) /* we return here from the call, get LR and */
119 ld r1,0(r1) /* .. old stack ptr */
120 mtspr SPRN_SRR0,r0 /* and get back to virtual mode with these */
122 ori r4,r4,MSR_IR|MSR_DR
126 2: mtspr SPRN_SRR0,r3 /* coming from above, enter real mode */
127 mr r3,r4 /* get parameter */
129 ori r0,r0,MSR_IR|MSR_DR
130 xori r0,r0,MSR_IR|MSR_DR
137 .tc ppc64_caches[TC],ppc64_caches
141 * Write any modified data cache blocks out to memory
142 * and invalidate the corresponding instruction cache blocks.
144 * flush_icache_range(unsigned long start, unsigned long stop)
146 * flush all bytes from start through stop-1 inclusive
149 _KPROBE(__flush_icache_range)
152 * Flush the data cache to memory
154 * Different systems have different cache line sizes
155 * and in some cases i-cache and d-cache line sizes differ from
158 ld r10,PPC64_CACHES@toc(r2)
159 lwz r7,DCACHEL1LINESIZE(r10)/* Get cache line size */
161 andc r6,r3,r5 /* round low to line bdy */
162 subf r8,r6,r4 /* compute length */
163 add r8,r8,r5 /* ensure we get enough */
164 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of cache line size */
165 srw. r8,r8,r9 /* compute line count */
166 beqlr /* nothing to do? */
173 /* Now invalidate the instruction cache */
175 lwz r7,ICACHEL1LINESIZE(r10) /* Get Icache line size */
177 andc r6,r3,r5 /* round low to line bdy */
178 subf r8,r6,r4 /* compute length */
180 lwz r9,ICACHEL1LOGLINESIZE(r10) /* Get log-2 of Icache line size */
181 srw. r8,r8,r9 /* compute line count */
182 beqlr /* nothing to do? */
191 * Like above, but only do the D-cache.
193 * flush_dcache_range(unsigned long start, unsigned long stop)
195 * flush all bytes from start to stop-1 inclusive
197 _GLOBAL(flush_dcache_range)
200 * Flush the data cache to memory
202 * Different systems have different cache line sizes
204 ld r10,PPC64_CACHES@toc(r2)
205 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
207 andc r6,r3,r5 /* round low to line bdy */
208 subf r8,r6,r4 /* compute length */
209 add r8,r8,r5 /* ensure we get enough */
210 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
211 srw. r8,r8,r9 /* compute line count */
212 beqlr /* nothing to do? */
221 * Like above, but works on non-mapped physical addresses.
222 * Use only for non-LPAR setups ! It also assumes real mode
223 * is cacheable. Used for flushing out the DART before using
224 * it as uncacheable memory
226 * flush_dcache_phys_range(unsigned long start, unsigned long stop)
228 * flush all bytes from start to stop-1 inclusive
230 _GLOBAL(flush_dcache_phys_range)
231 ld r10,PPC64_CACHES@toc(r2)
232 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
234 andc r6,r3,r5 /* round low to line bdy */
235 subf r8,r6,r4 /* compute length */
236 add r8,r8,r5 /* ensure we get enough */
237 lwz r9,DCACHEL1LOGLINESIZE(r10) /* Get log-2 of dcache line size */
238 srw. r8,r8,r9 /* compute line count */
239 beqlr /* nothing to do? */
240 mfmsr r5 /* Disable MMU Data Relocation */
253 mtmsr r5 /* Re-enable MMU Data Relocation */
258 _GLOBAL(flush_inval_dcache_range)
259 ld r10,PPC64_CACHES@toc(r2)
260 lwz r7,DCACHEL1LINESIZE(r10) /* Get dcache line size */
262 andc r6,r3,r5 /* round low to line bdy */
263 subf r8,r6,r4 /* compute length */
264 add r8,r8,r5 /* ensure we get enough */
265 lwz r9,DCACHEL1LOGLINESIZE(r10)/* Get log-2 of dcache line size */
266 srw. r8,r8,r9 /* compute line count */
267 beqlr /* nothing to do? */
280 * Flush a particular page from the data cache to RAM.
281 * Note: this is necessary because the instruction cache does *not*
282 * snoop from the data cache.
284 * void __flush_dcache_icache(void *page)
286 _GLOBAL(__flush_dcache_icache)
288 * Flush the data cache to memory
290 * Different systems have different cache line sizes
293 /* Flush the dcache */
294 ld r7,PPC64_CACHES@toc(r2)
295 clrrdi r3,r3,PAGE_SHIFT /* Page align */
296 lwz r4,DCACHEL1LINESPERPAGE(r7) /* Get # dcache lines per page */
297 lwz r5,DCACHEL1LINESIZE(r7) /* Get dcache line size */
305 /* Now invalidate the icache */
307 lwz r4,ICACHEL1LINESPERPAGE(r7) /* Get # icache lines per page */
308 lwz r5,ICACHEL1LINESIZE(r7) /* Get icache line size */
317 * I/O string operations
319 * insb(port, buf, len)
320 * outsb(port, buf, len)
321 * insw(port, buf, len)
322 * outsw(port, buf, len)
323 * insl(port, buf, len)
324 * outsl(port, buf, len)
325 * insw_ns(port, buf, len)
326 * outsw_ns(port, buf, len)
327 * insl_ns(port, buf, len)
328 * outsl_ns(port, buf, len)
330 * The *_ns versions don't do byte-swapping.
404 /* _GLOBAL(ide_insw) now in drivers/ide/ide-iops.c */
418 /* _GLOBAL(ide_outsw) now in drivers/ide/ide-iops.c */
455 * identify_cpu and calls setup_cpu
456 * In: r3 = base of the cpu_specs array
457 * r4 = address of cur_cpu_spec
458 * r5 = relocation offset
460 _GLOBAL(identify_cpu)
463 lwz r8,CPU_SPEC_PVR_MASK(r3)
465 lwz r9,CPU_SPEC_PVR_VALUE(r3)
468 addi r3,r3,CPU_SPEC_ENTRY_SIZE
473 ld r4,CPU_SPEC_SETUP(r3)
478 /* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */
484 * do_cpu_ftr_fixups - goes through the list of CPU feature fixups
485 * and writes nop's over sections of code that don't apply for this cpu.
486 * r3 = data offset (not changed)
488 _GLOBAL(do_cpu_ftr_fixups)
489 /* Get CPU 0 features */
490 LOADADDR(r6,cur_cpu_spec)
494 ld r4,CPU_SPEC_FEATURES(r4)
495 /* Get the fixup table */
496 LOADADDR(r6,__start___ftr_fixup)
498 LOADADDR(r7,__stop___ftr_fixup)
504 ld r8,-32(r6) /* mask */
506 ld r9,-24(r6) /* value */
509 ld r8,-16(r6) /* section begin */
510 ld r9,-8(r6) /* section end */
513 /* write nops over the section of code */
514 /* todo: if large section, add a branch at the start of it */
518 lis r0,0x60000000@h /* nop */
520 andi. r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
522 dcbst 0,r8 /* suboptimal, but simpler */
527 sync /* additional sync needed on g4 */
531 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
533 * Do an IO access in real mode
564 * Do an IO access in real mode
593 #endif /* defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE) */
596 * SCOM access functions for 970 (FX only for now)
598 * unsigned long scom970_read(unsigned int address);
599 * void scom970_write(unsigned int address, unsigned long value);
601 * The address passed in is the 24 bits register address. This code
602 * is 970 specific and will not check the status bits, so you should
603 * know what you are doing.
605 _GLOBAL(scom970_read)
612 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
613 * (including parity). On current CPUs they must be 0'd,
614 * and finally or in RW bit
619 /* do the actual scom read */
628 /* XXX: fixup result on some buggy 970's (ouch ! we lost a bit, bah
629 * that's the best we can do). Not implemented yet as we don't use
630 * the scom on any of the bogus CPUs yet, but may have to be done
634 /* restore interrupts */
639 _GLOBAL(scom970_write)
646 /* rotate 24 bits SCOM address 8 bits left and mask out it's low 8 bits
647 * (including parity). On current CPUs they must be 0'd.
653 mtspr SPRN_SCOMD,r4 /* write data */
655 mtspr SPRN_SCOMC,r3 /* write command */
660 /* restore interrupts */
666 * Create a kernel thread
667 * kernel_thread(fn, arg, flags)
669 _GLOBAL(kernel_thread)
672 stdu r1,-STACK_FRAME_OVERHEAD(r1)
675 ori r3,r5,CLONE_VM /* flags */
676 oris r3,r3,(CLONE_UNTRACED>>16)
677 li r4,0 /* new sp (unused) */
680 cmpdi 0,r3,0 /* parent or child? */
681 bne 1f /* return if parent */
683 stdu r0,-STACK_FRAME_OVERHEAD(r1)
686 mtlr r29 /* fn addr in lr */
687 mr r3,r30 /* load arg and call fn */
689 li r0,__NR_exit /* exit after child exits */
692 1: addi r1,r1,STACK_FRAME_OVERHEAD
698 * disable_kernel_fp()
701 _GLOBAL(disable_kernel_fp)
703 rldicl r0,r3,(63-MSR_FP_LG),1
704 rldicl r3,r0,(MSR_FP_LG+1),0
705 mtmsrd r3 /* disable use of fpu now */
709 #ifdef CONFIG_ALTIVEC
711 #if 0 /* this has no callers for now */
713 * disable_kernel_altivec()
716 _GLOBAL(disable_kernel_altivec)
718 rldicl r0,r3,(63-MSR_VEC_LG),1
719 rldicl r3,r0,(MSR_VEC_LG+1),0
720 mtmsrd r3 /* disable use of VMX now */
726 * giveup_altivec(tsk)
727 * Disable VMX for the task given as the argument,
728 * and save the vector registers in its thread_struct.
729 * Enables the VMX for use in the kernel on return.
731 _GLOBAL(giveup_altivec)
734 mtmsrd r5 /* enable use of VMX now */
737 beqlr- /* if no previous owner, done */
738 addi r3,r3,THREAD /* want THREAD of task */
746 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
748 andc r4,r4,r3 /* disable FP for previous task */
749 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
753 ld r4,last_task_used_altivec@got(r2)
755 #endif /* CONFIG_SMP */
758 #endif /* CONFIG_ALTIVEC */
760 _GLOBAL(__setup_cpu_power3)
770 /* kexec_wait(phys_cpu)
772 * wait for the flag to change, indicating this kernel is going away but
773 * the slave code for the next one is at addresses 0 to 100.
775 * This is used by all slaves.
777 * Physical (hardware) cpu id should be in r3.
782 addi r5,r5,kexec_flag-1b
785 #ifdef CONFIG_KEXEC /* use no memory without kexec */
792 /* this can be in text because we won't change it until we are
793 * running in real anyways
801 /* kexec_smp_wait(void)
803 * call with interrupts off
804 * note: this is a terminal routine, it does not save lr
806 * get phys id from paca
807 * set paca id to -1 to say we got here
808 * switch to real mode
809 * join other cpus in kexec_wait(phys_id)
811 _GLOBAL(kexec_smp_wait)
812 lhz r3,PACAHWCPUID(r13)
814 sth r4,PACAHWCPUID(r13) /* let others know we left */
819 * switch to real mode (turn mmu off)
820 * we use the early kernel trick that the hardware ignores bits
821 * 0 and 1 (big endian) of the effective address in real mode
823 * don't overwrite r3 here, it is live for kexec_wait above.
825 real_mode: /* assume normal blr return */
828 mflr r11 /* return address to SRR0 */
840 * kexec_sequence(newstack, start, image, control, clear_all())
842 * does the grungy work with stack switching and real mode switches
843 * also does simple calls to other code
846 _GLOBAL(kexec_sequence)
850 /* switch stacks to newstack -- &kexec_stack.stack */
851 stdu r1,THREAD_SIZE-112(r3)
857 /* save regs for local vars on new stack.
858 * yes, we won't go back, but ...
870 /* save args into preserved regs */
871 mr r31,r3 /* newstack (both) */
872 mr r30,r4 /* start (real) */
873 mr r29,r5 /* image (virt) */
874 mr r28,r6 /* control, unused */
875 mr r27,r7 /* clear_all() fn desc */
876 mr r26,r8 /* spare */
877 lhz r25,PACAHWCPUID(r13) /* get our phys cpu from paca */
879 /* disable interrupts, we are overwriting kernel data next */
884 /* copy dest pages, flush whole dest image */
886 bl .kexec_copy_flush /* (image) */
891 /* clear out hardware hash page table and tlb */
892 ld r5,0(r27) /* deref function descriptor */
894 bctrl /* ppc_md.hash_clear_all(void); */
897 * kexec image calling is:
898 * the first 0x100 bytes of the entry point are copied to 0
900 * all slaves branch to slave = 0x60 (absolute)
901 * slave(phys_cpu_id);
903 * master goes to start = entry point
904 * start(phys_cpu_id, start, 0);
907 * a wrapper is needed to call existing kernels, here is an approximate
908 * description of one method:
911 * start will be near the boot_block (maybe 0x100 bytes before it?)
912 * it will have a 0x60, which will b to boot_block, where it will wait
913 * and 0 will store phys into struct boot-block and load r3 from there,
914 * copy kernel 0-0x100 and tell slaves to back down to 0x60 again
917 * boot block will have all cpus scanning device tree to see if they
918 * are the boot cpu ?????
919 * other device tree differences (prop sizes, va vs pa, etc)...
922 /* copy 0x100 bytes starting at start to 0 */
927 bl .copy_and_flush /* (dest, src, copy limit, start offset) */
928 1: /* assume normal blr return */
930 /* release other cpus to the new kernel secondary start at 0x60 */
933 stw r6,kexec_flag-1b(5)
934 mr r3,r25 # my phys cpu
935 mr r4,r30 # start, aka phys mem offset
938 blr /* image->start(physid, image->start, 0); */
939 #endif /* CONFIG_KEXEC */