2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
24 #include <linux/syscalls.h>
26 #include <asm/processor.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/byteorder.h>
32 #include <asm/machdep.h>
38 #define DBG(fmt...) udbg_printf(fmt)
43 unsigned long pci_probe_only = 1;
44 unsigned long pci_assign_all_buses = 0;
47 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
48 * devices we don't have access to.
50 unsigned long io_page_mask;
52 EXPORT_SYMBOL(io_page_mask);
54 #ifdef CONFIG_PPC_MULTIPLATFORM
55 static void fixup_resource(struct resource *res, struct pci_dev *dev);
56 static void do_bus_setup(struct pci_bus *bus);
59 unsigned int pcibios_assign_all_busses(void)
61 return pci_assign_all_buses;
64 /* pci_io_base -- the base address from which io bars are offsets.
65 * This is the lowest I/O base address (so bar values are always positive),
66 * and it *must* be the start of ISA space if an ISA bus exists because
67 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
68 * page is mapped and isa_io_limit prevents access to it.
70 unsigned long isa_io_base; /* NULL if no ISA bus */
71 EXPORT_SYMBOL(isa_io_base);
72 unsigned long pci_io_base;
73 EXPORT_SYMBOL(pci_io_base);
75 void iSeries_pcibios_init(void);
79 struct dma_mapping_ops pci_dma_ops;
80 EXPORT_SYMBOL(pci_dma_ops);
82 int global_phb_number; /* Global phb counter */
84 /* Cached ISA bridge dev. */
85 struct pci_dev *ppc64_isabridge_dev = NULL;
87 static void fixup_broken_pcnet32(struct pci_dev* dev)
89 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
90 dev->vendor = PCI_VENDOR_ID_AMD;
91 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
94 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
96 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
99 unsigned long offset = 0;
100 struct pci_controller *hose = pci_bus_to_host(dev->bus);
105 if (res->flags & IORESOURCE_IO)
106 offset = (unsigned long)hose->io_base_virt - pci_io_base;
108 if (res->flags & IORESOURCE_MEM)
109 offset = hose->pci_mem_offset;
111 region->start = res->start - offset;
112 region->end = res->end - offset;
115 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
116 struct pci_bus_region *region)
118 unsigned long offset = 0;
119 struct pci_controller *hose = pci_bus_to_host(dev->bus);
124 if (res->flags & IORESOURCE_IO)
125 offset = (unsigned long)hose->io_base_virt - pci_io_base;
127 if (res->flags & IORESOURCE_MEM)
128 offset = hose->pci_mem_offset;
130 res->start = region->start + offset;
131 res->end = region->end + offset;
134 #ifdef CONFIG_HOTPLUG
135 EXPORT_SYMBOL(pcibios_resource_to_bus);
136 EXPORT_SYMBOL(pcibios_bus_to_resource);
140 * We need to avoid collisions with `mirrored' VGA ports
141 * and other strange ISA hardware, so we always want the
142 * addresses to be allocated in the 0x000-0x0ff region
145 * Why? Because some silly external IO cards only decode
146 * the low 10 bits of the IO address. The 0x00-0xff region
147 * is reserved for motherboard devices that decode all 16
148 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
149 * but we want to try to avoid allocating at 0x2900-0x2bff
150 * which might have be mirrored at 0x0100-0x03ff..
152 void pcibios_align_resource(void *data, struct resource *res,
153 unsigned long size, unsigned long align)
155 struct pci_dev *dev = data;
156 struct pci_controller *hose = pci_bus_to_host(dev->bus);
157 unsigned long start = res->start;
158 unsigned long alignto;
160 if (res->flags & IORESOURCE_IO) {
161 unsigned long offset = (unsigned long)hose->io_base_virt -
163 /* Make sure we start at our min on all hoses */
164 if (start - offset < PCIBIOS_MIN_IO)
165 start = PCIBIOS_MIN_IO + offset;
168 * Put everything into 0x00-0xff region modulo 0x400
171 start = (start + 0x3ff) & ~0x3ff;
173 } else if (res->flags & IORESOURCE_MEM) {
174 /* Make sure we start at our min on all hoses */
175 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
176 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
178 /* Align to multiple of size of minimum base. */
179 alignto = max(0x1000UL, align);
180 start = ALIGN(start, alignto);
186 static DEFINE_SPINLOCK(hose_spinlock);
189 * pci_controller(phb) initialized common variables.
191 void __devinit pci_setup_pci_controller(struct pci_controller *hose)
193 memset(hose, 0, sizeof(struct pci_controller));
195 spin_lock(&hose_spinlock);
196 hose->global_number = global_phb_number++;
197 list_add_tail(&hose->list_node, &hose_list);
198 spin_unlock(&hose_spinlock);
201 static void __init pcibios_claim_one_bus(struct pci_bus *b)
204 struct pci_bus *child_bus;
206 list_for_each_entry(dev, &b->devices, bus_list) {
209 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
210 struct resource *r = &dev->resource[i];
212 if (r->parent || !r->start || !r->flags)
214 pci_claim_resource(dev, i);
218 list_for_each_entry(child_bus, &b->children, node)
219 pcibios_claim_one_bus(child_bus);
222 #ifndef CONFIG_PPC_ISERIES
223 static void __init pcibios_claim_of_setup(void)
227 list_for_each_entry(b, &pci_root_buses, node)
228 pcibios_claim_one_bus(b);
232 #ifdef CONFIG_PPC_MULTIPLATFORM
233 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
238 prop = (u32 *) get_property(np, name, &len);
239 if (prop && len >= 4)
244 static unsigned int pci_parse_of_flags(u32 addr0)
246 unsigned int flags = 0;
248 if (addr0 & 0x02000000) {
249 flags |= IORESOURCE_MEM;
250 if (addr0 & 0x40000000)
251 flags |= IORESOURCE_PREFETCH;
252 } else if (addr0 & 0x01000000)
253 flags |= IORESOURCE_IO;
257 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
259 static void pci_parse_of_addrs(struct device_node *node, struct pci_dev *dev)
263 struct resource *res;
267 addrs = (u32 *) get_property(node, "assigned-addresses", &proplen);
270 for (; proplen >= 20; proplen -= 20, addrs += 5) {
271 flags = pci_parse_of_flags(addrs[0]);
274 base = GET_64BIT(addrs, 1);
275 size = GET_64BIT(addrs, 3);
279 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
280 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
281 } else if (i == dev->rom_base_reg) {
282 res = &dev->resource[PCI_ROM_RESOURCE];
283 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
285 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
289 res->end = base + size - 1;
291 res->name = pci_name(dev);
292 fixup_resource(res, dev);
296 static struct pci_dev *of_create_pci_dev(struct device_node *node,
297 struct pci_bus *bus, int devfn)
302 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
305 type = get_property(node, "device_type", NULL);
309 memset(dev, 0, sizeof(struct pci_dev));
312 dev->dev.parent = bus->bridge;
313 dev->dev.bus = &pci_bus_type;
315 dev->multifunction = 0; /* maybe a lie? */
317 dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
318 dev->device = get_int_prop(node, "device-id", 0xffff);
319 dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
320 dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
322 dev->cfg_size = 256; /*pci_cfg_space_size(dev);*/
324 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
325 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
326 dev->class = get_int_prop(node, "class-code", 0);
328 dev->current_state = 4; /* unknown power state */
330 if (!strcmp(type, "pci")) {
331 /* a PCI-PCI bridge */
332 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
333 dev->rom_base_reg = PCI_ROM_ADDRESS1;
334 } else if (!strcmp(type, "cardbus")) {
335 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
337 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
338 dev->rom_base_reg = PCI_ROM_ADDRESS;
340 if (node->n_intrs > 0) {
341 dev->irq = node->intrs[0].line;
342 pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
347 pci_parse_of_addrs(node, dev);
349 pci_device_add(dev, bus);
351 /* XXX pci_scan_msi_device(dev); */
356 static void of_scan_pci_bridge(struct device_node *node, struct pci_dev *dev);
358 static void __devinit of_scan_bus(struct device_node *node,
361 struct device_node *child = NULL;
366 while ((child = of_get_next_child(node, child)) != NULL) {
367 reg = (u32 *) get_property(child, "reg", ®len);
368 if (reg == NULL || reglen < 20)
370 devfn = (reg[0] >> 8) & 0xff;
371 /* create a new pci_dev for this device */
372 dev = of_create_pci_dev(child, bus, devfn);
375 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
376 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
377 of_scan_pci_bridge(child, dev);
383 static void __devinit of_scan_pci_bridge(struct device_node *node,
387 u32 *busrange, *ranges;
389 struct resource *res;
393 /* parse bus-range property */
394 busrange = (u32 *) get_property(node, "bus-range", &len);
395 if (busrange == NULL || len != 8) {
396 printk(KERN_ERR "Can't get bus-range for PCI-PCI bridge %s\n",
400 ranges = (u32 *) get_property(node, "ranges", &len);
401 if (ranges == NULL) {
402 printk(KERN_ERR "Can't get ranges for PCI-PCI bridge %s\n",
407 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
409 printk(KERN_ERR "Failed to create pci bus for %s\n",
414 bus->primary = dev->bus->number;
415 bus->subordinate = busrange[1];
419 /* parse ranges property */
420 /* PCI #address-cells == 3 and #size-cells == 2 always */
421 res = &dev->resource[PCI_BRIDGE_RESOURCES];
422 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
424 bus->resource[i] = res;
428 for (; len >= 32; len -= 32, ranges += 8) {
429 flags = pci_parse_of_flags(ranges[0]);
430 size = GET_64BIT(ranges, 6);
431 if (flags == 0 || size == 0)
433 if (flags & IORESOURCE_IO) {
434 res = bus->resource[0];
436 printk(KERN_ERR "PCI: ignoring extra I/O range"
437 " for bridge %s\n", node->full_name);
441 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
442 printk(KERN_ERR "PCI: too many memory ranges"
443 " for bridge %s\n", node->full_name);
446 res = bus->resource[i];
449 res->start = GET_64BIT(ranges, 1);
450 res->end = res->start + size - 1;
452 fixup_resource(res, dev);
454 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
457 mode = PCI_PROBE_NORMAL;
458 if (ppc_md.pci_probe_mode)
459 mode = ppc_md.pci_probe_mode(bus);
460 if (mode == PCI_PROBE_DEVTREE)
461 of_scan_bus(node, bus);
462 else if (mode == PCI_PROBE_NORMAL)
463 pci_scan_child_bus(bus);
465 #endif /* CONFIG_PPC_MULTIPLATFORM */
467 static void __devinit scan_phb(struct pci_controller *hose)
470 struct device_node *node = hose->arch_data;
472 struct resource *res;
474 bus = pci_create_bus(NULL, hose->first_busno, hose->ops, node);
476 printk(KERN_ERR "Failed to create bus for PCI domain %04x\n",
477 hose->global_number);
480 bus->secondary = hose->first_busno;
483 bus->resource[0] = res = &hose->io_resource;
484 if (res->flags && request_resource(&ioport_resource, res))
485 printk(KERN_ERR "Failed to request PCI IO region "
486 "on PCI domain %04x\n", hose->global_number);
488 for (i = 0; i < 3; ++i) {
489 res = &hose->mem_resources[i];
490 bus->resource[i+1] = res;
491 if (res->flags && request_resource(&iomem_resource, res))
492 printk(KERN_ERR "Failed to request PCI memory region "
493 "on PCI domain %04x\n", hose->global_number);
496 mode = PCI_PROBE_NORMAL;
497 #ifdef CONFIG_PPC_MULTIPLATFORM
498 if (ppc_md.pci_probe_mode)
499 mode = ppc_md.pci_probe_mode(bus);
500 if (mode == PCI_PROBE_DEVTREE) {
501 bus->subordinate = hose->last_busno;
502 of_scan_bus(node, bus);
504 #endif /* CONFIG_PPC_MULTIPLATFORM */
505 if (mode == PCI_PROBE_NORMAL)
506 hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
507 pci_bus_add_devices(bus);
510 static int __init pcibios_init(void)
512 struct pci_controller *hose, *tmp;
514 /* For now, override phys_mem_access_prot. If we need it,
515 * later, we may move that initialization to each ppc_md
517 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
519 #ifdef CONFIG_PPC_ISERIES
520 iSeries_pcibios_init();
523 printk("PCI: Probing PCI hardware\n");
525 /* Scan all of the recorded PCI controllers. */
526 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
529 #ifndef CONFIG_PPC_ISERIES
531 pcibios_claim_of_setup();
533 /* FIXME: `else' will be removed when
534 pci_assign_unassigned_resources() is able to work
535 correctly with [partially] allocated PCI tree. */
536 pci_assign_unassigned_resources();
537 #endif /* !CONFIG_PPC_ISERIES */
539 /* Call machine dependent final fixup */
540 if (ppc_md.pcibios_fixup)
541 ppc_md.pcibios_fixup();
543 /* Cache the location of the ISA bridge (if we have one) */
544 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
545 if (ppc64_isabridge_dev != NULL)
546 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
548 printk("PCI: Probing PCI hardware done\n");
553 subsys_initcall(pcibios_init);
555 char __init *pcibios_setup(char *str)
560 int pcibios_enable_device(struct pci_dev *dev, int mask)
565 pci_read_config_word(dev, PCI_COMMAND, &cmd);
568 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
569 struct resource *res = &dev->resource[i];
571 /* Only set up the requested stuff */
572 if (!(mask & (1<<i)))
575 if (res->flags & IORESOURCE_IO)
576 cmd |= PCI_COMMAND_IO;
577 if (res->flags & IORESOURCE_MEM)
578 cmd |= PCI_COMMAND_MEMORY;
582 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
584 /* Enable the appropriate bits in the PCI command register. */
585 pci_write_config_word(dev, PCI_COMMAND, cmd);
591 * Return the domain number for this bus.
593 int pci_domain_nr(struct pci_bus *bus)
595 #ifdef CONFIG_PPC_ISERIES
598 struct pci_controller *hose = pci_bus_to_host(bus);
600 return hose->global_number;
604 EXPORT_SYMBOL(pci_domain_nr);
606 /* Decide whether to display the domain number in /proc */
607 int pci_proc_domain(struct pci_bus *bus)
609 #ifdef CONFIG_PPC_ISERIES
612 struct pci_controller *hose = pci_bus_to_host(bus);
618 * Platform support for /proc/bus/pci/X/Y mmap()s,
619 * modelled on the sparc64 implementation by Dave Miller.
624 * Adjust vm_pgoff of VMA such that it is the physical page offset
625 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
627 * Basically, the user finds the base address for his device which he wishes
628 * to mmap. They read the 32-bit value from the config space base register,
629 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
630 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
632 * Returns negative error code on failure, zero on success.
634 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
635 unsigned long *offset,
636 enum pci_mmap_state mmap_state)
638 struct pci_controller *hose = pci_bus_to_host(dev->bus);
639 unsigned long io_offset = 0;
643 return NULL; /* should never happen */
645 /* If memory, add on the PCI bridge address offset */
646 if (mmap_state == pci_mmap_mem) {
647 *offset += hose->pci_mem_offset;
648 res_bit = IORESOURCE_MEM;
650 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
651 *offset += io_offset;
652 res_bit = IORESOURCE_IO;
656 * Check that the offset requested corresponds to one of the
657 * resources of the device.
659 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
660 struct resource *rp = &dev->resource[i];
661 int flags = rp->flags;
663 /* treat ROM as memory (should be already) */
664 if (i == PCI_ROM_RESOURCE)
665 flags |= IORESOURCE_MEM;
667 /* Active and same type? */
668 if ((flags & res_bit) == 0)
671 /* In the range of this resource? */
672 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
675 /* found it! construct the final physical address */
676 if (mmap_state == pci_mmap_io)
677 *offset += hose->io_base_phys - io_offset;
685 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
688 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
690 enum pci_mmap_state mmap_state,
693 unsigned long prot = pgprot_val(protection);
695 /* Write combine is always 0 on non-memory space mappings. On
696 * memory space, if the user didn't pass 1, we check for a
697 * "prefetchable" resource. This is a bit hackish, but we use
698 * this to workaround the inability of /sysfs to provide a write
701 if (mmap_state != pci_mmap_mem)
703 else if (write_combine == 0) {
704 if (rp->flags & IORESOURCE_PREFETCH)
708 /* XXX would be nice to have a way to ask for write-through */
709 prot |= _PAGE_NO_CACHE;
711 prot &= ~_PAGE_GUARDED;
713 prot |= _PAGE_GUARDED;
715 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
718 return __pgprot(prot);
722 * This one is used by /dev/mem and fbdev who have no clue about the
723 * PCI device, it tries to find the PCI device first and calls the
726 pgprot_t pci_phys_mem_access_prot(struct file *file,
727 unsigned long offset,
731 struct pci_dev *pdev = NULL;
732 struct resource *found = NULL;
733 unsigned long prot = pgprot_val(protection);
736 if (page_is_ram(offset >> PAGE_SHIFT))
737 return __pgprot(prot);
739 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
741 for_each_pci_dev(pdev) {
742 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
743 struct resource *rp = &pdev->resource[i];
744 int flags = rp->flags;
746 /* Active and same type? */
747 if ((flags & IORESOURCE_MEM) == 0)
749 /* In the range of this resource? */
750 if (offset < (rp->start & PAGE_MASK) ||
760 if (found->flags & IORESOURCE_PREFETCH)
761 prot &= ~_PAGE_GUARDED;
765 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
767 return __pgprot(prot);
772 * Perform the actual remap of the pages for a PCI device mapping, as
773 * appropriate for this architecture. The region in the process to map
774 * is described by vm_start and vm_end members of VMA, the base physical
775 * address is found in vm_pgoff.
776 * The pci device structure is provided so that architectures may make mapping
777 * decisions on a per-device or per-bus basis.
779 * Returns a negative error code on failure, zero on success.
781 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
782 enum pci_mmap_state mmap_state,
785 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
789 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
793 vma->vm_pgoff = offset >> PAGE_SHIFT;
794 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
795 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
797 mmap_state, write_combine);
799 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
800 vma->vm_end - vma->vm_start, vma->vm_page_prot);
805 #ifdef CONFIG_PPC_MULTIPLATFORM
806 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
808 struct pci_dev *pdev;
809 struct device_node *np;
811 pdev = to_pci_dev (dev);
812 np = pci_device_to_OF_node(pdev);
813 if (np == NULL || np->full_name == NULL)
815 return sprintf(buf, "%s", np->full_name);
817 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
818 #endif /* CONFIG_PPC_MULTIPLATFORM */
820 void pcibios_add_platform_entries(struct pci_dev *pdev)
822 #ifdef CONFIG_PPC_MULTIPLATFORM
823 device_create_file(&pdev->dev, &dev_attr_devspec);
824 #endif /* CONFIG_PPC_MULTIPLATFORM */
827 #ifdef CONFIG_PPC_MULTIPLATFORM
829 #define ISA_SPACE_MASK 0x1
830 #define ISA_SPACE_IO 0x1
832 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
833 unsigned long phb_io_base_phys,
834 void __iomem * phb_io_base_virt)
836 struct isa_range *range;
837 unsigned long pci_addr;
838 unsigned int isa_addr;
842 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
843 if (range == NULL || (rlen < sizeof(struct isa_range))) {
844 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
846 __ioremap_explicit(phb_io_base_phys,
847 (unsigned long)phb_io_base_virt,
848 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
852 /* From "ISA Binding to 1275"
853 * The ranges property is laid out as an array of elements,
854 * each of which comprises:
855 * cells 0 - 1: an ISA address
856 * cells 2 - 4: a PCI address
857 * (size depending on dev->n_addr_cells)
858 * cell 5: the size of the range
860 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
861 isa_addr = range->isa_addr.a_lo;
862 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
863 range->pci_addr.a_lo;
865 /* Assume these are both zero */
866 if ((pci_addr != 0) || (isa_addr != 0)) {
867 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
872 size = PAGE_ALIGN(range->size);
874 __ioremap_explicit(phb_io_base_phys,
875 (unsigned long) phb_io_base_virt,
876 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
880 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
881 struct device_node *dev)
883 unsigned int *ranges;
887 struct resource *res;
888 int np, na = prom_n_addr_cells(dev);
889 unsigned long pci_addr, cpu_phys_addr;
893 /* From "PCI Binding to 1275"
894 * The ranges property is laid out as an array of elements,
895 * each of which comprises:
896 * cells 0 - 2: a PCI address
897 * cells 3 or 3+4: a CPU physical address
898 * (size depending on dev->n_addr_cells)
899 * cells 4+5 or 5+6: the size of the range
902 hose->io_base_phys = 0;
903 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
904 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
906 pci_addr = (unsigned long)ranges[1] << 32 | ranges[2];
908 cpu_phys_addr = ranges[3];
910 cpu_phys_addr = cpu_phys_addr << 32 | ranges[4];
912 size = (unsigned long)ranges[na+3] << 32 | ranges[na+4];
915 switch ((ranges[0] >> 24) & 0x3) {
916 case 1: /* I/O space */
917 hose->io_base_phys = cpu_phys_addr;
918 hose->pci_io_size = size;
920 res = &hose->io_resource;
921 res->flags = IORESOURCE_IO;
922 res->start = pci_addr;
923 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
924 res->start, res->start + size - 1);
926 case 2: /* memory space */
928 while (memno < 3 && hose->mem_resources[memno].flags)
932 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
934 res = &hose->mem_resources[memno];
935 res->flags = IORESOURCE_MEM;
936 res->start = cpu_phys_addr;
937 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
938 res->start, res->start + size - 1);
943 res->name = dev->full_name;
944 res->end = res->start + size - 1;
953 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
955 unsigned long size = hose->pci_io_size;
956 unsigned long io_virt_offset;
957 struct resource *res;
958 struct device_node *isa_dn;
960 hose->io_base_virt = reserve_phb_iospace(size);
961 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
962 hose->global_number, hose->io_base_phys,
963 (unsigned long) hose->io_base_virt);
966 pci_io_base = (unsigned long)hose->io_base_virt;
967 isa_dn = of_find_node_by_type(NULL, "isa");
969 isa_io_base = pci_io_base;
970 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
978 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
979 res = &hose->io_resource;
980 res->start += io_virt_offset;
981 res->end += io_virt_offset;
984 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
987 unsigned long size = hose->pci_io_size;
988 unsigned long io_virt_offset;
989 struct resource *res;
991 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
992 _PAGE_NO_CACHE | _PAGE_GUARDED);
993 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
994 hose->global_number, hose->io_base_phys,
995 (unsigned long) hose->io_base_virt);
998 pci_io_base = (unsigned long)hose->io_base_virt;
1000 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
1001 res = &hose->io_resource;
1002 res->start += io_virt_offset;
1003 res->end += io_virt_offset;
1007 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
1008 unsigned long *start_virt, unsigned long *size)
1010 struct pci_controller *hose = pci_bus_to_host(bus);
1011 struct pci_bus_region region;
1012 struct resource *res;
1015 res = bus->resource[0];
1016 pcibios_resource_to_bus(bus->self, ®ion, res);
1017 *start_phys = hose->io_base_phys + region.start;
1018 *start_virt = (unsigned long) hose->io_base_virt +
1020 if (region.end > region.start)
1021 *size = region.end - region.start + 1;
1023 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1024 __FUNCTION__, region.start, region.end);
1030 res = &hose->io_resource;
1031 *start_phys = hose->io_base_phys;
1032 *start_virt = (unsigned long) hose->io_base_virt;
1033 if (res->end > res->start)
1034 *size = res->end - res->start + 1;
1036 printk("%s(): unexpected region 0x%lx->0x%lx\n",
1037 __FUNCTION__, res->start, res->end);
1045 int unmap_bus_range(struct pci_bus *bus)
1047 unsigned long start_phys;
1048 unsigned long start_virt;
1052 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1056 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1058 if (iounmap_explicit((void __iomem *) start_virt, size))
1063 EXPORT_SYMBOL(unmap_bus_range);
1065 int remap_bus_range(struct pci_bus *bus)
1067 unsigned long start_phys;
1068 unsigned long start_virt;
1072 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
1077 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
1079 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
1080 if (__ioremap_explicit(start_phys, start_virt, size,
1081 _PAGE_NO_CACHE | _PAGE_GUARDED))
1086 EXPORT_SYMBOL(remap_bus_range);
1088 void phbs_remap_io(void)
1090 struct pci_controller *hose, *tmp;
1092 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1093 remap_bus_range(hose->bus);
1097 * ppc64 can have multifunction devices that do not respond to function 0.
1098 * In this case we must scan all functions.
1099 * XXX this can go now, we use the OF device tree in all the
1100 * cases that caused problems. -- paulus
1102 int pcibios_scan_all_fns(struct pci_bus *bus, int devfn)
1107 static void __devinit fixup_resource(struct resource *res, struct pci_dev *dev)
1109 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1110 unsigned long start, end, mask, offset;
1112 if (res->flags & IORESOURCE_IO) {
1113 offset = (unsigned long)hose->io_base_virt - pci_io_base;
1115 start = res->start += offset;
1116 end = res->end += offset;
1118 /* Need to allow IO access to pages that are in the
1120 if (start < MAX_ISA_PORT) {
1121 if (end > MAX_ISA_PORT)
1124 start >>= PAGE_SHIFT;
1127 /* get the range of pages for the map */
1128 mask = ((1 << (end+1)) - 1) ^ ((1 << start) - 1);
1129 io_page_mask |= mask;
1131 } else if (res->flags & IORESOURCE_MEM) {
1132 res->start += hose->pci_mem_offset;
1133 res->end += hose->pci_mem_offset;
1137 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
1138 struct pci_bus *bus)
1140 /* Update device resources. */
1143 for (i = 0; i < PCI_NUM_RESOURCES; i++)
1144 if (dev->resource[i].flags)
1145 fixup_resource(&dev->resource[i], dev);
1147 EXPORT_SYMBOL(pcibios_fixup_device_resources);
1149 static void __devinit do_bus_setup(struct pci_bus *bus)
1151 struct pci_dev *dev;
1153 ppc_md.iommu_bus_setup(bus);
1155 list_for_each_entry(dev, &bus->devices, bus_list)
1156 ppc_md.iommu_dev_setup(dev);
1158 if (ppc_md.irq_bus_setup)
1159 ppc_md.irq_bus_setup(bus);
1162 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
1164 struct pci_dev *dev = bus->self;
1166 if (dev && pci_probe_only &&
1167 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1168 /* This is a subordinate bridge */
1170 pci_read_bridge_bases(bus);
1171 pcibios_fixup_device_resources(dev, bus);
1176 if (!pci_probe_only)
1179 list_for_each_entry(dev, &bus->devices, bus_list)
1180 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1181 pcibios_fixup_device_resources(dev, bus);
1183 EXPORT_SYMBOL(pcibios_fixup_bus);
1186 * Reads the interrupt pin to determine if interrupt is use by card.
1187 * If the interrupt is used, then gets the interrupt line from the
1188 * openfirmware and sets it in the pci_dev and pci_config line.
1190 int pci_read_irq_line(struct pci_dev *pci_dev)
1193 struct device_node *node;
1195 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
1199 node = pci_device_to_OF_node(pci_dev);
1203 if (node->n_intrs == 0)
1206 pci_dev->irq = node->intrs[0].line;
1208 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
1212 EXPORT_SYMBOL(pci_read_irq_line);
1214 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1215 const struct resource *rsrc,
1216 u64 *start, u64 *end)
1218 struct pci_controller *hose = pci_bus_to_host(dev->bus);
1219 unsigned long offset = 0;
1224 if (rsrc->flags & IORESOURCE_IO)
1225 offset = pci_io_base - (unsigned long)hose->io_base_virt +
1228 *start = rsrc->start + offset;
1229 *end = rsrc->end + offset;
1232 #endif /* CONFIG_PPC_MULTIPLATFORM */
1235 #define IOBASE_BRIDGE_NUMBER 0
1236 #define IOBASE_MEMORY 1
1238 #define IOBASE_ISA_IO 3
1239 #define IOBASE_ISA_MEM 4
1241 long sys_pciconfig_iobase(long which, unsigned long in_bus,
1242 unsigned long in_devfn)
1244 struct pci_controller* hose;
1245 struct list_head *ln;
1246 struct pci_bus *bus = NULL;
1247 struct device_node *hose_node;
1249 /* Argh ! Please forgive me for that hack, but that's the
1250 * simplest way to get existing XFree to not lockup on some
1251 * G5 machines... So when something asks for bus 0 io base
1252 * (bus 0 is HT root), we return the AGP one instead.
1254 #ifdef CONFIG_PPC_PMAC
1255 if (systemcfg->platform == PLATFORM_POWERMAC &&
1256 machine_is_compatible("MacRISC4"))
1259 #endif /* CONFIG_PPC_PMAC */
1261 /* That syscall isn't quite compatible with PCI domains, but it's
1262 * used on pre-domains setup. We return the first match
1265 for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
1266 bus = pci_bus_b(ln);
1267 if (in_bus >= bus->number && in_bus < (bus->number + bus->subordinate))
1271 if (bus == NULL || bus->sysdata == NULL)
1274 hose_node = (struct device_node *)bus->sysdata;
1275 hose = PCI_DN(hose_node)->phb;
1278 case IOBASE_BRIDGE_NUMBER:
1279 return (long)hose->first_busno;
1281 return (long)hose->pci_mem_offset;
1283 return (long)hose->io_base_phys;
1285 return (long)isa_io_base;
1286 case IOBASE_ISA_MEM: