2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
25 #include <asm/processor.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/byteorder.h>
31 #include <asm/machdep.h>
37 #define DBG(fmt...) udbg_printf(fmt)
42 unsigned long pci_probe_only = 1;
43 unsigned long pci_assign_all_buses = 0;
46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
47 * devices we don't have access to.
49 unsigned long io_page_mask;
51 EXPORT_SYMBOL(io_page_mask);
54 unsigned int pcibios_assign_all_busses(void)
56 return pci_assign_all_buses;
59 /* pci_io_base -- the base address from which io bars are offsets.
60 * This is the lowest I/O base address (so bar values are always positive),
61 * and it *must* be the start of ISA space if an ISA bus exists because
62 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
63 * page is mapped and isa_io_limit prevents access to it.
65 unsigned long isa_io_base; /* NULL if no ISA bus */
66 EXPORT_SYMBOL(isa_io_base);
67 unsigned long pci_io_base;
68 EXPORT_SYMBOL(pci_io_base);
70 void iSeries_pcibios_init(void);
74 struct dma_mapping_ops pci_dma_ops;
75 EXPORT_SYMBOL(pci_dma_ops);
77 int global_phb_number; /* Global phb counter */
79 /* Cached ISA bridge dev. */
80 struct pci_dev *ppc64_isabridge_dev = NULL;
82 static void fixup_broken_pcnet32(struct pci_dev* dev)
84 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
85 dev->vendor = PCI_VENDOR_ID_AMD;
86 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
89 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
91 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
94 unsigned long offset = 0;
95 struct pci_controller *hose = pci_bus_to_host(dev->bus);
100 if (res->flags & IORESOURCE_IO)
101 offset = (unsigned long)hose->io_base_virt - pci_io_base;
103 if (res->flags & IORESOURCE_MEM)
104 offset = hose->pci_mem_offset;
106 region->start = res->start - offset;
107 region->end = res->end - offset;
110 void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
111 struct pci_bus_region *region)
113 unsigned long offset = 0;
114 struct pci_controller *hose = pci_bus_to_host(dev->bus);
119 if (res->flags & IORESOURCE_IO)
120 offset = (unsigned long)hose->io_base_virt - pci_io_base;
122 if (res->flags & IORESOURCE_MEM)
123 offset = hose->pci_mem_offset;
125 res->start = region->start + offset;
126 res->end = region->end + offset;
129 #ifdef CONFIG_HOTPLUG
130 EXPORT_SYMBOL(pcibios_resource_to_bus);
131 EXPORT_SYMBOL(pcibios_bus_to_resource);
135 * We need to avoid collisions with `mirrored' VGA ports
136 * and other strange ISA hardware, so we always want the
137 * addresses to be allocated in the 0x000-0x0ff region
140 * Why? Because some silly external IO cards only decode
141 * the low 10 bits of the IO address. The 0x00-0xff region
142 * is reserved for motherboard devices that decode all 16
143 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
144 * but we want to try to avoid allocating at 0x2900-0x2bff
145 * which might have be mirrored at 0x0100-0x03ff..
147 void pcibios_align_resource(void *data, struct resource *res,
148 unsigned long size, unsigned long align)
150 struct pci_dev *dev = data;
151 struct pci_controller *hose = pci_bus_to_host(dev->bus);
152 unsigned long start = res->start;
153 unsigned long alignto;
155 if (res->flags & IORESOURCE_IO) {
156 unsigned long offset = (unsigned long)hose->io_base_virt -
158 /* Make sure we start at our min on all hoses */
159 if (start - offset < PCIBIOS_MIN_IO)
160 start = PCIBIOS_MIN_IO + offset;
163 * Put everything into 0x00-0xff region modulo 0x400
166 start = (start + 0x3ff) & ~0x3ff;
168 } else if (res->flags & IORESOURCE_MEM) {
169 /* Make sure we start at our min on all hoses */
170 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
171 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
173 /* Align to multiple of size of minimum base. */
174 alignto = max(0x1000UL, align);
175 start = ALIGN(start, alignto);
181 static DEFINE_SPINLOCK(hose_spinlock);
184 * pci_controller(phb) initialized common variables.
186 void __devinit pci_setup_pci_controller(struct pci_controller *hose)
188 memset(hose, 0, sizeof(struct pci_controller));
190 spin_lock(&hose_spinlock);
191 hose->global_number = global_phb_number++;
192 list_add_tail(&hose->list_node, &hose_list);
193 spin_unlock(&hose_spinlock);
196 static void __init pcibios_claim_one_bus(struct pci_bus *b)
199 struct pci_bus *child_bus;
201 list_for_each_entry(dev, &b->devices, bus_list) {
204 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
205 struct resource *r = &dev->resource[i];
207 if (r->parent || !r->start || !r->flags)
209 pci_claim_resource(dev, i);
213 list_for_each_entry(child_bus, &b->children, node)
214 pcibios_claim_one_bus(child_bus);
217 #ifndef CONFIG_PPC_ISERIES
218 static void __init pcibios_claim_of_setup(void)
222 list_for_each_entry(b, &pci_root_buses, node)
223 pcibios_claim_one_bus(b);
227 static int __init pcibios_init(void)
229 struct pci_controller *hose, *tmp;
232 /* For now, override phys_mem_access_prot. If we need it,
233 * later, we may move that initialization to each ppc_md
235 ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
237 #ifdef CONFIG_PPC_ISERIES
238 iSeries_pcibios_init();
241 printk("PCI: Probing PCI hardware\n");
243 /* Scan all of the recorded PCI controllers. */
244 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
245 hose->last_busno = 0xff;
246 bus = pci_scan_bus(hose->first_busno, hose->ops,
249 hose->last_busno = bus->subordinate;
252 #ifndef CONFIG_PPC_ISERIES
254 pcibios_claim_of_setup();
256 /* FIXME: `else' will be removed when
257 pci_assign_unassigned_resources() is able to work
258 correctly with [partially] allocated PCI tree. */
259 pci_assign_unassigned_resources();
260 #endif /* !CONFIG_PPC_ISERIES */
262 /* Call machine dependent final fixup */
263 if (ppc_md.pcibios_fixup)
264 ppc_md.pcibios_fixup();
266 /* Cache the location of the ISA bridge (if we have one) */
267 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
268 if (ppc64_isabridge_dev != NULL)
269 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
271 printk("PCI: Probing PCI hardware done\n");
276 subsys_initcall(pcibios_init);
278 char __init *pcibios_setup(char *str)
283 int pcibios_enable_device(struct pci_dev *dev, int mask)
288 pci_read_config_word(dev, PCI_COMMAND, &cmd);
291 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
292 struct resource *res = &dev->resource[i];
294 /* Only set up the requested stuff */
295 if (!(mask & (1<<i)))
298 if (res->flags & IORESOURCE_IO)
299 cmd |= PCI_COMMAND_IO;
300 if (res->flags & IORESOURCE_MEM)
301 cmd |= PCI_COMMAND_MEMORY;
305 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
307 /* Enable the appropriate bits in the PCI command register. */
308 pci_write_config_word(dev, PCI_COMMAND, cmd);
314 * Return the domain number for this bus.
316 int pci_domain_nr(struct pci_bus *bus)
318 #ifdef CONFIG_PPC_ISERIES
321 struct pci_controller *hose = pci_bus_to_host(bus);
323 return hose->global_number;
327 EXPORT_SYMBOL(pci_domain_nr);
329 /* Decide whether to display the domain number in /proc */
330 int pci_proc_domain(struct pci_bus *bus)
332 #ifdef CONFIG_PPC_ISERIES
335 struct pci_controller *hose = pci_bus_to_host(bus);
341 * Platform support for /proc/bus/pci/X/Y mmap()s,
342 * modelled on the sparc64 implementation by Dave Miller.
347 * Adjust vm_pgoff of VMA such that it is the physical page offset
348 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
350 * Basically, the user finds the base address for his device which he wishes
351 * to mmap. They read the 32-bit value from the config space base register,
352 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
353 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
355 * Returns negative error code on failure, zero on success.
357 static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
358 unsigned long *offset,
359 enum pci_mmap_state mmap_state)
361 struct pci_controller *hose = pci_bus_to_host(dev->bus);
362 unsigned long io_offset = 0;
366 return NULL; /* should never happen */
368 /* If memory, add on the PCI bridge address offset */
369 if (mmap_state == pci_mmap_mem) {
370 *offset += hose->pci_mem_offset;
371 res_bit = IORESOURCE_MEM;
373 io_offset = (unsigned long)hose->io_base_virt - pci_io_base;
374 *offset += io_offset;
375 res_bit = IORESOURCE_IO;
379 * Check that the offset requested corresponds to one of the
380 * resources of the device.
382 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
383 struct resource *rp = &dev->resource[i];
384 int flags = rp->flags;
386 /* treat ROM as memory (should be already) */
387 if (i == PCI_ROM_RESOURCE)
388 flags |= IORESOURCE_MEM;
390 /* Active and same type? */
391 if ((flags & res_bit) == 0)
394 /* In the range of this resource? */
395 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
398 /* found it! construct the final physical address */
399 if (mmap_state == pci_mmap_io)
400 *offset += hose->io_base_phys - io_offset;
408 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
411 static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
413 enum pci_mmap_state mmap_state,
416 unsigned long prot = pgprot_val(protection);
418 /* Write combine is always 0 on non-memory space mappings. On
419 * memory space, if the user didn't pass 1, we check for a
420 * "prefetchable" resource. This is a bit hackish, but we use
421 * this to workaround the inability of /sysfs to provide a write
424 if (mmap_state != pci_mmap_mem)
426 else if (write_combine == 0) {
427 if (rp->flags & IORESOURCE_PREFETCH)
431 /* XXX would be nice to have a way to ask for write-through */
432 prot |= _PAGE_NO_CACHE;
434 prot &= ~_PAGE_GUARDED;
436 prot |= _PAGE_GUARDED;
438 printk("PCI map for %s:%lx, prot: %lx\n", pci_name(dev), rp->start,
441 return __pgprot(prot);
445 * This one is used by /dev/mem and fbdev who have no clue about the
446 * PCI device, it tries to find the PCI device first and calls the
449 pgprot_t pci_phys_mem_access_prot(struct file *file,
450 unsigned long offset,
454 struct pci_dev *pdev = NULL;
455 struct resource *found = NULL;
456 unsigned long prot = pgprot_val(protection);
459 if (page_is_ram(offset >> PAGE_SHIFT))
460 return __pgprot(prot);
462 prot |= _PAGE_NO_CACHE | _PAGE_GUARDED;
464 for_each_pci_dev(pdev) {
465 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
466 struct resource *rp = &pdev->resource[i];
467 int flags = rp->flags;
469 /* Active and same type? */
470 if ((flags & IORESOURCE_MEM) == 0)
472 /* In the range of this resource? */
473 if (offset < (rp->start & PAGE_MASK) ||
483 if (found->flags & IORESOURCE_PREFETCH)
484 prot &= ~_PAGE_GUARDED;
488 DBG("non-PCI map for %lx, prot: %lx\n", offset, prot);
490 return __pgprot(prot);
495 * Perform the actual remap of the pages for a PCI device mapping, as
496 * appropriate for this architecture. The region in the process to map
497 * is described by vm_start and vm_end members of VMA, the base physical
498 * address is found in vm_pgoff.
499 * The pci device structure is provided so that architectures may make mapping
500 * decisions on a per-device or per-bus basis.
502 * Returns a negative error code on failure, zero on success.
504 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
505 enum pci_mmap_state mmap_state,
508 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
512 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
516 vma->vm_pgoff = offset >> PAGE_SHIFT;
517 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
518 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
520 mmap_state, write_combine);
522 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
523 vma->vm_end - vma->vm_start, vma->vm_page_prot);
528 #ifdef CONFIG_PPC_MULTIPLATFORM
529 static ssize_t pci_show_devspec(struct device *dev, struct device_attribute *attr, char *buf)
531 struct pci_dev *pdev;
532 struct device_node *np;
534 pdev = to_pci_dev (dev);
535 np = pci_device_to_OF_node(pdev);
536 if (np == NULL || np->full_name == NULL)
538 return sprintf(buf, "%s", np->full_name);
540 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
541 #endif /* CONFIG_PPC_MULTIPLATFORM */
543 void pcibios_add_platform_entries(struct pci_dev *pdev)
545 #ifdef CONFIG_PPC_MULTIPLATFORM
546 device_create_file(&pdev->dev, &dev_attr_devspec);
547 #endif /* CONFIG_PPC_MULTIPLATFORM */
550 #ifdef CONFIG_PPC_MULTIPLATFORM
552 #define ISA_SPACE_MASK 0x1
553 #define ISA_SPACE_IO 0x1
555 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
556 unsigned long phb_io_base_phys,
557 void __iomem * phb_io_base_virt)
559 struct isa_range *range;
560 unsigned long pci_addr;
561 unsigned int isa_addr;
565 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
566 if (range == NULL || (rlen < sizeof(struct isa_range))) {
567 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
569 __ioremap_explicit(phb_io_base_phys,
570 (unsigned long)phb_io_base_virt,
571 0x10000, _PAGE_NO_CACHE | _PAGE_GUARDED);
575 /* From "ISA Binding to 1275"
576 * The ranges property is laid out as an array of elements,
577 * each of which comprises:
578 * cells 0 - 1: an ISA address
579 * cells 2 - 4: a PCI address
580 * (size depending on dev->n_addr_cells)
581 * cell 5: the size of the range
583 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
584 isa_addr = range->isa_addr.a_lo;
585 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
586 range->pci_addr.a_lo;
588 /* Assume these are both zero */
589 if ((pci_addr != 0) || (isa_addr != 0)) {
590 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
595 size = PAGE_ALIGN(range->size);
597 __ioremap_explicit(phb_io_base_phys,
598 (unsigned long) phb_io_base_virt,
599 size, _PAGE_NO_CACHE | _PAGE_GUARDED);
603 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
604 struct device_node *dev)
606 unsigned int *ranges;
610 struct resource *res;
611 int np, na = prom_n_addr_cells(dev);
612 unsigned long pci_addr, cpu_phys_addr;
616 /* From "PCI Binding to 1275"
617 * The ranges property is laid out as an array of elements,
618 * each of which comprises:
619 * cells 0 - 2: a PCI address
620 * cells 3 or 3+4: a CPU physical address
621 * (size depending on dev->n_addr_cells)
622 * cells 4+5 or 5+6: the size of the range
625 hose->io_base_phys = 0;
626 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
627 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
629 pci_addr = (unsigned long)ranges[1] << 32 | ranges[2];
631 cpu_phys_addr = ranges[3];
633 cpu_phys_addr = cpu_phys_addr << 32 | ranges[4];
635 size = (unsigned long)ranges[na+3] << 32 | ranges[na+4];
638 switch ((ranges[0] >> 24) & 0x3) {
639 case 1: /* I/O space */
640 hose->io_base_phys = cpu_phys_addr;
641 hose->pci_io_size = size;
643 res = &hose->io_resource;
644 res->flags = IORESOURCE_IO;
645 res->start = pci_addr;
646 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
647 res->start, res->start + size - 1);
649 case 2: /* memory space */
651 while (memno < 3 && hose->mem_resources[memno].flags)
655 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
657 res = &hose->mem_resources[memno];
658 res->flags = IORESOURCE_MEM;
659 res->start = cpu_phys_addr;
660 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
661 res->start, res->start + size - 1);
666 res->name = dev->full_name;
667 res->end = res->start + size - 1;
676 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
678 unsigned long size = hose->pci_io_size;
679 unsigned long io_virt_offset;
680 struct resource *res;
681 struct device_node *isa_dn;
683 hose->io_base_virt = reserve_phb_iospace(size);
684 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
685 hose->global_number, hose->io_base_phys,
686 (unsigned long) hose->io_base_virt);
689 pci_io_base = (unsigned long)hose->io_base_virt;
690 isa_dn = of_find_node_by_type(NULL, "isa");
692 isa_io_base = pci_io_base;
693 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
701 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
702 res = &hose->io_resource;
703 res->start += io_virt_offset;
704 res->end += io_virt_offset;
707 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose,
710 unsigned long size = hose->pci_io_size;
711 unsigned long io_virt_offset;
712 struct resource *res;
714 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
715 _PAGE_NO_CACHE | _PAGE_GUARDED);
716 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
717 hose->global_number, hose->io_base_phys,
718 (unsigned long) hose->io_base_virt);
721 pci_io_base = (unsigned long)hose->io_base_virt;
723 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
724 res = &hose->io_resource;
725 res->start += io_virt_offset;
726 res->end += io_virt_offset;
730 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
731 unsigned long *start_virt, unsigned long *size)
733 struct pci_controller *hose = pci_bus_to_host(bus);
734 struct pci_bus_region region;
735 struct resource *res;
738 res = bus->resource[0];
739 pcibios_resource_to_bus(bus->self, ®ion, res);
740 *start_phys = hose->io_base_phys + region.start;
741 *start_virt = (unsigned long) hose->io_base_virt +
743 if (region.end > region.start)
744 *size = region.end - region.start + 1;
746 printk("%s(): unexpected region 0x%lx->0x%lx\n",
747 __FUNCTION__, region.start, region.end);
753 res = &hose->io_resource;
754 *start_phys = hose->io_base_phys;
755 *start_virt = (unsigned long) hose->io_base_virt;
756 if (res->end > res->start)
757 *size = res->end - res->start + 1;
759 printk("%s(): unexpected region 0x%lx->0x%lx\n",
760 __FUNCTION__, res->start, res->end);
768 int unmap_bus_range(struct pci_bus *bus)
770 unsigned long start_phys;
771 unsigned long start_virt;
775 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
779 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
781 if (iounmap_explicit((void __iomem *) start_virt, size))
786 EXPORT_SYMBOL(unmap_bus_range);
788 int remap_bus_range(struct pci_bus *bus)
790 unsigned long start_phys;
791 unsigned long start_virt;
795 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
800 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
802 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
803 if (__ioremap_explicit(start_phys, start_virt, size,
804 _PAGE_NO_CACHE | _PAGE_GUARDED))
809 EXPORT_SYMBOL(remap_bus_range);
811 void phbs_remap_io(void)
813 struct pci_controller *hose, *tmp;
815 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
816 remap_bus_range(hose->bus);
820 * ppc64 can have multifunction devices that do not respond to function 0.
821 * In this case we must scan all functions.
823 int pcibios_scan_all_fns(struct pci_bus *bus, int devfn)
825 struct device_node *busdn, *dn;
828 busdn = pci_device_to_OF_node(bus->self);
830 busdn = bus->sysdata; /* must be a phb */
836 * Check to see if there is any of the 8 functions are in the
837 * device tree. If they are then we need to scan all the
838 * functions of this slot.
840 for (dn = busdn->child; dn; dn = dn->sibling)
841 if ((dn->devfn >> 3) == (devfn >> 3))
848 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
851 /* Update device resources. */
852 struct pci_controller *hose = pci_bus_to_host(bus);
855 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
856 if (dev->resource[i].flags & IORESOURCE_IO) {
857 unsigned long offset = (unsigned long)hose->io_base_virt
859 unsigned long start, end, mask;
861 start = dev->resource[i].start += offset;
862 end = dev->resource[i].end += offset;
864 /* Need to allow IO access to pages that are in the
866 if (start < MAX_ISA_PORT) {
867 if (end > MAX_ISA_PORT)
870 start >>= PAGE_SHIFT;
873 /* get the range of pages for the map */
874 mask = ((1 << (end+1))-1) ^ ((1 << start)-1);
875 io_page_mask |= mask;
878 else if (dev->resource[i].flags & IORESOURCE_MEM) {
879 dev->resource[i].start += hose->pci_mem_offset;
880 dev->resource[i].end += hose->pci_mem_offset;
884 EXPORT_SYMBOL(pcibios_fixup_device_resources);
886 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
888 struct pci_controller *hose = pci_bus_to_host(bus);
889 struct pci_dev *dev = bus->self;
890 struct resource *res;
897 bus->resource[0] = res = &hose->io_resource;
899 if (res->flags && request_resource(&ioport_resource, res))
900 printk(KERN_ERR "Failed to request IO on "
901 "PCI domain %d\n", pci_domain_nr(bus));
903 for (i = 0; i < 3; ++i) {
904 res = &hose->mem_resources[i];
905 bus->resource[i+1] = res;
906 if (res->flags && request_resource(&iomem_resource, res))
907 printk(KERN_ERR "Failed to request MEM on "
911 } else if (pci_probe_only &&
912 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
913 /* This is a subordinate bridge */
915 pci_read_bridge_bases(bus);
916 pcibios_fixup_device_resources(dev, bus);
919 ppc_md.iommu_bus_setup(bus);
921 list_for_each_entry(dev, &bus->devices, bus_list)
922 ppc_md.iommu_dev_setup(dev);
924 if (ppc_md.irq_bus_setup)
925 ppc_md.irq_bus_setup(bus);
930 list_for_each_entry(dev, &bus->devices, bus_list) {
931 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
932 pcibios_fixup_device_resources(dev, bus);
935 EXPORT_SYMBOL(pcibios_fixup_bus);
938 * Reads the interrupt pin to determine if interrupt is use by card.
939 * If the interrupt is used, then gets the interrupt line from the
940 * openfirmware and sets it in the pci_dev and pci_config line.
942 int pci_read_irq_line(struct pci_dev *pci_dev)
945 struct device_node *node;
947 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
951 node = pci_device_to_OF_node(pci_dev);
955 if (node->n_intrs == 0)
958 pci_dev->irq = node->intrs[0].line;
960 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
964 EXPORT_SYMBOL(pci_read_irq_line);
966 void pci_resource_to_user(const struct pci_dev *dev, int bar,
967 const struct resource *rsrc,
968 u64 *start, u64 *end)
970 struct pci_controller *hose = pci_bus_to_host(dev->bus);
971 unsigned long offset = 0;
976 if (rsrc->flags & IORESOURCE_IO)
977 offset = pci_io_base - (unsigned long)hose->io_base_virt +
980 *start = rsrc->start + offset;
981 *end = rsrc->end + offset;
984 #endif /* CONFIG_PPC_MULTIPLATFORM */