3 * (Compatible with Algo System ., LTD. - AP-320A)
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 * Author : Yusuke Goda <goda.yuske@renesas.com>
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
14 #include <linux/device.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/mtd/physmap.h>
18 #include <linux/mtd/sh_flctl.h>
19 #include <linux/delay.h>
20 #include <linux/i2c.h>
21 #include <linux/smsc911x.h>
22 #include <linux/gpio.h>
23 #include <media/soc_camera_platform.h>
24 #include <media/sh_mobile_ceu.h>
25 #include <video/sh_mobile_lcdc.h>
27 #include <asm/clock.h>
28 #include <cpu/sh7723.h>
30 static struct smsc911x_platform_config smsc911x_config = {
31 .phy_interface = PHY_INTERFACE_MODE_MII,
32 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
33 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
34 .flags = SMSC911X_USE_32BIT,
37 static struct resource smsc9118_resources[] = {
41 .flags = IORESOURCE_MEM,
46 .flags = IORESOURCE_IRQ,
50 static struct platform_device smsc9118_device = {
53 .num_resources = ARRAY_SIZE(smsc9118_resources),
54 .resource = smsc9118_resources,
56 .platform_data = &smsc911x_config,
61 * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
62 * If this area erased, this board can not boot.
64 static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
68 .size = (1 * 1024 * 1024),
69 .mask_flags = MTD_WRITEABLE, /* Read-only */
72 .offset = MTDPART_OFS_APPEND,
73 .size = (2 * 1024 * 1024),
76 .offset = MTDPART_OFS_APPEND,
77 .size = ((7 * 1024 * 1024) + (512 * 1024)),
80 .offset = MTDPART_OFS_APPEND,
81 .mask_flags = MTD_WRITEABLE, /* Read-only */
82 .size = (1024 * 128 * 2),
85 .offset = MTDPART_OFS_APPEND,
86 .size = MTDPART_SIZ_FULL,
90 static struct physmap_flash_data ap325rxa_nor_flash_data = {
92 .parts = ap325rxa_nor_flash_partitions,
93 .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
96 static struct resource ap325rxa_nor_flash_resources[] = {
101 .flags = IORESOURCE_MEM,
105 static struct platform_device ap325rxa_nor_flash_device = {
106 .name = "physmap-flash",
107 .resource = ap325rxa_nor_flash_resources,
108 .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
110 .platform_data = &ap325rxa_nor_flash_data,
114 static struct mtd_partition nand_partition_info[] = {
118 .size = MTDPART_SIZ_FULL,
122 static struct resource nand_flash_resources[] = {
126 .flags = IORESOURCE_MEM,
130 static struct sh_flctl_platform_data nand_flash_data = {
131 .parts = nand_partition_info,
132 .nr_parts = ARRAY_SIZE(nand_partition_info),
133 .flcmncr_val = FCKSEL_E | TYPESEL_SET | NANWF_E,
137 static struct platform_device nand_flash_device = {
139 .resource = nand_flash_resources,
140 .num_resources = ARRAY_SIZE(nand_flash_resources),
142 .platform_data = &nand_flash_data,
146 #define FPGA_LCDREG 0xB4100180
147 #define FPGA_BKLREG 0xB4100212
148 #define FPGA_LCDREG_VAL 0x0018
149 #define PORT_MSELCRB 0xA4050182
150 #define PORT_HIZCRC 0xA405015C
151 #define PORT_DRVCRA 0xA405018A
152 #define PORT_DRVCRB 0xA405018C
154 static void ap320_wvga_power_on(void *board_data)
158 /* ASD AP-320/325 LCD ON */
159 ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
162 gpio_set_value(GPIO_PTS3, 0);
163 ctrl_outw(0x100, FPGA_BKLREG);
166 static struct sh_mobile_lcdc_info lcdc_info = {
167 .clock_source = LCDC_CLK_EXTERNAL,
169 .chan = LCDC_CHAN_MAINLCD,
171 .interface_type = RGB18,
183 .sync = 0, /* hsync and vsync are active low */
185 .lcd_size_cfg = { /* 7.0 inch */
190 .display_on = ap320_wvga_power_on,
195 static struct resource lcdc_resources[] = {
198 .start = 0xfe940000, /* P4-only space */
200 .flags = IORESOURCE_MEM,
204 .flags = IORESOURCE_IRQ,
208 static struct platform_device lcdc_device = {
209 .name = "sh_mobile_lcdc_fb",
210 .num_resources = ARRAY_SIZE(lcdc_resources),
211 .resource = lcdc_resources,
213 .platform_data = &lcdc_info,
218 static unsigned char camera_ncm03j_magic[] =
220 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
221 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
222 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
223 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
224 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
225 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
226 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
227 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
228 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
229 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
230 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
231 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
232 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
233 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
234 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
235 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
238 static int camera_set_capture(struct soc_camera_platform_info *info,
241 struct i2c_adapter *a = i2c_get_adapter(0);
247 return 0; /* no disable for now */
249 for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
257 buf[0] = camera_ncm03j_magic[i];
258 buf[1] = camera_ncm03j_magic[i + 1];
260 ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
266 static struct soc_camera_platform_info camera_info = {
268 .format_name = "UYVY",
271 .pixelformat = V4L2_PIX_FMT_UYVY,
272 .colorspace = V4L2_COLORSPACE_SMPTE170M,
276 .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
277 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
278 .set_capture = camera_set_capture,
281 static struct platform_device camera_device = {
282 .name = "soc_camera_platform",
284 .platform_data = &camera_info,
287 #endif /* CONFIG_I2C */
289 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
290 .flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
291 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
294 static struct resource ceu_resources[] = {
299 .flags = IORESOURCE_MEM,
303 .flags = IORESOURCE_IRQ,
306 /* place holder for contiguous memory */
310 static struct platform_device ceu_device = {
311 .name = "sh_mobile_ceu",
312 .id = 0, /* "ceu0" clock */
313 .num_resources = ARRAY_SIZE(ceu_resources),
314 .resource = ceu_resources,
316 .platform_data = &sh_mobile_ceu_info,
320 static struct platform_device *ap325rxa_devices[] __initdata = {
322 &ap325rxa_nor_flash_device,
331 static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
333 I2C_BOARD_INFO("pcf8563", 0x51),
337 static int __init ap325rxa_devices_setup(void)
339 /* LD3 and LD4 LEDs */
340 gpio_request(GPIO_PTX5, NULL); /* RUN */
341 gpio_direction_output(GPIO_PTX5, 1);
342 gpio_export(GPIO_PTX5, 0);
344 gpio_request(GPIO_PTX4, NULL); /* INDICATOR */
345 gpio_direction_output(GPIO_PTX4, 0);
346 gpio_export(GPIO_PTX4, 0);
349 gpio_request(GPIO_PTF7, NULL); /* MODE */
350 gpio_direction_input(GPIO_PTF7);
351 gpio_export(GPIO_PTF7, 0);
354 gpio_request(GPIO_FN_LCDD15, NULL);
355 gpio_request(GPIO_FN_LCDD14, NULL);
356 gpio_request(GPIO_FN_LCDD13, NULL);
357 gpio_request(GPIO_FN_LCDD12, NULL);
358 gpio_request(GPIO_FN_LCDD11, NULL);
359 gpio_request(GPIO_FN_LCDD10, NULL);
360 gpio_request(GPIO_FN_LCDD9, NULL);
361 gpio_request(GPIO_FN_LCDD8, NULL);
362 gpio_request(GPIO_FN_LCDD7, NULL);
363 gpio_request(GPIO_FN_LCDD6, NULL);
364 gpio_request(GPIO_FN_LCDD5, NULL);
365 gpio_request(GPIO_FN_LCDD4, NULL);
366 gpio_request(GPIO_FN_LCDD3, NULL);
367 gpio_request(GPIO_FN_LCDD2, NULL);
368 gpio_request(GPIO_FN_LCDD1, NULL);
369 gpio_request(GPIO_FN_LCDD0, NULL);
370 gpio_request(GPIO_FN_LCDLCLK_PTR, NULL);
371 gpio_request(GPIO_FN_LCDDCK, NULL);
372 gpio_request(GPIO_FN_LCDVEPWC, NULL);
373 gpio_request(GPIO_FN_LCDVCPWC, NULL);
374 gpio_request(GPIO_FN_LCDVSYN, NULL);
375 gpio_request(GPIO_FN_LCDHSYN, NULL);
376 gpio_request(GPIO_FN_LCDDISP, NULL);
377 gpio_request(GPIO_FN_LCDDON, NULL);
380 gpio_request(GPIO_PTS3, NULL);
381 gpio_direction_output(GPIO_PTS3, 1);
384 gpio_request(GPIO_FN_VIO_CLK2, NULL);
385 gpio_request(GPIO_FN_VIO_VD2, NULL);
386 gpio_request(GPIO_FN_VIO_HD2, NULL);
387 gpio_request(GPIO_FN_VIO_FLD, NULL);
388 gpio_request(GPIO_FN_VIO_CKO, NULL);
389 gpio_request(GPIO_FN_VIO_D15, NULL);
390 gpio_request(GPIO_FN_VIO_D14, NULL);
391 gpio_request(GPIO_FN_VIO_D13, NULL);
392 gpio_request(GPIO_FN_VIO_D12, NULL);
393 gpio_request(GPIO_FN_VIO_D11, NULL);
394 gpio_request(GPIO_FN_VIO_D10, NULL);
395 gpio_request(GPIO_FN_VIO_D9, NULL);
396 gpio_request(GPIO_FN_VIO_D8, NULL);
398 gpio_request(GPIO_PTZ7, NULL);
399 gpio_direction_output(GPIO_PTZ7, 0); /* OE_CAM */
400 gpio_request(GPIO_PTZ6, NULL);
401 gpio_direction_output(GPIO_PTZ6, 0); /* STBY_CAM */
402 gpio_request(GPIO_PTZ5, NULL);
403 gpio_direction_output(GPIO_PTZ5, 1); /* RST_CAM */
404 gpio_request(GPIO_PTZ4, NULL);
405 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
407 ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
410 gpio_request(GPIO_FN_FCE, NULL);
411 gpio_request(GPIO_FN_NAF7, NULL);
412 gpio_request(GPIO_FN_NAF6, NULL);
413 gpio_request(GPIO_FN_NAF5, NULL);
414 gpio_request(GPIO_FN_NAF4, NULL);
415 gpio_request(GPIO_FN_NAF3, NULL);
416 gpio_request(GPIO_FN_NAF2, NULL);
417 gpio_request(GPIO_FN_NAF1, NULL);
418 gpio_request(GPIO_FN_NAF0, NULL);
419 gpio_request(GPIO_FN_FCDE, NULL);
420 gpio_request(GPIO_FN_FOE, NULL);
421 gpio_request(GPIO_FN_FSC, NULL);
422 gpio_request(GPIO_FN_FWE, NULL);
423 gpio_request(GPIO_FN_FRB, NULL);
425 ctrl_outw(0, PORT_HIZCRC);
426 ctrl_outw(0xFFFF, PORT_DRVCRA);
427 ctrl_outw(0xFFFF, PORT_DRVCRB);
429 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
431 i2c_register_board_info(0, ap325rxa_i2c_devices,
432 ARRAY_SIZE(ap325rxa_i2c_devices));
434 return platform_add_devices(ap325rxa_devices,
435 ARRAY_SIZE(ap325rxa_devices));
437 device_initcall(ap325rxa_devices_setup);
439 static struct sh_machine_vector mv_ap325rxa __initmv = {
440 .mv_name = "AP-325RXA",