arch/sh/kernel/traps.c

   1 /*
   2  * 'traps.c' handles hardware traps and faults after we have saved some
   3  * state in 'entry.S'.
   4  *
   5  *  SuperH version: Copyright (C) 1999 Niibe Yutaka
   6  *                  Copyright (C) 2000 Philipp Rumpf
   7  *                  Copyright (C) 2000 David Howells
   8  *                  Copyright (C) 2002 - 2006 Paul Mundt
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/ptrace.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/module.h>
  19 #include <linux/kallsyms.h>
  20 #include <linux/io.h>
  21 #include <linux/debug_locks.h>
  22 #include <linux/limits.h>
  23 #include <asm/system.h>
  24 #include <asm/uaccess.h>
  25
  26 #ifdef CONFIG_SH_KGDB
  27 #include <asm/kgdb.h>
  28 #define CHK_REMOTE_DEBUG(regs)                  \
  29 {                                               \
  30         if (kgdb_debug_hook && !user_mode(regs))\
  31                 (*kgdb_debug_hook)(regs);       \
  32 }
  33 #else
  34 #define CHK_REMOTE_DEBUG(regs)
  35 #endif
  36
  37 #ifdef CONFIG_CPU_SH2
  38 # define TRAP_RESERVED_INST     4
  39 # define TRAP_ILLEGAL_SLOT_INST 6
  40 # define TRAP_ADDRESS_ERROR     9
  41 # ifdef CONFIG_CPU_SH2A
  42 #  define TRAP_DIVZERO_ERROR    17
  43 #  define TRAP_DIVOVF_ERROR     18
  44 # endif
  45 #else
  46 #define TRAP_RESERVED_INST      12
  47 #define TRAP_ILLEGAL_SLOT_INST  13
  48 #endif
  49
  50 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
  51 {
  52         unsigned long p;
  53         int i;
  54
  55         printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
  56
  57         for (p = bottom & ~31; p < top; ) {
  58                 printk("%04lx: ", p & 0xffff);
  59
  60                 for (i = 0; i < 8; i++, p += 4) {
  61                         unsigned int val;
  62
  63                         if (p < bottom || p >= top)
  64                                 printk("         ");
  65                         else {
  66                                 if (__get_user(val, (unsigned int __user *)p)) {
  67                                         printk("\n");
  68                                         return;
  69                                 }
  70                                 printk("%08x ", val);
  71                         }
  72                 }
  73                 printk("\n");
  74         }
  75 }
  76
  77 DEFINE_SPINLOCK(die_lock);
  78
  79 void die(const char * str, struct pt_regs * regs, long err)
  80 {
  81         static int die_counter;
  82
  83         console_verbose();
  84         spin_lock_irq(&die_lock);
  85         bust_spinlocks(1);
  86
  87         printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
  88
  89         CHK_REMOTE_DEBUG(regs);
  90         print_modules();
  91         show_regs(regs);
  92
  93         printk("Process: %s (pid: %d, stack limit = %p)\n",
  94                current->comm, current->pid, task_stack_page(current) + 1);
  95
  96         if (!user_mode(regs) || in_interrupt())
  97                 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
  98                          (unsigned long)task_stack_page(current));
  99
 100         bust_spinlocks(0);
 101         spin_unlock_irq(&die_lock);
 102         do_exit(SIGSEGV);
 103 }
 104
 105 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
 106                                  long err)
 107 {
 108         if (!user_mode(regs))
 109                 die(str, regs, err);
 110 }
 111
 112 /*
 113  * try and fix up kernelspace address errors
 114  * - userspace errors just cause EFAULT to be returned, resulting in SEGV
 115  * - kernel/userspace interfaces cause a jump to an appropriate handler
 116  * - other kernel errors are bad
 117  * - return 0 if fixed-up, -EFAULT if non-fatal (to the kernel) fault
 118  */
 119 static int die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
 120 {
 121         if (!user_mode(regs)) {
 122                 const struct exception_table_entry *fixup;
 123                 fixup = search_exception_tables(regs->pc);
 124                 if (fixup) {
 125                         regs->pc = fixup->fixup;
 126                         return 0;
 127                 }
 128                 die(str, regs, err);
 129         }
 130         return -EFAULT;
 131 }
 132
 133 #ifdef CONFIG_BUG
 134 #ifdef CONFIG_DEBUG_BUGVERBOSE
 135 static inline void do_bug_verbose(struct pt_regs *regs)
 136 {
 137         struct bug_frame f;
 138         long len;
 139
 140         if (__copy_from_user(&f, (const void __user *)regs->pc,
 141                              sizeof(struct bug_frame)))
 142                 return;
 143
 144         len = __strnlen_user(f.file, PATH_MAX) - 1;
 145         if (unlikely(len < 0 || len >= PATH_MAX))
 146                 f.file = "<bad filename>";
 147         len = __strnlen_user(f.func, PATH_MAX) - 1;
 148         if (unlikely(len < 0 || len >= PATH_MAX))
 149                 f.func = "<bad function>";
 150
 151         printk(KERN_ALERT "kernel BUG in %s() at %s:%d!\n",
 152                f.func, f.file, f.line);
 153 }
 154 #else
 155 static inline void do_bug_verbose(struct pt_regs *regs)
 156 {
 157 }
 158 #endif /* CONFIG_DEBUG_BUGVERBOSE */
 159 #endif /* CONFIG_BUG */
 160
 161 void handle_BUG(struct pt_regs *regs)
 162 {
 163         do_bug_verbose(regs);
 164         die("Kernel BUG", regs, TRAPA_BUG_OPCODE & 0xff);
 165 }
 166
 167 /*
 168  * handle an instruction that does an unaligned memory access by emulating the
 169  * desired behaviour
 170  * - note that PC _may not_ point to the faulting instruction
 171  *   (if that instruction is in a branch delay slot)
 172  * - return 0 if emulation okay, -EFAULT on existential error
 173  */
 174 static int handle_unaligned_ins(u16 instruction, struct pt_regs *regs)
 175 {
 176         int ret, index, count;
 177         unsigned long *rm, *rn;
 178         unsigned char *src, *dst;
 179
 180         index = (instruction>>8)&15;    /* 0x0F00 */
 181         rn = &regs->regs[index];
 182
 183         index = (instruction>>4)&15;    /* 0x00F0 */
 184         rm = &regs->regs[index];
 185
 186         count = 1<<(instruction&3);
 187
 188         ret = -EFAULT;
 189         switch (instruction>>12) {
 190         case 0: /* mov.[bwl] to/from memory via r0+rn */
 191                 if (instruction & 8) {
 192                         /* from memory */
 193                         src = (unsigned char*) *rm;
 194                         src += regs->regs[0];
 195                         dst = (unsigned char*) rn;
 196                         *(unsigned long*)dst = 0;
 197
 198 #ifdef __LITTLE_ENDIAN__
 199                         if (copy_from_user(dst, src, count))
 200                                 goto fetch_fault;
 201
 202                         if ((count == 2) && dst[1] & 0x80) {
 203                                 dst[2] = 0xff;
 204                                 dst[3] = 0xff;
 205                         }
 206 #else
 207                         dst += 4-count;
 208
 209                         if (__copy_user(dst, src, count))
 210                                 goto fetch_fault;
 211
 212                         if ((count == 2) && dst[2] & 0x80) {
 213                                 dst[0] = 0xff;
 214                                 dst[1] = 0xff;
 215                         }
 216 #endif
 217                 } else {
 218                         /* to memory */
 219                         src = (unsigned char*) rm;
 220 #if !defined(__LITTLE_ENDIAN__)
 221                         src += 4-count;
 222 #endif
 223                         dst = (unsigned char*) *rn;
 224                         dst += regs->regs[0];
 225
 226                         if (copy_to_user(dst, src, count))
 227                                 goto fetch_fault;
 228                 }
 229                 ret = 0;
 230                 break;
 231
 232         case 1: /* mov.l Rm,@(disp,Rn) */
 233                 src = (unsigned char*) rm;
 234                 dst = (unsigned char*) *rn;
 235                 dst += (instruction&0x000F)<<2;
 236
 237                 if (copy_to_user(dst,src,4))
 238                         goto fetch_fault;
 239                 ret = 0;
 240                 break;
 241
 242         case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
 243                 if (instruction & 4)
 244                         *rn -= count;
 245                 src = (unsigned char*) rm;
 246                 dst = (unsigned char*) *rn;
 247 #if !defined(__LITTLE_ENDIAN__)
 248                 src += 4-count;
 249 #endif
 250                 if (copy_to_user(dst, src, count))
 251                         goto fetch_fault;
 252                 ret = 0;
 253                 break;
 254
 255         case 5: /* mov.l @(disp,Rm),Rn */
 256                 src = (unsigned char*) *rm;
 257                 src += (instruction&0x000F)<<2;
 258                 dst = (unsigned char*) rn;
 259                 *(unsigned long*)dst = 0;
 260
 261                 if (copy_from_user(dst,src,4))
 262                         goto fetch_fault;
 263                 ret = 0;
 264                 break;
 265
 266         case 6: /* mov.[bwl] from memory, possibly with post-increment */
 267                 src = (unsigned char*) *rm;
 268                 if (instruction & 4)
 269                         *rm += count;
 270                 dst = (unsigned char*) rn;
 271                 *(unsigned long*)dst = 0;
 272
 273 #ifdef __LITTLE_ENDIAN__
 274                 if (copy_from_user(dst, src, count))
 275                         goto fetch_fault;
 276
 277                 if ((count == 2) && dst[1] & 0x80) {
 278                         dst[2] = 0xff;
 279                         dst[3] = 0xff;
 280                 }
 281 #else
 282                 dst += 4-count;
 283
 284                 if (copy_from_user(dst, src, count))
 285                         goto fetch_fault;
 286
 287                 if ((count == 2) && dst[2] & 0x80) {
 288                         dst[0] = 0xff;
 289                         dst[1] = 0xff;
 290                 }
 291 #endif
 292                 ret = 0;
 293                 break;
 294
 295         case 8:
 296                 switch ((instruction&0xFF00)>>8) {
 297                 case 0x81: /* mov.w R0,@(disp,Rn) */
 298                         src = (unsigned char*) &regs->regs[0];
 299 #if !defined(__LITTLE_ENDIAN__)
 300                         src += 2;
 301 #endif
 302                         dst = (unsigned char*) *rm; /* called Rn in the spec */
 303                         dst += (instruction&0x000F)<<1;
 304
 305                         if (copy_to_user(dst, src, 2))
 306                                 goto fetch_fault;
 307                         ret = 0;
 308                         break;
 309
 310                 case 0x85: /* mov.w @(disp,Rm),R0 */
 311                         src = (unsigned char*) *rm;
 312                         src += (instruction&0x000F)<<1;
 313                         dst = (unsigned char*) &regs->regs[0];
 314                         *(unsigned long*)dst = 0;
 315
 316 #if !defined(__LITTLE_ENDIAN__)
 317                         dst += 2;
 318 #endif
 319
 320                         if (copy_from_user(dst, src, 2))
 321                                 goto fetch_fault;
 322
 323 #ifdef __LITTLE_ENDIAN__
 324                         if (dst[1] & 0x80) {
 325                                 dst[2] = 0xff;
 326                                 dst[3] = 0xff;
 327                         }
 328 #else
 329                         if (dst[2] & 0x80) {
 330                                 dst[0] = 0xff;
 331                                 dst[1] = 0xff;
 332                         }
 333 #endif
 334                         ret = 0;
 335                         break;
 336                 }
 337                 break;
 338         }
 339         return ret;
 340
 341  fetch_fault:
 342         /* Argh. Address not only misaligned but also non-existent.
 343          * Raise an EFAULT and see if it's trapped
 344          */
 345         return die_if_no_fixup("Fault in unaligned fixup", regs, 0);
 346 }
 347
 348 /*
 349  * emulate the instruction in the delay slot
 350  * - fetches the instruction from PC+2
 351  */
 352 static inline int handle_unaligned_delayslot(struct pt_regs *regs)
 353 {
 354         u16 instruction;
 355
 356         if (copy_from_user(&instruction, (u16 *)(regs->pc+2), 2)) {
 357                 /* the instruction-fetch faulted */
 358                 if (user_mode(regs))
 359                         return -EFAULT;
 360
 361                 /* kernel */
 362                 die("delay-slot-insn faulting in handle_unaligned_delayslot",
 363                     regs, 0);
 364         }
 365
 366         return handle_unaligned_ins(instruction,regs);
 367 }
 368
 369 /*
 370  * handle an instruction that does an unaligned memory access
 371  * - have to be careful of branch delay-slot instructions that fault
 372  *  SH3:
 373  *   - if the branch would be taken PC points to the branch
 374  *   - if the branch would not be taken, PC points to delay-slot
 375  *  SH4:
 376  *   - PC always points to delayed branch
 377  * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
 378  */
 379
 380 /* Macros to determine offset from current PC for branch instructions */
 381 /* Explicit type coercion is used to force sign extension where needed */
 382 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
 383 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
 384
 385 /*
 386  * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
 387  * opcodes..
 388  */
 389 #ifndef CONFIG_CPU_SH2A
 390 static int handle_unaligned_notify_count = 10;
 391
 392 static int handle_unaligned_access(u16 instruction, struct pt_regs *regs)
 393 {
 394         u_int rm;
 395         int ret, index;
 396
 397         index = (instruction>>8)&15;    /* 0x0F00 */
 398         rm = regs->regs[index];
 399
 400         /* shout about the first ten userspace fixups */
 401         if (user_mode(regs) && handle_unaligned_notify_count>0) {
 402                 handle_unaligned_notify_count--;
 403
 404                 printk(KERN_NOTICE "Fixing up unaligned userspace access "
 405                        "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
 406                        current->comm,current->pid,(u16*)regs->pc,instruction);
 407         }
 408
 409         ret = -EFAULT;
 410         switch (instruction&0xF000) {
 411         case 0x0000:
 412                 if (instruction==0x000B) {
 413                         /* rts */
 414                         ret = handle_unaligned_delayslot(regs);
 415                         if (ret==0)
 416                                 regs->pc = regs->pr;
 417                 }
 418                 else if ((instruction&0x00FF)==0x0023) {
 419                         /* braf @Rm */
 420                         ret = handle_unaligned_delayslot(regs);
 421                         if (ret==0)
 422                                 regs->pc += rm + 4;
 423                 }
 424                 else if ((instruction&0x00FF)==0x0003) {
 425                         /* bsrf @Rm */
 426                         ret = handle_unaligned_delayslot(regs);
 427                         if (ret==0) {
 428                                 regs->pr = regs->pc + 4;
 429                                 regs->pc += rm + 4;
 430                         }
 431                 }
 432                 else {
 433                         /* mov.[bwl] to/from memory via r0+rn */
 434                         goto simple;
 435                 }
 436                 break;
 437
 438         case 0x1000: /* mov.l Rm,@(disp,Rn) */
 439                 goto simple;
 440
 441         case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
 442                 goto simple;
 443
 444         case 0x4000:
 445                 if ((instruction&0x00FF)==0x002B) {
 446                         /* jmp @Rm */
 447                         ret = handle_unaligned_delayslot(regs);
 448                         if (ret==0)
 449                                 regs->pc = rm;
 450                 }
 451                 else if ((instruction&0x00FF)==0x000B) {
 452                         /* jsr @Rm */
 453                         ret = handle_unaligned_delayslot(regs);
 454                         if (ret==0) {
 455                                 regs->pr = regs->pc + 4;
 456                                 regs->pc = rm;
 457                         }
 458                 }
 459                 else {
 460                         /* mov.[bwl] to/from memory via r0+rn */
 461                         goto simple;
 462                 }
 463                 break;
 464
 465         case 0x5000: /* mov.l @(disp,Rm),Rn */
 466                 goto simple;
 467
 468         case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
 469                 goto simple;
 470
 471         case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
 472                 switch (instruction&0x0F00) {
 473                 case 0x0100: /* mov.w R0,@(disp,Rm) */
 474                         goto simple;
 475                 case 0x0500: /* mov.w @(disp,Rm),R0 */
 476                         goto simple;
 477                 case 0x0B00: /* bf   lab - no delayslot*/
 478                         break;
 479                 case 0x0F00: /* bf/s lab */
 480                         ret = handle_unaligned_delayslot(regs);
 481                         if (ret==0) {
 482 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 483                                 if ((regs->sr & 0x00000001) != 0)
 484                                         regs->pc += 4; /* next after slot */
 485                                 else
 486 #endif
 487                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 488                         }
 489                         break;
 490                 case 0x0900: /* bt   lab - no delayslot */
 491                         break;
 492                 case 0x0D00: /* bt/s lab */
 493                         ret = handle_unaligned_delayslot(regs);
 494                         if (ret==0) {
 495 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
 496                                 if ((regs->sr & 0x00000001) == 0)
 497                                         regs->pc += 4; /* next after slot */
 498                                 else
 499 #endif
 500                                         regs->pc += SH_PC_8BIT_OFFSET(instruction);
 501                         }
 502                         break;
 503                 }
 504                 break;
 505
 506         case 0xA000: /* bra label */
 507                 ret = handle_unaligned_delayslot(regs);
 508                 if (ret==0)
 509                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 510                 break;
 511
 512         case 0xB000: /* bsr label */
 513                 ret = handle_unaligned_delayslot(regs);
 514                 if (ret==0) {
 515                         regs->pr = regs->pc + 4;
 516                         regs->pc += SH_PC_12BIT_OFFSET(instruction);
 517                 }
 518                 break;
 519         }
 520         return ret;
 521
 522         /* handle non-delay-slot instruction */
 523  simple:
 524         ret = handle_unaligned_ins(instruction,regs);
 525         if (ret==0)
 526                 regs->pc += 2;
 527         return ret;
 528 }
 529 #endif /* CONFIG_CPU_SH2A */
 530
 531 #ifdef CONFIG_CPU_HAS_SR_RB
 532 #define lookup_exception_vector(x)      \
 533         __asm__ __volatile__ ("stc r2_bank, %0\n\t" : "=r" ((x)))
 534 #else
 535 #define lookup_exception_vector(x)      \
 536         __asm__ __volatile__ ("mov r4, %0\n\t" : "=r" ((x)))
 537 #endif
 538
 539 /*
 540  * Handle various address error exceptions:
 541  *  - instruction address error:
 542  *       misaligned PC
 543  *       PC >= 0x80000000 in user mode
 544  *  - data address error (read and write)
 545  *       misaligned data access
 546  *       access to >= 0x80000000 is user mode
 547  * Unfortuntaly we can't distinguish between instruction address error
 548  * and data address errors caused by read acceses.
 549  */
 550 asmlinkage void do_address_error(struct pt_regs *regs,
 551                                  unsigned long writeaccess,
 552                                  unsigned long address)
 553 {
 554         unsigned long error_code = 0;
 555         mm_segment_t oldfs;
 556         siginfo_t info;
 557 #ifndef CONFIG_CPU_SH2A
 558         u16 instruction;
 559         int tmp;
 560 #endif
 561
 562         /* Intentional ifdef */
 563 #ifdef CONFIG_CPU_HAS_SR_RB
 564         lookup_exception_vector(error_code);
 565 #endif
 566
 567         oldfs = get_fs();
 568
 569         if (user_mode(regs)) {
 570                 int si_code = BUS_ADRERR;
 571
 572                 local_irq_enable();
 573
 574                 /* bad PC is not something we can fix */
 575                 if (regs->pc & 1) {
 576                         si_code = BUS_ADRALN;
 577                         goto uspace_segv;
 578                 }
 579
 580 #ifndef CONFIG_CPU_SH2A
 581                 set_fs(USER_DS);
 582                 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) {
 583                         /* Argh. Fault on the instruction itself.
 584                            This should never happen non-SMP
 585                         */
 586                         set_fs(oldfs);
 587                         goto uspace_segv;
 588                 }
 589
 590                 tmp = handle_unaligned_access(instruction, regs);
 591                 set_fs(oldfs);
 592
 593                 if (tmp==0)
 594                         return; /* sorted */
 595 #endif
 596
 597 uspace_segv:
 598                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
 599                        "access (PC %lx PR %lx)\n", current->comm, regs->pc,
 600                        regs->pr);
 601
 602                 info.si_signo = SIGBUS;
 603                 info.si_errno = 0;
 604                 info.si_code = si_code;
 605                 info.si_addr = (void *) address;
 606                 force_sig_info(SIGBUS, &info, current);
 607         } else {
 608                 if (regs->pc & 1)
 609                         die("unaligned program counter", regs, error_code);
 610
 611 #ifndef CONFIG_CPU_SH2A
 612                 set_fs(KERNEL_DS);
 613                 if (copy_from_user(&instruction, (u16 *)(regs->pc), 2)) {
 614                         /* Argh. Fault on the instruction itself.
 615                            This should never happen non-SMP
 616                         */
 617                         set_fs(oldfs);
 618                         die("insn faulting in do_address_error", regs, 0);
 619                 }
 620
 621                 handle_unaligned_access(instruction, regs);
 622                 set_fs(oldfs);
 623 #else
 624                 printk(KERN_NOTICE "Killing process \"%s\" due to unaligned "
 625                        "access\n", current->comm);
 626
 627                 force_sig(SIGSEGV, current);
 628 #endif
 629         }
 630 }
 631
 632 #ifdef CONFIG_SH_DSP
 633 /*
 634  *      SH-DSP support gerg@snapgear.com.
 635  */
 636 int is_dsp_inst(struct pt_regs *regs)
 637 {
 638         unsigned short inst;
 639
 640         /*
 641          * Safe guard if DSP mode is already enabled or we're lacking
 642          * the DSP altogether.
 643          */
 644         if (!(cpu_data->flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
 645                 return 0;
 646
 647         get_user(inst, ((unsigned short *) regs->pc));
 648
 649         inst &= 0xf000;
 650
 651         /* Check for any type of DSP or support instruction */
 652         if ((inst == 0xf000) || (inst == 0x4000))
 653                 return 1;
 654
 655         return 0;
 656 }
 657 #else
 658 #define is_dsp_inst(regs)       (0)
 659 #endif /* CONFIG_SH_DSP */
 660
 661 #ifdef CONFIG_CPU_SH2A
 662 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
 663                                 unsigned long r6, unsigned long r7,
 664                                 struct pt_regs __regs)
 665 {
 666         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 667         siginfo_t info;
 668
 669         switch (r4) {
 670         case TRAP_DIVZERO_ERROR:
 671                 info.si_code = FPE_INTDIV;
 672                 break;
 673         case TRAP_DIVOVF_ERROR:
 674                 info.si_code = FPE_INTOVF;
 675                 break;
 676         }
 677
 678         force_sig_info(SIGFPE, &info, current);
 679 }
 680 #endif
 681
 682 /* arch/sh/kernel/cpu/sh4/fpu.c */
 683 extern int do_fpu_inst(unsigned short, struct pt_regs *);
 684 extern asmlinkage void do_fpu_state_restore(unsigned long r4, unsigned long r5,
 685                 unsigned long r6, unsigned long r7, struct pt_regs __regs);
 686
 687 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
 688                                 unsigned long r6, unsigned long r7,
 689                                 struct pt_regs __regs)
 690 {
 691         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 692         unsigned long error_code;
 693         struct task_struct *tsk = current;
 694
 695 #ifdef CONFIG_SH_FPU_EMU
 696         unsigned short inst = 0;
 697         int err;
 698
 699         get_user(inst, (unsigned short*)regs->pc);
 700
 701         err = do_fpu_inst(inst, regs);
 702         if (!err) {
 703                 regs->pc += 2;
 704                 return;
 705         }
 706         /* not a FPU inst. */
 707 #endif
 708
 709 #ifdef CONFIG_SH_DSP
 710         /* Check if it's a DSP instruction */
 711         if (is_dsp_inst(regs)) {
 712                 /* Enable DSP mode, and restart instruction. */
 713                 regs->sr |= SR_DSP;
 714                 return;
 715         }
 716 #endif
 717
 718         lookup_exception_vector(error_code);
 719
 720         local_irq_enable();
 721         CHK_REMOTE_DEBUG(regs);
 722         force_sig(SIGILL, tsk);
 723         die_if_no_fixup("reserved instruction", regs, error_code);
 724 }
 725
 726 #ifdef CONFIG_SH_FPU_EMU
 727 static int emulate_branch(unsigned short inst, struct pt_regs* regs)
 728 {
 729         /*
 730          * bfs: 8fxx: PC+=d*2+4;
 731          * bts: 8dxx: PC+=d*2+4;
 732          * bra: axxx: PC+=D*2+4;
 733          * bsr: bxxx: PC+=D*2+4  after PR=PC+4;
 734          * braf:0x23: PC+=Rn*2+4;
 735          * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
 736          * jmp: 4x2b: PC=Rn;
 737          * jsr: 4x0b: PC=Rn      after PR=PC+4;
 738          * rts: 000b: PC=PR;
 739          */
 740         if ((inst & 0xfd00) == 0x8d00) {
 741                 regs->pc += SH_PC_8BIT_OFFSET(inst);
 742                 return 0;
 743         }
 744
 745         if ((inst & 0xe000) == 0xa000) {
 746                 regs->pc += SH_PC_12BIT_OFFSET(inst);
 747                 return 0;
 748         }
 749
 750         if ((inst & 0xf0df) == 0x0003) {
 751                 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
 752                 return 0;
 753         }
 754
 755         if ((inst & 0xf0df) == 0x400b) {
 756                 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
 757                 return 0;
 758         }
 759
 760         if ((inst & 0xffff) == 0x000b) {
 761                 regs->pc = regs->pr;
 762                 return 0;
 763         }
 764
 765         return 1;
 766 }
 767 #endif
 768
 769 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
 770                                 unsigned long r6, unsigned long r7,
 771                                 struct pt_regs __regs)
 772 {
 773         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 774         unsigned long error_code;
 775         struct task_struct *tsk = current;
 776 #ifdef CONFIG_SH_FPU_EMU
 777         unsigned short inst = 0;
 778
 779         get_user(inst, (unsigned short *)regs->pc + 1);
 780         if (!do_fpu_inst(inst, regs)) {
 781                 get_user(inst, (unsigned short *)regs->pc);
 782                 if (!emulate_branch(inst, regs))
 783                         return;
 784                 /* fault in branch.*/
 785         }
 786         /* not a FPU inst. */
 787 #endif
 788
 789         lookup_exception_vector(error_code);
 790
 791         local_irq_enable();
 792         CHK_REMOTE_DEBUG(regs);
 793         force_sig(SIGILL, tsk);
 794         die_if_no_fixup("illegal slot instruction", regs, error_code);
 795 }
 796
 797 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
 798                                    unsigned long r6, unsigned long r7,
 799                                    struct pt_regs __regs)
 800 {
 801         struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
 802         long ex;
 803
 804         lookup_exception_vector(ex);
 805         die_if_kernel("exception", regs, ex);
 806 }
 807
 808 #if defined(CONFIG_SH_STANDARD_BIOS)
 809 void *gdb_vbr_vector;
 810
 811 static inline void __init gdb_vbr_init(void)
 812 {
 813         register unsigned long vbr;
 814
 815         /*
 816          * Read the old value of the VBR register to initialise
 817          * the vector through which debug and BIOS traps are
 818          * delegated by the Linux trap handler.
 819          */
 820         asm volatile("stc vbr, %0" : "=r" (vbr));
 821
 822         gdb_vbr_vector = (void *)(vbr + 0x100);
 823         printk("Setting GDB trap vector to 0x%08lx\n",
 824                (unsigned long)gdb_vbr_vector);
 825 }
 826 #endif
 827
 828 void __init per_cpu_trap_init(void)
 829 {
 830         extern void *vbr_base;
 831
 832 #ifdef CONFIG_SH_STANDARD_BIOS
 833         gdb_vbr_init();
 834 #endif
 835
 836         /* NOTE: The VBR value should be at P1
 837            (or P2, virtural "fixed" address space).
 838            It's definitely should not in physical address.  */
 839
 840         asm volatile("ldc       %0, vbr"
 841                      : /* no output */
 842                      : "r" (&vbr_base)
 843                      : "memory");
 844 }
 845
 846 void *set_exception_table_vec(unsigned int vec, void *handler)
 847 {
 848         extern void *exception_handling_table[];
 849         void *old_handler;
 850
 851         old_handler = exception_handling_table[vec];
 852         exception_handling_table[vec] = handler;
 853         return old_handler;
 854 }
 855
 856 extern asmlinkage void address_error_handler(unsigned long r4, unsigned long r5,
 857                                              unsigned long r6, unsigned long r7,
 858                                              struct pt_regs __regs);
 859
 860 void __init trap_init(void)
 861 {
 862         set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
 863         set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
 864
 865 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
 866     defined(CONFIG_SH_FPU_EMU)
 867         /*
 868          * For SH-4 lacking an FPU, treat floating point instructions as
 869          * reserved. They'll be handled in the math-emu case, or faulted on
 870          * otherwise.
 871          */
 872         set_exception_table_evt(0x800, do_reserved_inst);
 873         set_exception_table_evt(0x820, do_illegal_slot_inst);
 874 #elif defined(CONFIG_SH_FPU)
 875         set_exception_table_evt(0x800, do_fpu_state_restore);
 876         set_exception_table_evt(0x820, do_fpu_state_restore);
 877 #endif
 878
 879 #ifdef CONFIG_CPU_SH2
 880         set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_handler);
 881 #endif
 882 #ifdef CONFIG_CPU_SH2A
 883         set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
 884         set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
 885 #endif
 886
 887         /* Setup VBR for boot cpu */
 888         per_cpu_trap_init();
 889 }
 890
 891 void show_trace(struct task_struct *tsk, unsigned long *sp,
 892                 struct pt_regs *regs)
 893 {
 894         unsigned long addr;
 895
 896         if (regs && user_mode(regs))
 897                 return;
 898
 899         printk("\nCall trace: ");
 900 #ifdef CONFIG_KALLSYMS
 901         printk("\n");
 902 #endif
 903
 904         while (!kstack_end(sp)) {
 905                 addr = *sp++;
 906                 if (kernel_text_address(addr))
 907                         print_ip_sym(addr);
 908         }
 909
 910         printk("\n");
 911
 912         if (!tsk)
 913                 tsk = current;
 914
 915         debug_show_held_locks(tsk);
 916 }
 917
 918 void show_stack(struct task_struct *tsk, unsigned long *sp)
 919 {
 920         unsigned long stack;
 921
 922         if (!tsk)
 923                 tsk = current;
 924         if (tsk == current)
 925                 sp = (unsigned long *)current_stack_pointer;
 926         else
 927                 sp = (unsigned long *)tsk->thread.sp;
 928
 929         stack = (unsigned long)sp;
 930         dump_mem("Stack: ", stack, THREAD_SIZE +
 931                  (unsigned long)task_stack_page(tsk));
 932         show_trace(tsk, sp, NULL);
 933 }
 934
 935 void dump_stack(void)
 936 {
 937         show_stack(NULL, NULL);
 938 }
 939 EXPORT_SYMBOL(dump_stack);