1 /* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
10 #include <linux/config.h>
11 #include <linux/errno.h>
16 #include <asm/ptrace.h>
18 #include <asm/signal.h>
19 #include <asm/pgtable.h>
20 #include <asm/processor.h>
21 #include <asm/visasm.h>
22 #include <asm/estate.h>
23 #include <asm/auxio.h>
25 /* #define SYSCALL_TRACING 1 */
29 #define NR_SYSCALLS 284 /* Each OS is different... */
34 .globl sparc64_vpte_patchme1
35 .globl sparc64_vpte_patchme2
37 * On a second level vpte miss, check whether the original fault is to the OBP
38 * range (note that this is only possible for instruction miss, data misses to
39 * obp range do not use vpte). If so, go back directly to the faulting address.
40 * This is because we want to read the tpc, otherwise we have no way of knowing
41 * the 8k aligned faulting address if we are using >8k kernel pagesize. This
42 * also ensures no vpte range addresses are dropped into tlb while obp is
43 * executing (see inherit_locked_prom_mappings() rant).
46 /* Load 0xf0000000, which is LOW_OBP_ADDRESS. */
50 /* Is addr >= LOW_OBP_ADDRESS? */
52 blu,pn %xcc, sparc64_vpte_patchme1
55 /* Load 0x100000000, which is HI_OBP_ADDRESS. */
58 /* Is addr < HI_OBP_ADDRESS? */
60 blu,pn %xcc, obp_iaddr_patch
63 /* These two instructions are patched by paginig_init(). */
64 sparc64_vpte_patchme1:
66 sparc64_vpte_patchme2:
69 /* With kernel PGD in %g5, branch back into dtlb_backend. */
70 ba,pt %xcc, sparc64_kpte_continue
71 andn %g1, 0x3, %g1 /* Finish PMD offset adjustment. */
74 /* Restore previous TAG_ACCESS, %g5 is zero, and we will
75 * skip over the trap instruction so that the top level
76 * TLB miss handler will thing this %g5 value is just an
77 * invalid PTE, thus branching to full fault processing.
80 stxa %g4, [%g1 + %g1] ASI_DMMU
83 .globl obp_iaddr_patch
85 /* These two instructions patched by inherit_prom_mappings(). */
89 /* Behave as if we are at TL0. */
91 rdpr %tpc, %g4 /* Find original faulting iaddr */
92 srlx %g4, 13, %g4 /* Throw out context bits */
93 sllx %g4, 13, %g4 /* g4 has vpn + ctx0 now */
95 /* Restore previous TAG_ACCESS. */
97 stxa %g4, [%g1 + %g1] ASI_IMMU
104 /* Load PMD, is it valid? */
105 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
109 /* Get PTE offset. */
115 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
116 brgez,pn %g5, longpath
119 /* TLB load and return from trap. */
120 stxa %g5, [%g0] ASI_ITLB_DATA_IN
123 .globl obp_daddr_patch
125 /* These two instructions patched by inherit_prom_mappings(). */
129 /* Get PMD offset. */
134 /* Load PMD, is it valid? */
135 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
139 /* Get PTE offset. */
145 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
146 brgez,pn %g5, longpath
149 /* TLB load and return from trap. */
150 stxa %g5, [%g0] ASI_DTLB_DATA_IN
154 * On a first level data miss, check whether this is to the OBP range (note
155 * that such accesses can be made by prom, as well as by kernel using
156 * prom_getproperty on "address"), and if so, do not use vpte access ...
157 * rather, use information saved during inherit_prom_mappings() using 8k
161 /* Load 0xf0000000, which is LOW_OBP_ADDRESS. */
165 /* Is addr >= LOW_OBP_ADDRESS? */
167 blu,pn %xcc, vmalloc_addr
170 /* Load 0x100000000, which is HI_OBP_ADDRESS. */
173 /* Is addr < HI_OBP_ADDRESS? */
175 blu,pn %xcc, obp_daddr_patch
179 /* If we get here, a vmalloc addr accessed, load kernel VPTE. */
180 ldxa [%g3 + %g6] ASI_N, %g5
181 brgez,pn %g5, longpath
184 /* PTE is valid, load into TLB and return from trap. */
185 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
188 /* This is trivial with the new code... */
191 sethi %hi(TSTATE_PEF), %g4 ! IEU0
197 andcc %g5, FPRS_FEF, %g0
201 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
204 109: or %g7, %lo(109b), %g7
206 ba,a,pt %xcc, rtrap_clr_l6
208 1: ldub [%g6 + TI_FPSAVED], %g5 ! Load Group
209 wr %g0, FPRS_FEF, %fprs ! LSU Group+4bubbles
210 andcc %g5, FPRS_FEF, %g0 ! IEU1 Group
211 be,a,pt %icc, 1f ! CTI
213 ldx [%g6 + TI_GSR], %g7 ! Load Group
214 1: andcc %g5, FPRS_DL, %g0 ! IEU1
215 bne,pn %icc, 2f ! CTI
217 andcc %g5, FPRS_DU, %g0 ! IEU1 Group
218 bne,pn %icc, 1f ! CTI
248 b,pt %xcc, fpdis_exit2
250 1: mov SECONDARY_CONTEXT, %g3
251 add %g6, TI_FPREGS + 0x80, %g1
254 ldxa [%g3] ASI_DMMU, %g5
257 stxa %g2, [%g3] ASI_DMMU
259 add %g6, TI_FPREGS + 0xc0, %g2
262 ldda [%g1] ASI_BLK_S, %f32 ! grrr, where is ASI_BLK_NUCLEUS 8-(
263 ldda [%g2] ASI_BLK_S, %f48
275 b,pt %xcc, fpdis_exit
277 2: andcc %g5, FPRS_DU, %g0
280 mov SECONDARY_CONTEXT, %g3
282 ldxa [%g3] ASI_DMMU, %g5
283 add %g6, TI_FPREGS, %g1
286 stxa %g2, [%g3] ASI_DMMU
288 add %g6, TI_FPREGS + 0x40, %g2
289 faddd %f32, %f34, %f36
290 fmuld %f32, %f34, %f38
291 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
292 ldda [%g2] ASI_BLK_S, %f16
293 faddd %f32, %f34, %f40
294 fmuld %f32, %f34, %f42
295 faddd %f32, %f34, %f44
296 fmuld %f32, %f34, %f46
297 faddd %f32, %f34, %f48
298 fmuld %f32, %f34, %f50
299 faddd %f32, %f34, %f52
300 fmuld %f32, %f34, %f54
301 faddd %f32, %f34, %f56
302 fmuld %f32, %f34, %f58
303 faddd %f32, %f34, %f60
304 fmuld %f32, %f34, %f62
306 ba,pt %xcc, fpdis_exit
308 3: mov SECONDARY_CONTEXT, %g3
309 add %g6, TI_FPREGS, %g1
310 ldxa [%g3] ASI_DMMU, %g5
313 stxa %g2, [%g3] ASI_DMMU
316 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
317 ldda [%g1 + %g2] ASI_BLK_S, %f16
319 ldda [%g1] ASI_BLK_S, %f32
320 ldda [%g1 + %g2] ASI_BLK_S, %f48
323 stxa %g5, [%g3] ASI_DMMU
327 ldx [%g6 + TI_XFSR], %fsr
329 or %g3, %g4, %g3 ! anal...
331 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
337 add %sp, PTREGS_OFF, %o0
341 .globl do_fpother_check_fitos
343 do_fpother_check_fitos:
344 sethi %hi(fp_other_bounce - 4), %g7
345 or %g7, %lo(fp_other_bounce - 4), %g7
347 /* NOTE: Need to preserve %g7 until we fully commit
348 * to the fitos fixup.
350 stx %fsr, [%g6 + TI_XFSR]
352 andcc %g3, TSTATE_PRIV, %g0
353 bne,pn %xcc, do_fptrap_after_fsr
355 ldx [%g6 + TI_XFSR], %g3
358 cmp %g1, 2 ! Unfinished FP-OP
359 bne,pn %xcc, do_fptrap_after_fsr
360 sethi %hi(1 << 23), %g1 ! Inexact
362 bne,pn %xcc, do_fptrap_after_fsr
364 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
365 #define FITOS_MASK 0xc1f83fe0
366 #define FITOS_COMPARE 0x81a01880
367 sethi %hi(FITOS_MASK), %g1
368 or %g1, %lo(FITOS_MASK), %g1
370 sethi %hi(FITOS_COMPARE), %g2
371 or %g2, %lo(FITOS_COMPARE), %g2
373 bne,pn %xcc, do_fptrap_after_fsr
375 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
376 sethi %hi(fitos_table_1), %g1
378 or %g1, %lo(fitos_table_1), %g1
381 ba,pt %xcc, fitos_emul_continue
418 sethi %hi(fitos_table_2), %g1
420 or %g1, %lo(fitos_table_2), %g1
424 ba,pt %xcc, fitos_emul_fini
461 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
467 stx %fsr, [%g6 + TI_XFSR]
469 ldub [%g6 + TI_FPSAVED], %g3
472 stb %g3, [%g6 + TI_FPSAVED]
474 stx %g3, [%g6 + TI_GSR]
475 mov SECONDARY_CONTEXT, %g3
476 ldxa [%g3] ASI_DMMU, %g5
479 stxa %g2, [%g3] ASI_DMMU
481 add %g6, TI_FPREGS, %g2
482 andcc %g1, FPRS_DL, %g0
485 stda %f0, [%g2] ASI_BLK_S
486 stda %f16, [%g2 + %g3] ASI_BLK_S
487 andcc %g1, FPRS_DU, %g0
490 stda %f32, [%g2] ASI_BLK_S
491 stda %f48, [%g2 + %g3] ASI_BLK_S
492 5: mov SECONDARY_CONTEXT, %g1
494 stxa %g5, [%g1] ASI_DMMU
500 sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2
502 .globl cheetah_plus_patch_fpdis
503 cheetah_plus_patch_fpdis:
504 /* We configure the dTLB512_0 for 4MB pages and the
505 * dTLB512_1 for 8K pages when in context zero.
507 sethi %hi(cplus_fptrap_1), %o0
508 lduw [%o0 + %lo(cplus_fptrap_1)], %o1
510 set cplus_fptrap_insn_1, %o2
513 set cplus_fptrap_insn_2, %o2
516 set cplus_fptrap_insn_3, %o2
519 set cplus_fptrap_insn_4, %o2
526 /* The registers for cross calls will be:
528 * DATA 0: [low 32-bits] Address of function to call, jmp to this
529 * [high 32-bits] MMU Context Argument 0, place in %g5
530 * DATA 1: Address Argument 1, place in %g6
531 * DATA 2: Address Argument 2, place in %g7
533 * With this method we can do most of the cross-call tlb/cache
534 * flushing very quickly.
536 * Current CPU's IRQ worklist table is locked into %g1,
544 ldxa [%g3 + %g0] ASI_INTR_R, %g3
545 sethi %hi(KERNBASE), %g4
547 bgeu,pn %xcc, do_ivec_xcall
549 stxa %g0, [%g0] ASI_INTR_RECEIVE
552 sethi %hi(ivector_table), %g2
554 or %g2, %lo(ivector_table), %g2
556 ldx [%g3 + 0x08], %g2 /* irq_info */
557 ldub [%g3 + 0x04], %g4 /* pil */
558 brz,pn %g2, do_ivec_spurious
563 lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
564 stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
565 stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
566 wr %g2, 0x0, %set_softint
571 ldxa [%g1 + %g0] ASI_INTR_R, %g1
574 ldxa [%g7 + %g0] ASI_INTR_R, %g7
575 stxa %g0, [%g0] ASI_INTR_RECEIVE
585 stw %g3, [%g6 + 0x00] /* irq_work(cpu, 0) = bucket */
588 wrpr %g5, PSTATE_IG | PSTATE_AG, %pstate
591 109: or %g7, %lo(109b), %g7
592 call catch_disabled_ivec
593 add %sp, PTREGS_OFF, %o0
597 .globl save_alternate_globals
598 save_alternate_globals: /* %o0 = save_area */
600 andn %o5, PSTATE_IE, %o1
601 wrpr %o1, PSTATE_AG, %pstate
602 stx %g0, [%o0 + 0x00]
603 stx %g1, [%o0 + 0x08]
604 stx %g2, [%o0 + 0x10]
605 stx %g3, [%o0 + 0x18]
606 stx %g4, [%o0 + 0x20]
607 stx %g5, [%o0 + 0x28]
608 stx %g6, [%o0 + 0x30]
609 stx %g7, [%o0 + 0x38]
610 wrpr %o1, PSTATE_IG, %pstate
611 stx %g0, [%o0 + 0x40]
612 stx %g1, [%o0 + 0x48]
613 stx %g2, [%o0 + 0x50]
614 stx %g3, [%o0 + 0x58]
615 stx %g4, [%o0 + 0x60]
616 stx %g5, [%o0 + 0x68]
617 stx %g6, [%o0 + 0x70]
618 stx %g7, [%o0 + 0x78]
619 wrpr %o1, PSTATE_MG, %pstate
620 stx %g0, [%o0 + 0x80]
621 stx %g1, [%o0 + 0x88]
622 stx %g2, [%o0 + 0x90]
623 stx %g3, [%o0 + 0x98]
624 stx %g4, [%o0 + 0xa0]
625 stx %g5, [%o0 + 0xa8]
626 stx %g6, [%o0 + 0xb0]
627 stx %g7, [%o0 + 0xb8]
628 wrpr %o5, 0x0, %pstate
632 .globl restore_alternate_globals
633 restore_alternate_globals: /* %o0 = save_area */
635 andn %o5, PSTATE_IE, %o1
636 wrpr %o1, PSTATE_AG, %pstate
637 ldx [%o0 + 0x00], %g0
638 ldx [%o0 + 0x08], %g1
639 ldx [%o0 + 0x10], %g2
640 ldx [%o0 + 0x18], %g3
641 ldx [%o0 + 0x20], %g4
642 ldx [%o0 + 0x28], %g5
643 ldx [%o0 + 0x30], %g6
644 ldx [%o0 + 0x38], %g7
645 wrpr %o1, PSTATE_IG, %pstate
646 ldx [%o0 + 0x40], %g0
647 ldx [%o0 + 0x48], %g1
648 ldx [%o0 + 0x50], %g2
649 ldx [%o0 + 0x58], %g3
650 ldx [%o0 + 0x60], %g4
651 ldx [%o0 + 0x68], %g5
652 ldx [%o0 + 0x70], %g6
653 ldx [%o0 + 0x78], %g7
654 wrpr %o1, PSTATE_MG, %pstate
655 ldx [%o0 + 0x80], %g0
656 ldx [%o0 + 0x88], %g1
657 ldx [%o0 + 0x90], %g2
658 ldx [%o0 + 0x98], %g3
659 ldx [%o0 + 0xa0], %g4
660 ldx [%o0 + 0xa8], %g5
661 ldx [%o0 + 0xb0], %g6
662 ldx [%o0 + 0xb8], %g7
663 wrpr %o5, 0x0, %pstate
669 ldx [%o0 + PT_V9_TSTATE], %o1
673 stx %o1, [%o0 + PT_V9_G1]
675 ldx [%o0 + PT_V9_TSTATE], %o1
676 ldx [%o0 + PT_V9_G1], %o2
677 or %g0, %ulo(TSTATE_ICC), %o3
684 stx %o1, [%o0 + PT_V9_TSTATE]
686 .globl utrap, utrap_ill
687 utrap: brz,pn %g1, etrap
692 andn %l6, TSTATE_CWP, %l6
693 wrpr %l6, %l7, %tstate
700 add %sp, PTREGS_OFF, %o0
704 /* XXX Here is stuff we still need to write... -DaveM XXX */
705 .globl netbsd_syscall
710 /* These next few routines must be sure to clear the
711 * SFSR FaultValid bit so that the fast tlb data protection
712 * handler does not flush the wrong context and lock up the
715 .globl __do_data_access_exception
716 .globl __do_data_access_exception_tl1
717 __do_data_access_exception_tl1:
719 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
722 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
723 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
724 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
726 ba,pt %xcc, winfix_dax
728 __do_data_access_exception:
730 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
733 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
734 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
735 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
739 109: or %g7, %lo(109b), %g7
742 call data_access_exception
743 add %sp, PTREGS_OFF, %o0
747 .globl __do_instruction_access_exception
748 .globl __do_instruction_access_exception_tl1
749 __do_instruction_access_exception_tl1:
751 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
754 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
755 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
756 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
760 109: or %g7, %lo(109b), %g7
763 call instruction_access_exception_tl1
764 add %sp, PTREGS_OFF, %o0
768 __do_instruction_access_exception:
770 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
773 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
774 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
775 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
779 109: or %g7, %lo(109b), %g7
782 call instruction_access_exception
783 add %sp, PTREGS_OFF, %o0
787 /* This is the trap handler entry point for ECC correctable
788 * errors. They are corrected, but we listen for the trap
789 * so that the event can be logged.
791 * Disrupting errors are either:
792 * 1) single-bit ECC errors during UDB reads to system
794 * 2) data parity errors during write-back events
796 * As far as I can make out from the manual, the CEE trap
797 * is only for correctable errors during memory read
798 * accesses by the front-end of the processor.
800 * The code below is only for trap level 1 CEE events,
801 * as it is the only situation where we can safely record
802 * and log. For trap level >1 we just clear the CE bit
803 * in the AFSR and return.
806 /* Our trap handling infrastructure allows us to preserve
807 * two 64-bit values during etrap for arguments to
808 * subsequent C code. Therefore we encode the information
811 * value 1) Full 64-bits of AFAR
812 * value 2) Low 33-bits of AFSR, then bits 33-->42
813 * are UDBL error status and bits 43-->52
814 * are UDBH error status
819 ldxa [%g0] ASI_AFSR, %g1 ! Read AFSR
820 ldxa [%g0] ASI_AFAR, %g2 ! Read AFAR
821 sllx %g1, 31, %g1 ! Clear reserved bits
822 srlx %g1, 31, %g1 ! in AFSR
824 /* NOTE: UltraSparc-I/II have high and low UDB error
825 * registers, corresponding to the two UDB units
826 * present on those chips. UltraSparc-IIi only
827 * has a single UDB, called "SDB" in the manual.
828 * For IIi the upper UDB register always reads
829 * as zero so for our purposes things will just
830 * work with the checks below.
832 ldxa [%g0] ASI_UDBL_ERROR_R, %g3 ! Read UDB-Low error status
833 andcc %g3, (1 << 8), %g4 ! Check CE bit
834 sllx %g3, (64 - 10), %g3 ! Clear reserved bits
835 srlx %g3, (64 - 10), %g3 ! in UDB-Low error status
837 sllx %g3, (33 + 0), %g3 ! Shift up to encoding area
838 or %g1, %g3, %g1 ! Or it in
839 be,pn %xcc, 1f ! Branch if CE bit was clear
841 stxa %g4, [%g0] ASI_UDB_ERROR_W ! Clear CE sticky bit in UDBL
842 membar #Sync ! Synchronize ASI stores
843 1: mov 0x18, %g5 ! Addr of UDB-High error status
844 ldxa [%g5] ASI_UDBH_ERROR_R, %g3 ! Read it
846 andcc %g3, (1 << 8), %g4 ! Check CE bit
847 sllx %g3, (64 - 10), %g3 ! Clear reserved bits
848 srlx %g3, (64 - 10), %g3 ! in UDB-High error status
849 sllx %g3, (33 + 10), %g3 ! Shift up to encoding area
850 or %g1, %g3, %g1 ! Or it in
851 be,pn %xcc, 1f ! Branch if CE bit was clear
855 stxa %g4, [%g5] ASI_UDB_ERROR_W ! Clear CE sticky bit in UDBH
856 membar #Sync ! Synchronize ASI stores
857 1: mov 1, %g5 ! AFSR CE bit is
858 sllx %g5, 20, %g5 ! bit 20
859 stxa %g5, [%g0] ASI_AFSR ! Clear CE sticky bit in AFSR
860 membar #Sync ! Synchronize ASI stores
861 sllx %g2, (64 - 41), %g2 ! Clear reserved bits
862 srlx %g2, (64 - 41), %g2 ! in latched AFAR
864 andn %g2, 0x0f, %g2 ! Finish resv bit clearing
865 mov %g1, %g4 ! Move AFSR+UDB* into save reg
866 mov %g2, %g5 ! Move AFAR into save reg
869 ba,pt %xcc, etrap_irq
875 add %sp, PTREGS_OFF, %o2
876 ba,a,pt %xcc, rtrap_irq
878 /* Capture I/D/E-cache state into per-cpu error scoreboard.
880 * %g1: (TL>=0) ? 1 : 0
885 * %g6: current thread ptr
888 #define CHEETAH_LOG_ERROR \
889 /* Put "TL1" software bit into AFSR. */ \
893 /* Get log entry pointer for this cpu at this trap level. */ \
894 BRANCH_IF_JALAPENO(g2,g3,50f) \
895 ldxa [%g0] ASI_SAFARI_CONFIG, %g2; \
898 and %g2, 0x3ff, %g2; \
899 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2; \
901 and %g2, 0x1f, %g2; \
902 60: sllx %g2, 9, %g2; \
903 sethi %hi(cheetah_error_log), %g3; \
904 ldx [%g3 + %lo(cheetah_error_log)], %g3; \
910 /* %g1 holds pointer to the top of the logging scoreboard */ \
911 ldx [%g1 + 0x0], %g7; \
915 stx %g4, [%g1 + 0x0]; \
916 stx %g5, [%g1 + 0x8]; \
917 add %g1, 0x10, %g1; \
918 /* %g1 now points to D-cache logging area */ \
919 set 0x3ff8, %g2; /* DC_addr mask */ \
920 and %g5, %g2, %g2; /* DC_addr bits of AFAR */ \
922 or %g3, 1, %g3; /* PHYS tag + valid */ \
923 10: ldxa [%g2] ASI_DCACHE_TAG, %g7; \
924 cmp %g3, %g7; /* TAG match? */ \
927 /* Yep, what we want, capture state. */ \
928 stx %g2, [%g1 + 0x20]; \
929 stx %g7, [%g1 + 0x28]; \
930 /* A membar Sync is required before and after utag access. */ \
932 ldxa [%g2] ASI_DCACHE_UTAG, %g7; \
934 stx %g7, [%g1 + 0x30]; \
935 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7; \
936 stx %g7, [%g1 + 0x38]; \
938 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7; \
940 add %g3, (1 << 5), %g3; \
945 add %g1, 0x20, %g1; \
946 13: sethi %hi(1 << 14), %g7; \
952 add %g1, 0x40, %g1; \
953 20: /* %g1 now points to I-cache logging area */ \
954 set 0x1fe0, %g2; /* IC_addr mask */ \
955 and %g5, %g2, %g2; /* IC_addr bits of AFAR */ \
956 sllx %g2, 1, %g2; /* IC_addr[13:6]==VA[12:5] */ \
957 srlx %g5, (13 - 8), %g3; /* Make PTAG */ \
958 andn %g3, 0xff, %g3; /* Mask off undefined bits */ \
959 21: ldxa [%g2] ASI_IC_TAG, %g7; \
960 andn %g7, 0xff, %g7; \
964 /* Yep, what we want, capture state. */ \
965 stx %g2, [%g1 + 0x40]; \
966 stx %g7, [%g1 + 0x48]; \
967 add %g2, (1 << 3), %g2; \
968 ldxa [%g2] ASI_IC_TAG, %g7; \
969 add %g2, (1 << 3), %g2; \
970 stx %g7, [%g1 + 0x50]; \
971 ldxa [%g2] ASI_IC_TAG, %g7; \
972 add %g2, (1 << 3), %g2; \
973 stx %g7, [%g1 + 0x60]; \
974 ldxa [%g2] ASI_IC_TAG, %g7; \
975 stx %g7, [%g1 + 0x68]; \
976 sub %g2, (3 << 3), %g2; \
977 ldxa [%g2] ASI_IC_STAG, %g7; \
978 stx %g7, [%g1 + 0x58]; \
981 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7; \
983 add %g3, (1 << 3), %g3; \
988 add %g1, 0x30, %g1; \
989 23: sethi %hi(1 << 14), %g7; \
995 add %g1, 0x70, %g1; \
996 30: /* %g1 now points to E-cache logging area */ \
997 andn %g5, (32 - 1), %g2; /* E-cache subblock */ \
998 stx %g2, [%g1 + 0x20]; \
999 ldxa [%g2] ASI_EC_TAG_DATA, %g7; \
1000 stx %g7, [%g1 + 0x28]; \
1001 ldxa [%g2] ASI_EC_R, %g0; \
1003 31: ldxa [%g3] ASI_EC_DATA, %g7; \
1004 stx %g7, [%g1 + %g3]; \
1005 add %g3, 0x8, %g3; \
1011 /* These get patched into the trap table at boot time
1012 * once we know we have a cheetah processor.
1014 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
1015 cheetah_fecc_trap_vector:
1017 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1018 andn %g1, DCU_DC | DCU_IC, %g1
1019 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1021 sethi %hi(cheetah_fast_ecc), %g2
1022 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
1024 cheetah_fecc_trap_vector_tl1:
1026 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1027 andn %g1, DCU_DC | DCU_IC, %g1
1028 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1030 sethi %hi(cheetah_fast_ecc), %g2
1031 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
1033 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
1034 cheetah_cee_trap_vector:
1036 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1037 andn %g1, DCU_IC, %g1
1038 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1040 sethi %hi(cheetah_cee), %g2
1041 jmpl %g2 + %lo(cheetah_cee), %g0
1043 cheetah_cee_trap_vector_tl1:
1045 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1046 andn %g1, DCU_IC, %g1
1047 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1049 sethi %hi(cheetah_cee), %g2
1050 jmpl %g2 + %lo(cheetah_cee), %g0
1052 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
1053 cheetah_deferred_trap_vector:
1055 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
1056 andn %g1, DCU_DC | DCU_IC, %g1;
1057 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
1059 sethi %hi(cheetah_deferred_trap), %g2
1060 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
1062 cheetah_deferred_trap_vector_tl1:
1064 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
1065 andn %g1, DCU_DC | DCU_IC, %g1;
1066 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
1068 sethi %hi(cheetah_deferred_trap), %g2
1069 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
1072 /* Cheetah+ specific traps. These are for the new I/D cache parity
1073 * error traps. The first argument to cheetah_plus_parity_handler
1074 * is encoded as follows:
1076 * Bit0: 0=dcache,1=icache
1077 * Bit1: 0=recoverable,1=unrecoverable
1079 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
1080 cheetah_plus_dcpe_trap_vector:
1082 sethi %hi(do_cheetah_plus_data_parity), %g7
1083 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
1090 do_cheetah_plus_data_parity:
1094 call cheetah_plus_parity_error
1095 add %sp, PTREGS_OFF, %o1
1099 cheetah_plus_dcpe_trap_vector_tl1:
1101 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
1102 sethi %hi(do_dcpe_tl1), %g3
1103 jmpl %g3 + %lo(do_dcpe_tl1), %g0
1109 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
1110 cheetah_plus_icpe_trap_vector:
1112 sethi %hi(do_cheetah_plus_insn_parity), %g7
1113 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
1120 do_cheetah_plus_insn_parity:
1124 call cheetah_plus_parity_error
1125 add %sp, PTREGS_OFF, %o1
1129 cheetah_plus_icpe_trap_vector_tl1:
1131 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
1132 sethi %hi(do_icpe_tl1), %g3
1133 jmpl %g3 + %lo(do_icpe_tl1), %g0
1139 /* If we take one of these traps when tl >= 1, then we
1140 * jump to interrupt globals. If some trap level above us
1141 * was also using interrupt globals, we cannot recover.
1142 * We may use all interrupt global registers except %g6.
1144 .globl do_dcpe_tl1, do_icpe_tl1
1146 rdpr %tl, %g1 ! Save original trap level
1147 mov 1, %g2 ! Setup TSTATE checking loop
1148 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
1149 1: wrpr %g2, %tl ! Set trap level to check
1150 rdpr %tstate, %g4 ! Read TSTATE for this level
1151 andcc %g4, %g3, %g0 ! Interrupt globals in use?
1152 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
1153 wrpr %g1, %tl ! Restore original trap level
1154 add %g2, 1, %g2 ! Next trap level
1155 cmp %g2, %g1 ! Hit them all yet?
1156 ble,pt %icc, 1b ! Not yet
1158 wrpr %g1, %tl ! Restore original trap level
1159 do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
1160 /* Reset D-cache parity */
1161 sethi %hi(1 << 16), %g1 ! D-cache size
1162 mov (1 << 5), %g2 ! D-cache line size
1163 sub %g1, %g2, %g1 ! Move down 1 cacheline
1164 1: srl %g1, 14, %g3 ! Compute UTAG
1166 stxa %g3, [%g1] ASI_DCACHE_UTAG
1168 sub %g2, 8, %g3 ! 64-bit data word within line
1170 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
1172 subcc %g3, 8, %g3 ! Next 64-bit data word
1175 subcc %g1, %g2, %g1 ! Next cacheline
1178 ba,pt %xcc, dcpe_icpe_tl1_common
1183 ba,pt %xcc, etraptl1
1184 1: or %g7, %lo(1b), %g7
1186 call cheetah_plus_parity_error
1187 add %sp, PTREGS_OFF, %o1
1192 rdpr %tl, %g1 ! Save original trap level
1193 mov 1, %g2 ! Setup TSTATE checking loop
1194 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
1195 1: wrpr %g2, %tl ! Set trap level to check
1196 rdpr %tstate, %g4 ! Read TSTATE for this level
1197 andcc %g4, %g3, %g0 ! Interrupt globals in use?
1198 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
1199 wrpr %g1, %tl ! Restore original trap level
1200 add %g2, 1, %g2 ! Next trap level
1201 cmp %g2, %g1 ! Hit them all yet?
1202 ble,pt %icc, 1b ! Not yet
1204 wrpr %g1, %tl ! Restore original trap level
1205 do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
1207 sethi %hi(1 << 15), %g1 ! I-cache size
1208 mov (1 << 5), %g2 ! I-cache line size
1210 1: or %g1, (2 << 3), %g3
1211 stxa %g0, [%g3] ASI_IC_TAG
1216 ba,pt %xcc, dcpe_icpe_tl1_common
1221 ba,pt %xcc, etraptl1
1222 1: or %g7, %lo(1b), %g7
1224 call cheetah_plus_parity_error
1225 add %sp, PTREGS_OFF, %o1
1229 dcpe_icpe_tl1_common:
1230 /* Flush D-cache, re-enable D/I caches in DCU and finally
1231 * retry the trapping instruction.
1233 sethi %hi(1 << 16), %g1 ! D-cache size
1234 mov (1 << 5), %g2 ! D-cache line size
1236 1: stxa %g0, [%g1] ASI_DCACHE_TAG
1241 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1242 or %g1, (DCU_DC | DCU_IC), %g1
1243 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1247 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1248 * in the trap table. That code has done a memory barrier
1249 * and has disabled both the I-cache and D-cache in the DCU
1250 * control register. The I-cache is disabled so that we may
1251 * capture the corrupted cache line, and the D-cache is disabled
1252 * because corrupt data may have been placed there and we don't
1253 * want to reference it.
1255 * %g1 is one if this trap occurred at %tl >= 1.
1257 * Next, we turn off error reporting so that we don't recurse.
1259 .globl cheetah_fast_ecc
1261 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1262 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1263 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1266 /* Fetch and clear AFSR/AFAR */
1267 ldxa [%g0] ASI_AFSR, %g4
1268 ldxa [%g0] ASI_AFAR, %g5
1269 stxa %g4, [%g0] ASI_AFSR
1276 ba,pt %xcc, etrap_irq
1280 call cheetah_fecc_handler
1281 add %sp, PTREGS_OFF, %o0
1282 ba,a,pt %xcc, rtrap_irq
1284 /* Our caller has disabled I-cache and performed membar Sync. */
1287 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1288 andn %g2, ESTATE_ERROR_CEEN, %g2
1289 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1292 /* Fetch and clear AFSR/AFAR */
1293 ldxa [%g0] ASI_AFSR, %g4
1294 ldxa [%g0] ASI_AFAR, %g5
1295 stxa %g4, [%g0] ASI_AFSR
1302 ba,pt %xcc, etrap_irq
1306 call cheetah_cee_handler
1307 add %sp, PTREGS_OFF, %o0
1308 ba,a,pt %xcc, rtrap_irq
1310 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1311 .globl cheetah_deferred_trap
1312 cheetah_deferred_trap:
1313 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1314 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1315 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1318 /* Fetch and clear AFSR/AFAR */
1319 ldxa [%g0] ASI_AFSR, %g4
1320 ldxa [%g0] ASI_AFAR, %g5
1321 stxa %g4, [%g0] ASI_AFSR
1328 ba,pt %xcc, etrap_irq
1332 call cheetah_deferred_handler
1333 add %sp, PTREGS_OFF, %o0
1334 ba,a,pt %xcc, rtrap_irq
1339 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1341 sethi %hi(109f), %g7
1343 109: or %g7, %lo(109b), %g7
1345 add %sp, PTREGS_OFF, %o0
1354 /* Setup %g4/%g5 now as they are used in the
1359 ldxa [%g4] ASI_DMMU, %g4
1360 ldxa [%g3] ASI_DMMU, %g5
1361 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1363 bgu,pn %icc, winfix_mna
1366 1: sethi %hi(109f), %g7
1368 109: or %g7, %lo(109b), %g7
1371 call mem_address_unaligned
1372 add %sp, PTREGS_OFF, %o0
1378 sethi %hi(109f), %g7
1380 ldxa [%g4] ASI_DMMU, %g5
1381 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1384 ldxa [%g4] ASI_DMMU, %g4
1386 109: or %g7, %lo(109b), %g7
1390 add %sp, PTREGS_OFF, %o0
1396 sethi %hi(109f), %g7
1398 ldxa [%g4] ASI_DMMU, %g5
1399 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1402 ldxa [%g4] ASI_DMMU, %g4
1404 109: or %g7, %lo(109b), %g7
1408 add %sp, PTREGS_OFF, %o0
1412 .globl breakpoint_trap
1414 call sparc_breakpoint
1415 add %sp, PTREGS_OFF, %o0
1419 #if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
1420 defined(CONFIG_SOLARIS_EMUL_MODULE)
1421 /* SunOS uses syscall zero as the 'indirect syscall' it looks
1422 * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
1423 * This is complete brain damage.
1429 cmp %o0, NR_SYSCALLS
1432 sethi %hi(sunos_nosys), %l6
1434 or %l6, %lo(sunos_nosys), %l6
1435 1: sethi %hi(sunos_sys_table), %l7
1436 or %l7, %lo(sunos_sys_table), %l7
1437 lduw [%l7 + %o0], %l6
1451 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1452 b,pt %xcc, ret_sys_call
1453 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1455 /* SunOS getuid() returns uid in %o0 and euid in %o1 */
1458 call sys32_geteuid16
1461 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1462 b,pt %xcc, ret_sys_call
1463 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1465 /* SunOS getgid() returns gid in %o0 and egid in %o1 */
1468 call sys32_getegid16
1471 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1472 b,pt %xcc, ret_sys_call
1473 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1476 /* SunOS's execv() call only specifies the argv argument, the
1477 * environment settings are the same as the calling processes.
1481 sethi %hi(sparc_execve), %g1
1482 ba,pt %xcc, execve_merge
1483 or %g1, %lo(sparc_execve), %g1
1484 #ifdef CONFIG_COMPAT
1487 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1490 sethi %hi(sparc32_execve), %g1
1491 or %g1, %lo(sparc32_execve), %g1
1496 add %sp, PTREGS_OFF, %o0
1498 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1499 .globl sys_sigsuspend, sys_rt_sigsuspend
1500 .globl sys_rt_sigreturn
1502 .globl sys_sigaltstack
1504 sys_pipe: ba,pt %xcc, sparc_pipe
1505 add %sp, PTREGS_OFF, %o0
1506 sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1507 add %sp, PTREGS_OFF, %o0
1508 sys_memory_ordering:
1509 ba,pt %xcc, sparc_memory_ordering
1510 add %sp, PTREGS_OFF, %o1
1511 sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1512 add %i6, STACK_BIAS, %o2
1513 #ifdef CONFIG_COMPAT
1514 .globl sys32_sigstack
1515 sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1517 .globl sys32_sigaltstack
1519 ba,pt %xcc, do_sys32_sigaltstack
1523 sys_sigsuspend: add %sp, PTREGS_OFF, %o0
1525 add %o7, 1f-.-4, %o7
1527 sys_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1528 add %sp, PTREGS_OFF, %o2
1529 call do_rt_sigsuspend
1530 add %o7, 1f-.-4, %o7
1532 #ifdef CONFIG_COMPAT
1533 .globl sys32_rt_sigsuspend
1534 sys32_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1536 add %sp, PTREGS_OFF, %o2
1537 call do_rt_sigsuspend32
1538 add %o7, 1f-.-4, %o7
1540 /* NOTE: %o0 has a correct value already */
1541 sys_sigpause: add %sp, PTREGS_OFF, %o1
1543 add %o7, 1f-.-4, %o7
1545 #ifdef CONFIG_COMPAT
1546 .globl sys32_sigreturn
1548 add %sp, PTREGS_OFF, %o0
1550 add %o7, 1f-.-4, %o7
1554 add %sp, PTREGS_OFF, %o0
1555 call do_rt_sigreturn
1556 add %o7, 1f-.-4, %o7
1558 #ifdef CONFIG_COMPAT
1559 .globl sys32_rt_sigreturn
1561 add %sp, PTREGS_OFF, %o0
1562 call do_rt_sigreturn32
1563 add %o7, 1f-.-4, %o7
1566 sys_ptrace: add %sp, PTREGS_OFF, %o0
1568 add %o7, 1f-.-4, %o7
1571 1: ldx [%curptr + TI_FLAGS], %l5
1572 andcc %l5, _TIF_SYSCALL_TRACE, %g0
1581 /* This is how fork() was meant to be done, 8 instruction entry.
1583 * I questioned the following code briefly, let me clear things
1584 * up so you must not reason on it like I did.
1586 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1587 * need it here because the only piece of window state we copy to
1588 * the child is the CWP register. Even if the parent sleeps,
1589 * we are safe because we stuck it into pt_regs of the parent
1590 * so it will not change.
1592 * XXX This raises the question, whether we can do the same on
1593 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1594 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1595 * XXX fork_kwim in UREG_G1 (global registers are considered
1596 * XXX volatile across a system call in the sparc ABI I think
1597 * XXX if it isn't we can use regs->y instead, anyone who depends
1598 * XXX upon the Y register being preserved across a fork deserves
1601 * In fact we should take advantage of that fact for other things
1602 * during system calls...
1604 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1605 .globl ret_from_syscall
1607 sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1608 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1609 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1610 ba,pt %xcc, sys_clone
1616 ba,pt %xcc, sparc_do_fork
1617 add %sp, PTREGS_OFF, %o2
1619 /* Clear SPARC_FLAG_NEWCHILD, switch_to leaves thread.flags in
1620 * %o7 for us. Check performance counter stuff too.
1622 andn %o7, _TIF_NEWCHILD, %l0
1623 stx %l0, [%g6 + TI_FLAGS]
1626 andcc %l0, _TIF_PERFCTR, %g0
1629 ldx [%g6 + TI_PCR], %o7
1632 /* Blackbird errata workaround. See commentary in
1633 * smp.c:smp_percpu_timer_interrupt() for more
1639 99: wr %g0, %g0, %pic
1642 1: b,pt %xcc, ret_sys_call
1643 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1644 sparc_exit: wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV), %pstate
1648 wrpr %g3, 0x0, %cansave
1649 wrpr %g0, 0x0, %otherwin
1650 wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE), %pstate
1651 ba,pt %xcc, sys_exit
1652 stb %g0, [%g6 + TI_WSAVED]
1654 linux_sparc_ni_syscall:
1655 sethi %hi(sys_ni_syscall), %l7
1657 or %l7, %lo(sys_ni_syscall), %l7
1659 linux_syscall_trace32:
1669 linux_syscall_trace:
1680 /* Linux 32-bit and SunOS system calls enter here... */
1682 .globl linux_sparc_syscall32
1683 linux_sparc_syscall32:
1684 /* Direct access to user regs, much faster. */
1685 cmp %g1, NR_SYSCALLS ! IEU1 Group
1686 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1687 srl %i0, 0, %o0 ! IEU0
1688 sll %g1, 2, %l4 ! IEU0 Group
1689 #ifdef SYSCALL_TRACING
1690 call syscall_trace_entry
1691 add %sp, PTREGS_OFF, %o0
1694 srl %i4, 0, %o4 ! IEU1
1695 lduw [%l7 + %l4], %l7 ! Load
1696 srl %i1, 0, %o1 ! IEU0 Group
1697 ldx [%curptr + TI_FLAGS], %l0 ! Load
1699 srl %i5, 0, %o5 ! IEU1
1700 srl %i2, 0, %o2 ! IEU0 Group
1701 andcc %l0, _TIF_SYSCALL_TRACE, %g0 ! IEU0 Group
1702 bne,pn %icc, linux_syscall_trace32 ! CTI
1704 call %l7 ! CTI Group brk forced
1705 srl %i3, 0, %o3 ! IEU0
1708 /* Linux native and SunOS system calls enter here... */
1710 .globl linux_sparc_syscall, ret_sys_call
1711 linux_sparc_syscall:
1712 /* Direct access to user regs, much faster. */
1713 cmp %g1, NR_SYSCALLS ! IEU1 Group
1714 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1716 sll %g1, 2, %l4 ! IEU0 Group
1717 #ifdef SYSCALL_TRACING
1718 call syscall_trace_entry
1719 add %sp, PTREGS_OFF, %o0
1723 lduw [%l7 + %l4], %l7 ! Load
1724 4: mov %i2, %o2 ! IEU0 Group
1725 ldx [%curptr + TI_FLAGS], %l0 ! Load
1728 mov %i4, %o4 ! IEU0 Group
1729 andcc %l0, _TIF_SYSCALL_TRACE, %g0 ! IEU1 Group+1 bubble
1730 bne,pn %icc, linux_syscall_trace ! CTI Group
1732 2: call %l7 ! CTI Group brk forced
1736 3: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1738 #ifdef SYSCALL_TRACING
1740 call syscall_trace_exit
1741 add %sp, PTREGS_OFF, %o0
1744 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1745 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1747 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1750 /* Check if force_successful_syscall_return()
1753 ldx [%curptr + TI_FLAGS], %l0
1754 andcc %l0, _TIF_SYSCALL_SUCCESS, %g0
1756 andn %l0, _TIF_SYSCALL_SUCCESS, %l0
1758 stx %l0, [%curptr + TI_FLAGS]
1761 cmp %o0, -ERESTART_RESTARTBLOCK
1763 andcc %l0, _TIF_SYSCALL_TRACE, %l6
1765 /* System call success, clear Carry condition code. */
1767 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1768 bne,pn %icc, linux_syscall_trace2
1769 add %l1, 0x4, %l2 ! npc = npc+4
1770 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1771 ba,pt %xcc, rtrap_clr_l6
1772 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1775 /* System call failure, set Carry condition code.
1776 * Also, get abs(errno) to return to the process.
1778 andcc %l0, _TIF_SYSCALL_TRACE, %l6
1781 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1783 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1784 bne,pn %icc, linux_syscall_trace2
1785 add %l1, 0x4, %l2 ! npc = npc+4
1786 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1789 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1790 linux_syscall_trace2:
1793 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1795 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1798 .globl __flushw_user
1803 1: save %sp, -128, %sp
1809 restore %g0, %g0, %g0