1 /* $Id: entry.S,v 1.144 2002/02/09 19:49:30 davem Exp $
2 * arch/sparc64/kernel/entry.S: Sparc64 trap low-level entry points.
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 * Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
10 #include <linux/config.h>
11 #include <linux/errno.h>
16 #include <asm/ptrace.h>
18 #include <asm/signal.h>
19 #include <asm/pgtable.h>
20 #include <asm/processor.h>
21 #include <asm/visasm.h>
22 #include <asm/estate.h>
23 #include <asm/auxio.h>
25 /* #define SYSCALL_TRACING 1 */
29 #define NR_SYSCALLS 284 /* Each OS is different... */
34 .globl sparc64_vpte_patchme1
35 .globl sparc64_vpte_patchme2
37 * On a second level vpte miss, check whether the original fault is to the OBP
38 * range (note that this is only possible for instruction miss, data misses to
39 * obp range do not use vpte). If so, go back directly to the faulting address.
40 * This is because we want to read the tpc, otherwise we have no way of knowing
41 * the 8k aligned faulting address if we are using >8k kernel pagesize. This
42 * also ensures no vpte range addresses are dropped into tlb while obp is
43 * executing (see inherit_locked_prom_mappings() rant).
46 /* Load 0xf0000000, which is LOW_OBP_ADDRESS. */
50 /* Is addr >= LOW_OBP_ADDRESS? */
52 blu,pn %xcc, sparc64_vpte_patchme1
55 /* Load 0x100000000, which is HI_OBP_ADDRESS. */
58 /* Is addr < HI_OBP_ADDRESS? */
60 blu,pn %xcc, obp_iaddr_patch
63 /* These two instructions are patched by paginig_init(). */
64 sparc64_vpte_patchme1:
66 sparc64_vpte_patchme2:
69 /* With kernel PGD in %g5, branch back into dtlb_backend. */
70 ba,pt %xcc, sparc64_kpte_continue
71 andn %g1, 0x3, %g1 /* Finish PMD offset adjustment. */
74 /* Restore previous TAG_ACCESS, %g5 is zero, and we will
75 * skip over the trap instruction so that the top level
76 * TLB miss handler will thing this %g5 value is just an
77 * invalid PTE, thus branching to full fault processing.
80 stxa %g4, [%g1 + %g1] ASI_DMMU
83 .globl obp_iaddr_patch
85 /* These two instructions patched by inherit_prom_mappings(). */
89 /* Behave as if we are at TL0. */
91 rdpr %tpc, %g4 /* Find original faulting iaddr */
92 srlx %g4, 13, %g4 /* Throw out context bits */
93 sllx %g4, 13, %g4 /* g4 has vpn + ctx0 now */
95 /* Restore previous TAG_ACCESS. */
97 stxa %g4, [%g1 + %g1] ASI_IMMU
104 /* Load PMD, is it valid? */
105 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
109 /* Get PTE offset. */
115 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
116 brgez,pn %g5, longpath
119 /* TLB load and return from trap. */
120 stxa %g5, [%g0] ASI_ITLB_DATA_IN
123 .globl obp_daddr_patch
125 /* These two instructions patched by inherit_prom_mappings(). */
129 /* Get PMD offset. */
134 /* Load PMD, is it valid? */
135 lduwa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
139 /* Get PTE offset. */
145 ldxa [%g5 + %g6] ASI_PHYS_USE_EC, %g5
146 brgez,pn %g5, longpath
149 /* TLB load and return from trap. */
150 stxa %g5, [%g0] ASI_DTLB_DATA_IN
154 * On a first level data miss, check whether this is to the OBP range (note
155 * that such accesses can be made by prom, as well as by kernel using
156 * prom_getproperty on "address"), and if so, do not use vpte access ...
157 * rather, use information saved during inherit_prom_mappings() using 8k
161 /* Load 0xf0000000, which is LOW_OBP_ADDRESS. */
165 /* Is addr >= LOW_OBP_ADDRESS? */
167 blu,pn %xcc, vmalloc_addr
170 /* Load 0x100000000, which is HI_OBP_ADDRESS. */
173 /* Is addr < HI_OBP_ADDRESS? */
175 blu,pn %xcc, obp_daddr_patch
179 /* If we get here, a vmalloc addr accessed, load kernel VPTE. */
180 ldxa [%g3 + %g6] ASI_N, %g5
181 brgez,pn %g5, longpath
184 /* PTE is valid, load into TLB and return from trap. */
185 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
188 /* This is trivial with the new code... */
191 sethi %hi(TSTATE_PEF), %g4 ! IEU0
197 andcc %g5, FPRS_FEF, %g0
201 /* Legal state when DCR_IFPOE is set in Cheetah %dcr. */
204 109: or %g7, %lo(109b), %g7
206 ba,a,pt %xcc, rtrap_clr_l6
208 1: ldub [%g6 + TI_FPSAVED], %g5 ! Load Group
209 wr %g0, FPRS_FEF, %fprs ! LSU Group+4bubbles
210 andcc %g5, FPRS_FEF, %g0 ! IEU1 Group
211 be,a,pt %icc, 1f ! CTI
213 ldx [%g6 + TI_GSR], %g7 ! Load Group
214 1: andcc %g5, FPRS_DL, %g0 ! IEU1
215 bne,pn %icc, 2f ! CTI
217 andcc %g5, FPRS_DU, %g0 ! IEU1 Group
218 bne,pn %icc, 1f ! CTI
248 b,pt %xcc, fpdis_exit2
250 1: mov SECONDARY_CONTEXT, %g3
251 add %g6, TI_FPREGS + 0x80, %g1
254 ldxa [%g3] ASI_DMMU, %g5
257 stxa %g2, [%g3] ASI_DMMU
259 add %g6, TI_FPREGS + 0xc0, %g2
262 ldda [%g1] ASI_BLK_S, %f32 ! grrr, where is ASI_BLK_NUCLEUS 8-(
263 ldda [%g2] ASI_BLK_S, %f48
275 b,pt %xcc, fpdis_exit
277 2: andcc %g5, FPRS_DU, %g0
280 mov SECONDARY_CONTEXT, %g3
282 ldxa [%g3] ASI_DMMU, %g5
283 add %g6, TI_FPREGS, %g1
286 stxa %g2, [%g3] ASI_DMMU
288 add %g6, TI_FPREGS + 0x40, %g2
289 faddd %f32, %f34, %f36
290 fmuld %f32, %f34, %f38
291 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
292 ldda [%g2] ASI_BLK_S, %f16
293 faddd %f32, %f34, %f40
294 fmuld %f32, %f34, %f42
295 faddd %f32, %f34, %f44
296 fmuld %f32, %f34, %f46
297 faddd %f32, %f34, %f48
298 fmuld %f32, %f34, %f50
299 faddd %f32, %f34, %f52
300 fmuld %f32, %f34, %f54
301 faddd %f32, %f34, %f56
302 fmuld %f32, %f34, %f58
303 faddd %f32, %f34, %f60
304 fmuld %f32, %f34, %f62
306 ba,pt %xcc, fpdis_exit
308 3: mov SECONDARY_CONTEXT, %g3
309 add %g6, TI_FPREGS, %g1
310 ldxa [%g3] ASI_DMMU, %g5
313 stxa %g2, [%g3] ASI_DMMU
316 ldda [%g1] ASI_BLK_S, %f0 ! grrr, where is ASI_BLK_NUCLEUS 8-(
317 ldda [%g1 + %g2] ASI_BLK_S, %f16
319 ldda [%g1] ASI_BLK_S, %f32
320 ldda [%g1 + %g2] ASI_BLK_S, %f48
323 stxa %g5, [%g3] ASI_DMMU
327 ldx [%g6 + TI_XFSR], %fsr
329 or %g3, %g4, %g3 ! anal...
331 wr %g0, FPRS_FEF, %fprs ! clean DU/DL bits
337 add %sp, PTREGS_OFF, %o0
341 .globl do_fpother_check_fitos
343 do_fpother_check_fitos:
344 sethi %hi(fp_other_bounce - 4), %g7
345 or %g7, %lo(fp_other_bounce - 4), %g7
347 /* NOTE: Need to preserve %g7 until we fully commit
348 * to the fitos fixup.
350 stx %fsr, [%g6 + TI_XFSR]
352 andcc %g3, TSTATE_PRIV, %g0
353 bne,pn %xcc, do_fptrap_after_fsr
355 ldx [%g6 + TI_XFSR], %g3
358 cmp %g1, 2 ! Unfinished FP-OP
359 bne,pn %xcc, do_fptrap_after_fsr
360 sethi %hi(1 << 23), %g1 ! Inexact
362 bne,pn %xcc, do_fptrap_after_fsr
364 lduwa [%g1] ASI_AIUP, %g3 ! This cannot ever fail
365 #define FITOS_MASK 0xc1f83fe0
366 #define FITOS_COMPARE 0x81a01880
367 sethi %hi(FITOS_MASK), %g1
368 or %g1, %lo(FITOS_MASK), %g1
370 sethi %hi(FITOS_COMPARE), %g2
371 or %g2, %lo(FITOS_COMPARE), %g2
373 bne,pn %xcc, do_fptrap_after_fsr
375 std %f62, [%g6 + TI_FPREGS + (62 * 4)]
376 sethi %hi(fitos_table_1), %g1
378 or %g1, %lo(fitos_table_1), %g1
381 ba,pt %xcc, fitos_emul_continue
418 sethi %hi(fitos_table_2), %g1
420 or %g1, %lo(fitos_table_2), %g1
424 ba,pt %xcc, fitos_emul_fini
461 ldd [%g6 + TI_FPREGS + (62 * 4)], %f62
467 stx %fsr, [%g6 + TI_XFSR]
469 ldub [%g6 + TI_FPSAVED], %g3
472 stb %g3, [%g6 + TI_FPSAVED]
474 stx %g3, [%g6 + TI_GSR]
475 mov SECONDARY_CONTEXT, %g3
476 ldxa [%g3] ASI_DMMU, %g5
479 stxa %g2, [%g3] ASI_DMMU
481 add %g6, TI_FPREGS, %g2
482 andcc %g1, FPRS_DL, %g0
485 stda %f0, [%g2] ASI_BLK_S
486 stda %f16, [%g2 + %g3] ASI_BLK_S
487 andcc %g1, FPRS_DU, %g0
490 stda %f32, [%g2] ASI_BLK_S
491 stda %f48, [%g2 + %g3] ASI_BLK_S
492 5: mov SECONDARY_CONTEXT, %g1
494 stxa %g5, [%g1] ASI_DMMU
500 sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2
502 .globl cheetah_plus_patch_fpdis
503 cheetah_plus_patch_fpdis:
504 /* We configure the dTLB512_0 for 4MB pages and the
505 * dTLB512_1 for 8K pages when in context zero.
507 sethi %hi(cplus_fptrap_1), %o0
508 lduw [%o0 + %lo(cplus_fptrap_1)], %o1
510 set cplus_fptrap_insn_1, %o2
513 set cplus_fptrap_insn_2, %o2
516 set cplus_fptrap_insn_3, %o2
519 set cplus_fptrap_insn_4, %o2
526 /* The registers for cross calls will be:
528 * DATA 0: [low 32-bits] Address of function to call, jmp to this
529 * [high 32-bits] MMU Context Argument 0, place in %g5
530 * DATA 1: Address Argument 1, place in %g6
531 * DATA 2: Address Argument 2, place in %g7
533 * With this method we can do most of the cross-call tlb/cache
534 * flushing very quickly.
536 * Current CPU's IRQ worklist table is locked into %g1,
544 ldxa [%g3 + %g0] ASI_INTR_R, %g3
545 sethi %hi(KERNBASE), %g4
547 bgeu,pn %xcc, do_ivec_xcall
549 stxa %g0, [%g0] ASI_INTR_RECEIVE
552 sethi %hi(ivector_table), %g2
554 or %g2, %lo(ivector_table), %g2
556 ldub [%g3 + 0x04], %g4 /* pil */
561 lduw [%g6 + %g4], %g5 /* g5 = irq_work(cpu, pil) */
562 stw %g5, [%g3 + 0x00] /* bucket->irq_chain = g5 */
563 stw %g3, [%g6 + %g4] /* irq_work(cpu, pil) = bucket */
564 wr %g2, 0x0, %set_softint
568 ldxa [%g1 + %g0] ASI_INTR_R, %g1
572 ldxa [%g7 + %g0] ASI_INTR_R, %g7
573 stxa %g0, [%g0] ASI_INTR_RECEIVE
582 .globl save_alternate_globals
583 save_alternate_globals: /* %o0 = save_area */
585 andn %o5, PSTATE_IE, %o1
586 wrpr %o1, PSTATE_AG, %pstate
587 stx %g0, [%o0 + 0x00]
588 stx %g1, [%o0 + 0x08]
589 stx %g2, [%o0 + 0x10]
590 stx %g3, [%o0 + 0x18]
591 stx %g4, [%o0 + 0x20]
592 stx %g5, [%o0 + 0x28]
593 stx %g6, [%o0 + 0x30]
594 stx %g7, [%o0 + 0x38]
595 wrpr %o1, PSTATE_IG, %pstate
596 stx %g0, [%o0 + 0x40]
597 stx %g1, [%o0 + 0x48]
598 stx %g2, [%o0 + 0x50]
599 stx %g3, [%o0 + 0x58]
600 stx %g4, [%o0 + 0x60]
601 stx %g5, [%o0 + 0x68]
602 stx %g6, [%o0 + 0x70]
603 stx %g7, [%o0 + 0x78]
604 wrpr %o1, PSTATE_MG, %pstate
605 stx %g0, [%o0 + 0x80]
606 stx %g1, [%o0 + 0x88]
607 stx %g2, [%o0 + 0x90]
608 stx %g3, [%o0 + 0x98]
609 stx %g4, [%o0 + 0xa0]
610 stx %g5, [%o0 + 0xa8]
611 stx %g6, [%o0 + 0xb0]
612 stx %g7, [%o0 + 0xb8]
613 wrpr %o5, 0x0, %pstate
617 .globl restore_alternate_globals
618 restore_alternate_globals: /* %o0 = save_area */
620 andn %o5, PSTATE_IE, %o1
621 wrpr %o1, PSTATE_AG, %pstate
622 ldx [%o0 + 0x00], %g0
623 ldx [%o0 + 0x08], %g1
624 ldx [%o0 + 0x10], %g2
625 ldx [%o0 + 0x18], %g3
626 ldx [%o0 + 0x20], %g4
627 ldx [%o0 + 0x28], %g5
628 ldx [%o0 + 0x30], %g6
629 ldx [%o0 + 0x38], %g7
630 wrpr %o1, PSTATE_IG, %pstate
631 ldx [%o0 + 0x40], %g0
632 ldx [%o0 + 0x48], %g1
633 ldx [%o0 + 0x50], %g2
634 ldx [%o0 + 0x58], %g3
635 ldx [%o0 + 0x60], %g4
636 ldx [%o0 + 0x68], %g5
637 ldx [%o0 + 0x70], %g6
638 ldx [%o0 + 0x78], %g7
639 wrpr %o1, PSTATE_MG, %pstate
640 ldx [%o0 + 0x80], %g0
641 ldx [%o0 + 0x88], %g1
642 ldx [%o0 + 0x90], %g2
643 ldx [%o0 + 0x98], %g3
644 ldx [%o0 + 0xa0], %g4
645 ldx [%o0 + 0xa8], %g5
646 ldx [%o0 + 0xb0], %g6
647 ldx [%o0 + 0xb8], %g7
648 wrpr %o5, 0x0, %pstate
654 ldx [%o0 + PT_V9_TSTATE], %o1
658 stx %o1, [%o0 + PT_V9_G1]
660 ldx [%o0 + PT_V9_TSTATE], %o1
661 ldx [%o0 + PT_V9_G1], %o2
662 or %g0, %ulo(TSTATE_ICC), %o3
669 stx %o1, [%o0 + PT_V9_TSTATE]
671 .globl utrap, utrap_ill
672 utrap: brz,pn %g1, etrap
677 andn %l6, TSTATE_CWP, %l6
678 wrpr %l6, %l7, %tstate
685 add %sp, PTREGS_OFF, %o0
689 /* XXX Here is stuff we still need to write... -DaveM XXX */
690 .globl netbsd_syscall
695 /* These next few routines must be sure to clear the
696 * SFSR FaultValid bit so that the fast tlb data protection
697 * handler does not flush the wrong context and lock up the
700 .globl __do_data_access_exception
701 .globl __do_data_access_exception_tl1
702 __do_data_access_exception_tl1:
704 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
707 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
708 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
709 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
711 ba,pt %xcc, winfix_dax
713 __do_data_access_exception:
715 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
718 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
719 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
720 stxa %g0, [%g3] ASI_DMMU ! Clear SFSR.FaultValid bit
724 109: or %g7, %lo(109b), %g7
727 call data_access_exception
728 add %sp, PTREGS_OFF, %o0
732 .globl __do_instruction_access_exception
733 .globl __do_instruction_access_exception_tl1
734 __do_instruction_access_exception_tl1:
736 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
739 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
740 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
741 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
745 109: or %g7, %lo(109b), %g7
748 call instruction_access_exception_tl1
749 add %sp, PTREGS_OFF, %o0
753 __do_instruction_access_exception:
755 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
758 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
759 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
760 stxa %g0, [%g3] ASI_IMMU ! Clear FaultValid bit
764 109: or %g7, %lo(109b), %g7
767 call instruction_access_exception
768 add %sp, PTREGS_OFF, %o0
772 /* This is the trap handler entry point for ECC correctable
773 * errors. They are corrected, but we listen for the trap
774 * so that the event can be logged.
776 * Disrupting errors are either:
777 * 1) single-bit ECC errors during UDB reads to system
779 * 2) data parity errors during write-back events
781 * As far as I can make out from the manual, the CEE trap
782 * is only for correctable errors during memory read
783 * accesses by the front-end of the processor.
785 * The code below is only for trap level 1 CEE events,
786 * as it is the only situation where we can safely record
787 * and log. For trap level >1 we just clear the CE bit
788 * in the AFSR and return.
791 /* Our trap handling infrastructure allows us to preserve
792 * two 64-bit values during etrap for arguments to
793 * subsequent C code. Therefore we encode the information
796 * value 1) Full 64-bits of AFAR
797 * value 2) Low 33-bits of AFSR, then bits 33-->42
798 * are UDBL error status and bits 43-->52
799 * are UDBH error status
804 ldxa [%g0] ASI_AFSR, %g1 ! Read AFSR
805 ldxa [%g0] ASI_AFAR, %g2 ! Read AFAR
806 sllx %g1, 31, %g1 ! Clear reserved bits
807 srlx %g1, 31, %g1 ! in AFSR
809 /* NOTE: UltraSparc-I/II have high and low UDB error
810 * registers, corresponding to the two UDB units
811 * present on those chips. UltraSparc-IIi only
812 * has a single UDB, called "SDB" in the manual.
813 * For IIi the upper UDB register always reads
814 * as zero so for our purposes things will just
815 * work with the checks below.
817 ldxa [%g0] ASI_UDBL_ERROR_R, %g3 ! Read UDB-Low error status
818 andcc %g3, (1 << 8), %g4 ! Check CE bit
819 sllx %g3, (64 - 10), %g3 ! Clear reserved bits
820 srlx %g3, (64 - 10), %g3 ! in UDB-Low error status
822 sllx %g3, (33 + 0), %g3 ! Shift up to encoding area
823 or %g1, %g3, %g1 ! Or it in
824 be,pn %xcc, 1f ! Branch if CE bit was clear
826 stxa %g4, [%g0] ASI_UDB_ERROR_W ! Clear CE sticky bit in UDBL
827 membar #Sync ! Synchronize ASI stores
828 1: mov 0x18, %g5 ! Addr of UDB-High error status
829 ldxa [%g5] ASI_UDBH_ERROR_R, %g3 ! Read it
831 andcc %g3, (1 << 8), %g4 ! Check CE bit
832 sllx %g3, (64 - 10), %g3 ! Clear reserved bits
833 srlx %g3, (64 - 10), %g3 ! in UDB-High error status
834 sllx %g3, (33 + 10), %g3 ! Shift up to encoding area
835 or %g1, %g3, %g1 ! Or it in
836 be,pn %xcc, 1f ! Branch if CE bit was clear
840 stxa %g4, [%g5] ASI_UDB_ERROR_W ! Clear CE sticky bit in UDBH
841 membar #Sync ! Synchronize ASI stores
842 1: mov 1, %g5 ! AFSR CE bit is
843 sllx %g5, 20, %g5 ! bit 20
844 stxa %g5, [%g0] ASI_AFSR ! Clear CE sticky bit in AFSR
845 membar #Sync ! Synchronize ASI stores
846 sllx %g2, (64 - 41), %g2 ! Clear reserved bits
847 srlx %g2, (64 - 41), %g2 ! in latched AFAR
849 andn %g2, 0x0f, %g2 ! Finish resv bit clearing
850 mov %g1, %g4 ! Move AFSR+UDB* into save reg
851 mov %g2, %g5 ! Move AFAR into save reg
854 ba,pt %xcc, etrap_irq
860 add %sp, PTREGS_OFF, %o2
861 ba,a,pt %xcc, rtrap_irq
863 /* Capture I/D/E-cache state into per-cpu error scoreboard.
865 * %g1: (TL>=0) ? 1 : 0
870 * %g6: current thread ptr
873 #define CHEETAH_LOG_ERROR \
874 /* Put "TL1" software bit into AFSR. */ \
878 /* Get log entry pointer for this cpu at this trap level. */ \
879 BRANCH_IF_JALAPENO(g2,g3,50f) \
880 ldxa [%g0] ASI_SAFARI_CONFIG, %g2; \
883 and %g2, 0x3ff, %g2; \
884 50: ldxa [%g0] ASI_JBUS_CONFIG, %g2; \
886 and %g2, 0x1f, %g2; \
887 60: sllx %g2, 9, %g2; \
888 sethi %hi(cheetah_error_log), %g3; \
889 ldx [%g3 + %lo(cheetah_error_log)], %g3; \
895 /* %g1 holds pointer to the top of the logging scoreboard */ \
896 ldx [%g1 + 0x0], %g7; \
900 stx %g4, [%g1 + 0x0]; \
901 stx %g5, [%g1 + 0x8]; \
902 add %g1, 0x10, %g1; \
903 /* %g1 now points to D-cache logging area */ \
904 set 0x3ff8, %g2; /* DC_addr mask */ \
905 and %g5, %g2, %g2; /* DC_addr bits of AFAR */ \
907 or %g3, 1, %g3; /* PHYS tag + valid */ \
908 10: ldxa [%g2] ASI_DCACHE_TAG, %g7; \
909 cmp %g3, %g7; /* TAG match? */ \
912 /* Yep, what we want, capture state. */ \
913 stx %g2, [%g1 + 0x20]; \
914 stx %g7, [%g1 + 0x28]; \
915 /* A membar Sync is required before and after utag access. */ \
917 ldxa [%g2] ASI_DCACHE_UTAG, %g7; \
919 stx %g7, [%g1 + 0x30]; \
920 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7; \
921 stx %g7, [%g1 + 0x38]; \
923 12: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7; \
925 add %g3, (1 << 5), %g3; \
930 add %g1, 0x20, %g1; \
931 13: sethi %hi(1 << 14), %g7; \
937 add %g1, 0x40, %g1; \
938 20: /* %g1 now points to I-cache logging area */ \
939 set 0x1fe0, %g2; /* IC_addr mask */ \
940 and %g5, %g2, %g2; /* IC_addr bits of AFAR */ \
941 sllx %g2, 1, %g2; /* IC_addr[13:6]==VA[12:5] */ \
942 srlx %g5, (13 - 8), %g3; /* Make PTAG */ \
943 andn %g3, 0xff, %g3; /* Mask off undefined bits */ \
944 21: ldxa [%g2] ASI_IC_TAG, %g7; \
945 andn %g7, 0xff, %g7; \
949 /* Yep, what we want, capture state. */ \
950 stx %g2, [%g1 + 0x40]; \
951 stx %g7, [%g1 + 0x48]; \
952 add %g2, (1 << 3), %g2; \
953 ldxa [%g2] ASI_IC_TAG, %g7; \
954 add %g2, (1 << 3), %g2; \
955 stx %g7, [%g1 + 0x50]; \
956 ldxa [%g2] ASI_IC_TAG, %g7; \
957 add %g2, (1 << 3), %g2; \
958 stx %g7, [%g1 + 0x60]; \
959 ldxa [%g2] ASI_IC_TAG, %g7; \
960 stx %g7, [%g1 + 0x68]; \
961 sub %g2, (3 << 3), %g2; \
962 ldxa [%g2] ASI_IC_STAG, %g7; \
963 stx %g7, [%g1 + 0x58]; \
966 22: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7; \
968 add %g3, (1 << 3), %g3; \
973 add %g1, 0x30, %g1; \
974 23: sethi %hi(1 << 14), %g7; \
980 add %g1, 0x70, %g1; \
981 30: /* %g1 now points to E-cache logging area */ \
982 andn %g5, (32 - 1), %g2; /* E-cache subblock */ \
983 stx %g2, [%g1 + 0x20]; \
984 ldxa [%g2] ASI_EC_TAG_DATA, %g7; \
985 stx %g7, [%g1 + 0x28]; \
986 ldxa [%g2] ASI_EC_R, %g0; \
988 31: ldxa [%g3] ASI_EC_DATA, %g7; \
989 stx %g7, [%g1 + %g3]; \
996 /* These get patched into the trap table at boot time
997 * once we know we have a cheetah processor.
999 .globl cheetah_fecc_trap_vector, cheetah_fecc_trap_vector_tl1
1000 cheetah_fecc_trap_vector:
1002 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1003 andn %g1, DCU_DC | DCU_IC, %g1
1004 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1006 sethi %hi(cheetah_fast_ecc), %g2
1007 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
1009 cheetah_fecc_trap_vector_tl1:
1011 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1012 andn %g1, DCU_DC | DCU_IC, %g1
1013 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1015 sethi %hi(cheetah_fast_ecc), %g2
1016 jmpl %g2 + %lo(cheetah_fast_ecc), %g0
1018 .globl cheetah_cee_trap_vector, cheetah_cee_trap_vector_tl1
1019 cheetah_cee_trap_vector:
1021 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1022 andn %g1, DCU_IC, %g1
1023 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1025 sethi %hi(cheetah_cee), %g2
1026 jmpl %g2 + %lo(cheetah_cee), %g0
1028 cheetah_cee_trap_vector_tl1:
1030 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1031 andn %g1, DCU_IC, %g1
1032 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1034 sethi %hi(cheetah_cee), %g2
1035 jmpl %g2 + %lo(cheetah_cee), %g0
1037 .globl cheetah_deferred_trap_vector, cheetah_deferred_trap_vector_tl1
1038 cheetah_deferred_trap_vector:
1040 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
1041 andn %g1, DCU_DC | DCU_IC, %g1;
1042 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
1044 sethi %hi(cheetah_deferred_trap), %g2
1045 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
1047 cheetah_deferred_trap_vector_tl1:
1049 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1;
1050 andn %g1, DCU_DC | DCU_IC, %g1;
1051 stxa %g1, [%g0] ASI_DCU_CONTROL_REG;
1053 sethi %hi(cheetah_deferred_trap), %g2
1054 jmpl %g2 + %lo(cheetah_deferred_trap), %g0
1057 /* Cheetah+ specific traps. These are for the new I/D cache parity
1058 * error traps. The first argument to cheetah_plus_parity_handler
1059 * is encoded as follows:
1061 * Bit0: 0=dcache,1=icache
1062 * Bit1: 0=recoverable,1=unrecoverable
1064 .globl cheetah_plus_dcpe_trap_vector, cheetah_plus_dcpe_trap_vector_tl1
1065 cheetah_plus_dcpe_trap_vector:
1067 sethi %hi(do_cheetah_plus_data_parity), %g7
1068 jmpl %g7 + %lo(do_cheetah_plus_data_parity), %g0
1075 do_cheetah_plus_data_parity:
1079 call cheetah_plus_parity_error
1080 add %sp, PTREGS_OFF, %o1
1084 cheetah_plus_dcpe_trap_vector_tl1:
1086 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
1087 sethi %hi(do_dcpe_tl1), %g3
1088 jmpl %g3 + %lo(do_dcpe_tl1), %g0
1094 .globl cheetah_plus_icpe_trap_vector, cheetah_plus_icpe_trap_vector_tl1
1095 cheetah_plus_icpe_trap_vector:
1097 sethi %hi(do_cheetah_plus_insn_parity), %g7
1098 jmpl %g7 + %lo(do_cheetah_plus_insn_parity), %g0
1105 do_cheetah_plus_insn_parity:
1109 call cheetah_plus_parity_error
1110 add %sp, PTREGS_OFF, %o1
1114 cheetah_plus_icpe_trap_vector_tl1:
1116 wrpr PSTATE_IG | PSTATE_PEF | PSTATE_PRIV, %pstate
1117 sethi %hi(do_icpe_tl1), %g3
1118 jmpl %g3 + %lo(do_icpe_tl1), %g0
1124 /* If we take one of these traps when tl >= 1, then we
1125 * jump to interrupt globals. If some trap level above us
1126 * was also using interrupt globals, we cannot recover.
1127 * We may use all interrupt global registers except %g6.
1129 .globl do_dcpe_tl1, do_icpe_tl1
1131 rdpr %tl, %g1 ! Save original trap level
1132 mov 1, %g2 ! Setup TSTATE checking loop
1133 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
1134 1: wrpr %g2, %tl ! Set trap level to check
1135 rdpr %tstate, %g4 ! Read TSTATE for this level
1136 andcc %g4, %g3, %g0 ! Interrupt globals in use?
1137 bne,a,pn %xcc, do_dcpe_tl1_fatal ! Yep, irrecoverable
1138 wrpr %g1, %tl ! Restore original trap level
1139 add %g2, 1, %g2 ! Next trap level
1140 cmp %g2, %g1 ! Hit them all yet?
1141 ble,pt %icc, 1b ! Not yet
1143 wrpr %g1, %tl ! Restore original trap level
1144 do_dcpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
1145 /* Reset D-cache parity */
1146 sethi %hi(1 << 16), %g1 ! D-cache size
1147 mov (1 << 5), %g2 ! D-cache line size
1148 sub %g1, %g2, %g1 ! Move down 1 cacheline
1149 1: srl %g1, 14, %g3 ! Compute UTAG
1151 stxa %g3, [%g1] ASI_DCACHE_UTAG
1153 sub %g2, 8, %g3 ! 64-bit data word within line
1155 stxa %g0, [%g1 + %g3] ASI_DCACHE_DATA
1157 subcc %g3, 8, %g3 ! Next 64-bit data word
1160 subcc %g1, %g2, %g1 ! Next cacheline
1163 ba,pt %xcc, dcpe_icpe_tl1_common
1168 ba,pt %xcc, etraptl1
1169 1: or %g7, %lo(1b), %g7
1171 call cheetah_plus_parity_error
1172 add %sp, PTREGS_OFF, %o1
1177 rdpr %tl, %g1 ! Save original trap level
1178 mov 1, %g2 ! Setup TSTATE checking loop
1179 sethi %hi(TSTATE_IG), %g3 ! TSTATE mask bit
1180 1: wrpr %g2, %tl ! Set trap level to check
1181 rdpr %tstate, %g4 ! Read TSTATE for this level
1182 andcc %g4, %g3, %g0 ! Interrupt globals in use?
1183 bne,a,pn %xcc, do_icpe_tl1_fatal ! Yep, irrecoverable
1184 wrpr %g1, %tl ! Restore original trap level
1185 add %g2, 1, %g2 ! Next trap level
1186 cmp %g2, %g1 ! Hit them all yet?
1187 ble,pt %icc, 1b ! Not yet
1189 wrpr %g1, %tl ! Restore original trap level
1190 do_icpe_tl1_nonfatal: /* Ok we may use interrupt globals safely. */
1192 sethi %hi(1 << 15), %g1 ! I-cache size
1193 mov (1 << 5), %g2 ! I-cache line size
1195 1: or %g1, (2 << 3), %g3
1196 stxa %g0, [%g3] ASI_IC_TAG
1201 ba,pt %xcc, dcpe_icpe_tl1_common
1206 ba,pt %xcc, etraptl1
1207 1: or %g7, %lo(1b), %g7
1209 call cheetah_plus_parity_error
1210 add %sp, PTREGS_OFF, %o1
1214 dcpe_icpe_tl1_common:
1215 /* Flush D-cache, re-enable D/I caches in DCU and finally
1216 * retry the trapping instruction.
1218 sethi %hi(1 << 16), %g1 ! D-cache size
1219 mov (1 << 5), %g2 ! D-cache line size
1221 1: stxa %g0, [%g1] ASI_DCACHE_TAG
1226 ldxa [%g0] ASI_DCU_CONTROL_REG, %g1
1227 or %g1, (DCU_DC | DCU_IC), %g1
1228 stxa %g1, [%g0] ASI_DCU_CONTROL_REG
1232 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1233 * in the trap table. That code has done a memory barrier
1234 * and has disabled both the I-cache and D-cache in the DCU
1235 * control register. The I-cache is disabled so that we may
1236 * capture the corrupted cache line, and the D-cache is disabled
1237 * because corrupt data may have been placed there and we don't
1238 * want to reference it.
1240 * %g1 is one if this trap occurred at %tl >= 1.
1242 * Next, we turn off error reporting so that we don't recurse.
1244 .globl cheetah_fast_ecc
1246 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1247 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1248 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1251 /* Fetch and clear AFSR/AFAR */
1252 ldxa [%g0] ASI_AFSR, %g4
1253 ldxa [%g0] ASI_AFAR, %g5
1254 stxa %g4, [%g0] ASI_AFSR
1261 ba,pt %xcc, etrap_irq
1265 call cheetah_fecc_handler
1266 add %sp, PTREGS_OFF, %o0
1267 ba,a,pt %xcc, rtrap_irq
1269 /* Our caller has disabled I-cache and performed membar Sync. */
1272 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1273 andn %g2, ESTATE_ERROR_CEEN, %g2
1274 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1277 /* Fetch and clear AFSR/AFAR */
1278 ldxa [%g0] ASI_AFSR, %g4
1279 ldxa [%g0] ASI_AFAR, %g5
1280 stxa %g4, [%g0] ASI_AFSR
1287 ba,pt %xcc, etrap_irq
1291 call cheetah_cee_handler
1292 add %sp, PTREGS_OFF, %o0
1293 ba,a,pt %xcc, rtrap_irq
1295 /* Our caller has disabled I-cache+D-cache and performed membar Sync. */
1296 .globl cheetah_deferred_trap
1297 cheetah_deferred_trap:
1298 ldxa [%g0] ASI_ESTATE_ERROR_EN, %g2
1299 andn %g2, ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN, %g2
1300 stxa %g2, [%g0] ASI_ESTATE_ERROR_EN
1303 /* Fetch and clear AFSR/AFAR */
1304 ldxa [%g0] ASI_AFSR, %g4
1305 ldxa [%g0] ASI_AFAR, %g5
1306 stxa %g4, [%g0] ASI_AFSR
1313 ba,pt %xcc, etrap_irq
1317 call cheetah_deferred_handler
1318 add %sp, PTREGS_OFF, %o0
1319 ba,a,pt %xcc, rtrap_irq
1324 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1326 sethi %hi(109f), %g7
1328 109: or %g7, %lo(109b), %g7
1330 add %sp, PTREGS_OFF, %o0
1339 /* Setup %g4/%g5 now as they are used in the
1344 ldxa [%g4] ASI_DMMU, %g4
1345 ldxa [%g3] ASI_DMMU, %g5
1346 stxa %g0, [%g3] ASI_DMMU ! Clear FaultValid bit
1348 bgu,pn %icc, winfix_mna
1351 1: sethi %hi(109f), %g7
1353 109: or %g7, %lo(109b), %g7
1356 call mem_address_unaligned
1357 add %sp, PTREGS_OFF, %o0
1363 sethi %hi(109f), %g7
1365 ldxa [%g4] ASI_DMMU, %g5
1366 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1369 ldxa [%g4] ASI_DMMU, %g4
1371 109: or %g7, %lo(109b), %g7
1375 add %sp, PTREGS_OFF, %o0
1381 sethi %hi(109f), %g7
1383 ldxa [%g4] ASI_DMMU, %g5
1384 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
1387 ldxa [%g4] ASI_DMMU, %g4
1389 109: or %g7, %lo(109b), %g7
1393 add %sp, PTREGS_OFF, %o0
1397 .globl breakpoint_trap
1399 call sparc_breakpoint
1400 add %sp, PTREGS_OFF, %o0
1404 #if defined(CONFIG_SUNOS_EMUL) || defined(CONFIG_SOLARIS_EMUL) || \
1405 defined(CONFIG_SOLARIS_EMUL_MODULE)
1406 /* SunOS uses syscall zero as the 'indirect syscall' it looks
1407 * like indir_syscall(scall_num, arg0, arg1, arg2...); etc.
1408 * This is complete brain damage.
1414 cmp %o0, NR_SYSCALLS
1417 sethi %hi(sunos_nosys), %l6
1419 or %l6, %lo(sunos_nosys), %l6
1420 1: sethi %hi(sunos_sys_table), %l7
1421 or %l7, %lo(sunos_sys_table), %l7
1422 lduw [%l7 + %o0], %l6
1436 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1437 b,pt %xcc, ret_sys_call
1438 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1440 /* SunOS getuid() returns uid in %o0 and euid in %o1 */
1443 call sys32_geteuid16
1446 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1447 b,pt %xcc, ret_sys_call
1448 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1450 /* SunOS getgid() returns gid in %o0 and egid in %o1 */
1453 call sys32_getegid16
1456 stx %o0, [%sp + PTREGS_OFF + PT_V9_I1]
1457 b,pt %xcc, ret_sys_call
1458 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1461 /* SunOS's execv() call only specifies the argv argument, the
1462 * environment settings are the same as the calling processes.
1466 sethi %hi(sparc_execve), %g1
1467 ba,pt %xcc, execve_merge
1468 or %g1, %lo(sparc_execve), %g1
1469 #ifdef CONFIG_COMPAT
1472 stx %g0, [%sp + PTREGS_OFF + PT_V9_I2]
1475 sethi %hi(sparc32_execve), %g1
1476 or %g1, %lo(sparc32_execve), %g1
1481 add %sp, PTREGS_OFF, %o0
1483 .globl sys_pipe, sys_sigpause, sys_nis_syscall
1484 .globl sys_sigsuspend, sys_rt_sigsuspend
1485 .globl sys_rt_sigreturn
1487 .globl sys_sigaltstack
1489 sys_pipe: ba,pt %xcc, sparc_pipe
1490 add %sp, PTREGS_OFF, %o0
1491 sys_nis_syscall:ba,pt %xcc, c_sys_nis_syscall
1492 add %sp, PTREGS_OFF, %o0
1493 sys_memory_ordering:
1494 ba,pt %xcc, sparc_memory_ordering
1495 add %sp, PTREGS_OFF, %o1
1496 sys_sigaltstack:ba,pt %xcc, do_sigaltstack
1497 add %i6, STACK_BIAS, %o2
1498 #ifdef CONFIG_COMPAT
1499 .globl sys32_sigstack
1500 sys32_sigstack: ba,pt %xcc, do_sys32_sigstack
1502 .globl sys32_sigaltstack
1504 ba,pt %xcc, do_sys32_sigaltstack
1508 sys_sigsuspend: add %sp, PTREGS_OFF, %o0
1510 add %o7, 1f-.-4, %o7
1512 sys_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1513 add %sp, PTREGS_OFF, %o2
1514 call do_rt_sigsuspend
1515 add %o7, 1f-.-4, %o7
1517 #ifdef CONFIG_COMPAT
1518 .globl sys32_rt_sigsuspend
1519 sys32_rt_sigsuspend: /* NOTE: %o0,%o1 have a correct value already */
1521 add %sp, PTREGS_OFF, %o2
1522 call do_rt_sigsuspend32
1523 add %o7, 1f-.-4, %o7
1525 /* NOTE: %o0 has a correct value already */
1526 sys_sigpause: add %sp, PTREGS_OFF, %o1
1528 add %o7, 1f-.-4, %o7
1530 #ifdef CONFIG_COMPAT
1531 .globl sys32_sigreturn
1533 add %sp, PTREGS_OFF, %o0
1535 add %o7, 1f-.-4, %o7
1539 add %sp, PTREGS_OFF, %o0
1540 call do_rt_sigreturn
1541 add %o7, 1f-.-4, %o7
1543 #ifdef CONFIG_COMPAT
1544 .globl sys32_rt_sigreturn
1546 add %sp, PTREGS_OFF, %o0
1547 call do_rt_sigreturn32
1548 add %o7, 1f-.-4, %o7
1551 sys_ptrace: add %sp, PTREGS_OFF, %o0
1553 add %o7, 1f-.-4, %o7
1556 1: ldx [%curptr + TI_FLAGS], %l5
1557 andcc %l5, _TIF_SYSCALL_TRACE, %g0
1566 /* This is how fork() was meant to be done, 8 instruction entry.
1568 * I questioned the following code briefly, let me clear things
1569 * up so you must not reason on it like I did.
1571 * Know the fork_kpsr etc. we use in the sparc32 port? We don't
1572 * need it here because the only piece of window state we copy to
1573 * the child is the CWP register. Even if the parent sleeps,
1574 * we are safe because we stuck it into pt_regs of the parent
1575 * so it will not change.
1577 * XXX This raises the question, whether we can do the same on
1578 * XXX sparc32 to get rid of fork_kpsr _and_ fork_kwim. The
1579 * XXX answer is yes. We stick fork_kpsr in UREG_G0 and
1580 * XXX fork_kwim in UREG_G1 (global registers are considered
1581 * XXX volatile across a system call in the sparc ABI I think
1582 * XXX if it isn't we can use regs->y instead, anyone who depends
1583 * XXX upon the Y register being preserved across a fork deserves
1586 * In fact we should take advantage of that fact for other things
1587 * during system calls...
1589 .globl sys_fork, sys_vfork, sys_clone, sparc_exit
1590 .globl ret_from_syscall
1592 sys_vfork: /* Under Linux, vfork and fork are just special cases of clone. */
1593 sethi %hi(0x4000 | 0x0100 | SIGCHLD), %o0
1594 or %o0, %lo(0x4000 | 0x0100 | SIGCHLD), %o0
1595 ba,pt %xcc, sys_clone
1601 ba,pt %xcc, sparc_do_fork
1602 add %sp, PTREGS_OFF, %o2
1604 /* Clear SPARC_FLAG_NEWCHILD, switch_to leaves thread.flags in
1605 * %o7 for us. Check performance counter stuff too.
1607 andn %o7, _TIF_NEWCHILD, %l0
1608 stx %l0, [%g6 + TI_FLAGS]
1611 andcc %l0, _TIF_PERFCTR, %g0
1614 ldx [%g6 + TI_PCR], %o7
1617 /* Blackbird errata workaround. See commentary in
1618 * smp.c:smp_percpu_timer_interrupt() for more
1624 99: wr %g0, %g0, %pic
1627 1: b,pt %xcc, ret_sys_call
1628 ldx [%sp + PTREGS_OFF + PT_V9_I0], %o0
1629 sparc_exit: wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV), %pstate
1633 wrpr %g3, 0x0, %cansave
1634 wrpr %g0, 0x0, %otherwin
1635 wrpr %g0, (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE), %pstate
1636 ba,pt %xcc, sys_exit
1637 stb %g0, [%g6 + TI_WSAVED]
1639 linux_sparc_ni_syscall:
1640 sethi %hi(sys_ni_syscall), %l7
1642 or %l7, %lo(sys_ni_syscall), %l7
1644 linux_syscall_trace32:
1654 linux_syscall_trace:
1665 /* Linux 32-bit and SunOS system calls enter here... */
1667 .globl linux_sparc_syscall32
1668 linux_sparc_syscall32:
1669 /* Direct access to user regs, much faster. */
1670 cmp %g1, NR_SYSCALLS ! IEU1 Group
1671 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1672 srl %i0, 0, %o0 ! IEU0
1673 sll %g1, 2, %l4 ! IEU0 Group
1674 #ifdef SYSCALL_TRACING
1675 call syscall_trace_entry
1676 add %sp, PTREGS_OFF, %o0
1679 srl %i4, 0, %o4 ! IEU1
1680 lduw [%l7 + %l4], %l7 ! Load
1681 srl %i1, 0, %o1 ! IEU0 Group
1682 ldx [%curptr + TI_FLAGS], %l0 ! Load
1684 srl %i5, 0, %o5 ! IEU1
1685 srl %i2, 0, %o2 ! IEU0 Group
1686 andcc %l0, _TIF_SYSCALL_TRACE, %g0 ! IEU0 Group
1687 bne,pn %icc, linux_syscall_trace32 ! CTI
1689 call %l7 ! CTI Group brk forced
1690 srl %i3, 0, %o3 ! IEU0
1693 /* Linux native and SunOS system calls enter here... */
1695 .globl linux_sparc_syscall, ret_sys_call
1696 linux_sparc_syscall:
1697 /* Direct access to user regs, much faster. */
1698 cmp %g1, NR_SYSCALLS ! IEU1 Group
1699 bgeu,pn %xcc, linux_sparc_ni_syscall ! CTI
1701 sll %g1, 2, %l4 ! IEU0 Group
1702 #ifdef SYSCALL_TRACING
1703 call syscall_trace_entry
1704 add %sp, PTREGS_OFF, %o0
1708 lduw [%l7 + %l4], %l7 ! Load
1709 4: mov %i2, %o2 ! IEU0 Group
1710 ldx [%curptr + TI_FLAGS], %l0 ! Load
1713 mov %i4, %o4 ! IEU0 Group
1714 andcc %l0, _TIF_SYSCALL_TRACE, %g0 ! IEU1 Group+1 bubble
1715 bne,pn %icc, linux_syscall_trace ! CTI Group
1717 2: call %l7 ! CTI Group brk forced
1721 3: stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1723 #ifdef SYSCALL_TRACING
1725 call syscall_trace_exit
1726 add %sp, PTREGS_OFF, %o0
1729 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %g3
1730 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %l1 ! pc = npc
1732 mov %ulo(TSTATE_XCARRY | TSTATE_ICARRY), %g2
1735 /* Check if force_successful_syscall_return()
1738 ldx [%curptr + TI_FLAGS], %l0
1739 andcc %l0, _TIF_SYSCALL_SUCCESS, %g0
1741 andn %l0, _TIF_SYSCALL_SUCCESS, %l0
1743 stx %l0, [%curptr + TI_FLAGS]
1746 cmp %o0, -ERESTART_RESTARTBLOCK
1748 andcc %l0, _TIF_SYSCALL_TRACE, %l6
1750 /* System call success, clear Carry condition code. */
1752 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1753 bne,pn %icc, linux_syscall_trace2
1754 add %l1, 0x4, %l2 ! npc = npc+4
1755 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1756 ba,pt %xcc, rtrap_clr_l6
1757 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1760 /* System call failure, set Carry condition code.
1761 * Also, get abs(errno) to return to the process.
1763 andcc %l0, _TIF_SYSCALL_TRACE, %l6
1766 stx %o0, [%sp + PTREGS_OFF + PT_V9_I0]
1768 stx %g3, [%sp + PTREGS_OFF + PT_V9_TSTATE]
1769 bne,pn %icc, linux_syscall_trace2
1770 add %l1, 0x4, %l2 ! npc = npc+4
1771 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1774 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1775 linux_syscall_trace2:
1778 stx %l1, [%sp + PTREGS_OFF + PT_V9_TPC]
1780 stx %l2, [%sp + PTREGS_OFF + PT_V9_TNPC]
1783 .globl __flushw_user
1788 1: save %sp, -128, %sp
1794 restore %g0, %g0, %g0