1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/smp_lock.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
20 #include <linux/seq_file.h>
21 #include <linux/cache.h>
22 #include <linux/jiffies.h>
23 #include <linux/profile.h>
24 #include <linux/bootmem.h>
27 #include <asm/ptrace.h>
28 #include <asm/atomic.h>
29 #include <asm/tlbflush.h>
30 #include <asm/mmu_context.h>
31 #include <asm/cpudata.h>
35 #include <asm/pgtable.h>
36 #include <asm/oplib.h>
37 #include <asm/uaccess.h>
38 #include <asm/timer.h>
39 #include <asm/starfire.h>
41 #include <asm/sections.h>
43 extern void calibrate_delay(void);
45 /* Please don't make this stuff initdata!!! --DaveM */
46 static unsigned char boot_cpu_id;
48 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
49 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
50 static cpumask_t smp_commenced_mask;
51 static cpumask_t cpu_callout_map;
53 void smp_info(struct seq_file *m)
57 seq_printf(m, "State:\n");
58 for (i = 0; i < NR_CPUS; i++) {
61 "CPU%d:\t\tonline\n", i);
65 void smp_bogo(struct seq_file *m)
69 for (i = 0; i < NR_CPUS; i++)
72 "Cpu%dBogo\t: %lu.%02lu\n"
73 "Cpu%dClkTck\t: %016lx\n",
74 i, cpu_data(i).udelay_val / (500000/HZ),
75 (cpu_data(i).udelay_val / (5000/HZ)) % 100,
76 i, cpu_data(i).clock_tick);
79 void __init smp_store_cpu_info(int id)
83 /* multiplier and counter set by
84 smp_setup_percpu_timer() */
85 cpu_data(id).udelay_val = loops_per_jiffy;
87 cpu_find_by_mid(id, &cpu_node);
88 cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
89 "clock-frequency", 0);
91 cpu_data(id).idle_volume = 1;
93 cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
95 cpu_data(id).dcache_line_size =
96 prom_getintdefault(cpu_node, "dcache-line-size", 32);
97 cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
99 cpu_data(id).icache_line_size =
100 prom_getintdefault(cpu_node, "icache-line-size", 32);
101 cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
103 cpu_data(id).ecache_line_size =
104 prom_getintdefault(cpu_node, "ecache-line-size", 64);
105 printk("CPU[%d]: Caches "
106 "D[sz(%d):line_sz(%d)] "
107 "I[sz(%d):line_sz(%d)] "
108 "E[sz(%d):line_sz(%d)]\n",
110 cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
111 cpu_data(id).icache_size, cpu_data(id).icache_line_size,
112 cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
115 static void smp_setup_percpu_timer(void);
117 static volatile unsigned long callin_flag = 0;
119 void __init smp_callin(void)
121 int cpuid = hard_smp_processor_id();
123 __local_per_cpu_offset = __per_cpu_offset(cpuid);
125 if (tlb_type == hypervisor)
126 sun4v_ktsb_register();
130 smp_setup_percpu_timer();
132 if (cheetah_pcache_forced_on)
133 cheetah_enable_pcache();
138 smp_store_cpu_info(cpuid);
140 __asm__ __volatile__("membar #Sync\n\t"
141 "flush %%g6" : : : "memory");
143 /* Clear this or we will die instantly when we
144 * schedule back to this idler...
146 current_thread_info()->new_child = 0;
148 /* Attach to the address space of init_task. */
149 atomic_inc(&init_mm.mm_count);
150 current->active_mm = &init_mm;
152 while (!cpu_isset(cpuid, smp_commenced_mask))
155 cpu_set(cpuid, cpu_online_map);
157 /* idle thread is expected to have preempt disabled */
163 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
164 panic("SMP bolixed\n");
167 static unsigned long current_tick_offset __read_mostly;
169 /* This tick register synchronization scheme is taken entirely from
170 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
172 * The only change I've made is to rework it so that the master
173 * initiates the synchonization instead of the slave. -DaveM
177 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
179 #define NUM_ROUNDS 64 /* magic value */
180 #define NUM_ITERS 5 /* likewise */
182 static DEFINE_SPINLOCK(itc_sync_lock);
183 static unsigned long go[SLAVE + 1];
185 #define DEBUG_TICK_SYNC 0
187 static inline long get_delta (long *rt, long *master)
189 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
190 unsigned long tcenter, t0, t1, tm;
193 for (i = 0; i < NUM_ITERS; i++) {
194 t0 = tick_ops->get_tick();
197 while (!(tm = go[SLAVE]))
201 t1 = tick_ops->get_tick();
203 if (t1 - t0 < best_t1 - best_t0)
204 best_t0 = t0, best_t1 = t1, best_tm = tm;
207 *rt = best_t1 - best_t0;
208 *master = best_tm - best_t0;
210 /* average best_t0 and best_t1 without overflow: */
211 tcenter = (best_t0/2 + best_t1/2);
212 if (best_t0 % 2 + best_t1 % 2 == 2)
214 return tcenter - best_tm;
217 void smp_synchronize_tick_client(void)
219 long i, delta, adj, adjust_latency = 0, done = 0;
220 unsigned long flags, rt, master_time_stamp, bound;
223 long rt; /* roundtrip time */
224 long master; /* master's timestamp */
225 long diff; /* difference between midpoint and master's timestamp */
226 long lat; /* estimate of itc adjustment latency */
235 local_irq_save(flags);
237 for (i = 0; i < NUM_ROUNDS; i++) {
238 delta = get_delta(&rt, &master_time_stamp);
240 done = 1; /* let's lock on to this... */
246 adjust_latency += -delta;
247 adj = -delta + adjust_latency/4;
251 tick_ops->add_tick(adj, current_tick_offset);
255 t[i].master = master_time_stamp;
257 t[i].lat = adjust_latency/4;
261 local_irq_restore(flags);
264 for (i = 0; i < NUM_ROUNDS; i++)
265 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
266 t[i].rt, t[i].master, t[i].diff, t[i].lat);
269 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
270 "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
273 static void smp_start_sync_tick_client(int cpu);
275 static void smp_synchronize_one_tick(int cpu)
277 unsigned long flags, i;
281 smp_start_sync_tick_client(cpu);
283 /* wait for client to be ready */
287 /* now let the client proceed into his loop */
291 spin_lock_irqsave(&itc_sync_lock, flags);
293 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
298 go[SLAVE] = tick_ops->get_tick();
302 spin_unlock_irqrestore(&itc_sync_lock, flags);
305 extern unsigned long sparc64_cpu_startup;
307 /* The OBP cpu startup callback truncates the 3rd arg cookie to
308 * 32-bits (I think) so to be safe we have it read the pointer
309 * contained here so we work on >4GB machines. -DaveM
311 static struct thread_info *cpu_new_thread = NULL;
313 static int __devinit smp_boot_one_cpu(unsigned int cpu)
315 unsigned long entry =
316 (unsigned long)(&sparc64_cpu_startup);
317 unsigned long cookie =
318 (unsigned long)(&cpu_new_thread);
319 struct task_struct *p;
320 int timeout, ret, cpu_node;
324 cpu_new_thread = task_thread_info(p);
325 cpu_set(cpu, cpu_callout_map);
327 cpu_find_by_mid(cpu, &cpu_node);
328 prom_startcpu(cpu_node, entry, cookie);
330 for (timeout = 0; timeout < 5000000; timeout++) {
338 printk("Processor %d is stuck.\n", cpu);
339 cpu_clear(cpu, cpu_callout_map);
342 cpu_new_thread = NULL;
347 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
352 if (this_is_starfire) {
353 /* map to real upaid */
354 cpu = (((cpu & 0x3c) << 1) |
355 ((cpu & 0x40) >> 4) |
359 target = (cpu << 14) | 0x70;
361 /* Ok, this is the real Spitfire Errata #54.
362 * One must read back from a UDB internal register
363 * after writes to the UDB interrupt dispatch, but
364 * before the membar Sync for that write.
365 * So we use the high UDB control register (ASI 0x7f,
366 * ADDR 0x20) for the dummy read. -DaveM
369 __asm__ __volatile__(
370 "wrpr %1, %2, %%pstate\n\t"
371 "stxa %4, [%0] %3\n\t"
372 "stxa %5, [%0+%8] %3\n\t"
374 "stxa %6, [%0+%8] %3\n\t"
376 "stxa %%g0, [%7] %3\n\t"
379 "ldxa [%%g1] 0x7f, %%g0\n\t"
382 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
383 "r" (data0), "r" (data1), "r" (data2), "r" (target),
384 "r" (0x10), "0" (tmp)
387 /* NOTE: PSTATE_IE is still clear. */
390 __asm__ __volatile__("ldxa [%%g0] %1, %0"
392 : "i" (ASI_INTR_DISPATCH_STAT));
394 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
401 } while (result & 0x1);
402 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
405 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
406 smp_processor_id(), result);
413 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
418 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
419 for_each_cpu_mask(i, mask)
420 spitfire_xcall_helper(data0, data1, data2, pstate, i);
423 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
424 * packet, but we have no use for that. However we do take advantage of
425 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
427 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
430 int nack_busy_id, is_jbus;
432 if (cpus_empty(mask))
435 /* Unfortunately, someone at Sun had the brilliant idea to make the
436 * busy/nack fields hard-coded by ITID number for this Ultra-III
437 * derivative processor.
439 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
440 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
441 (ver >> 32) == __SERRANO_ID);
443 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
446 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
447 : : "r" (pstate), "i" (PSTATE_IE));
449 /* Setup the dispatch data registers. */
450 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
451 "stxa %1, [%4] %6\n\t"
452 "stxa %2, [%5] %6\n\t"
455 : "r" (data0), "r" (data1), "r" (data2),
456 "r" (0x40), "r" (0x50), "r" (0x60),
463 for_each_cpu_mask(i, mask) {
464 u64 target = (i << 14) | 0x70;
467 target |= (nack_busy_id << 24);
468 __asm__ __volatile__(
469 "stxa %%g0, [%0] %1\n\t"
472 : "r" (target), "i" (ASI_INTR_W));
477 /* Now, poll for completion. */
482 stuck = 100000 * nack_busy_id;
484 __asm__ __volatile__("ldxa [%%g0] %1, %0"
485 : "=r" (dispatch_stat)
486 : "i" (ASI_INTR_DISPATCH_STAT));
487 if (dispatch_stat == 0UL) {
488 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
494 } while (dispatch_stat & 0x5555555555555555UL);
496 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
499 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
500 /* Busy bits will not clear, continue instead
501 * of freezing up on this cpu.
503 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
504 smp_processor_id(), dispatch_stat);
506 int i, this_busy_nack = 0;
508 /* Delay some random time with interrupts enabled
509 * to prevent deadlock.
511 udelay(2 * nack_busy_id);
513 /* Clear out the mask bits for cpus which did not
516 for_each_cpu_mask(i, mask) {
520 check_mask = (0x2UL << (2*i));
522 check_mask = (0x2UL <<
524 if ((dispatch_stat & check_mask) == 0)
535 /* Multi-cpu list version. */
536 static int init_cpu_list(u16 *list, cpumask_t mask)
541 for_each_cpu_mask(i, mask)
547 static int update_cpu_list(u16 *list, int orig_cnt, cpumask_t mask)
551 for (i = 0; i < orig_cnt; i++) {
552 if (list[i] == 0xffff)
556 return init_cpu_list(list, mask);
559 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
561 int this_cpu = get_cpu();
562 struct trap_per_cpu *tb = &trap_block[this_cpu];
563 u64 *mondo = __va(tb->cpu_mondo_block_pa);
564 u16 *cpu_list = __va(tb->cpu_list_pa);
573 cnt = init_cpu_list(cpu_list, mask);
575 register unsigned long func __asm__("%o5");
576 register unsigned long arg0 __asm__("%o0");
577 register unsigned long arg1 __asm__("%o1");
578 register unsigned long arg2 __asm__("%o2");
580 func = HV_FAST_CPU_MONDO_SEND;
582 arg1 = tb->cpu_list_pa;
583 arg2 = tb->cpu_mondo_block_pa;
585 __asm__ __volatile__("ta %8"
586 : "=&r" (func), "=&r" (arg0),
587 "=&r" (arg1), "=&r" (arg2)
588 : "0" (func), "1" (arg0),
589 "2" (arg1), "3" (arg2),
592 if (likely(arg0 == HV_EOK))
595 if (unlikely(++retries > 100)) {
596 printk("CPU[%d]: sun4v mondo error %lu\n",
601 cnt = update_cpu_list(cpu_list, cnt, mask);
609 /* Single-cpu list version. */
610 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
612 int this_cpu = get_cpu();
613 struct trap_per_cpu *tb = &trap_block[this_cpu];
614 u64 *mondo = __va(tb->cpu_mondo_block_pa);
615 u16 *cpu_list = __va(tb->cpu_list_pa);
623 for_each_cpu_mask(i, mask) {
627 register unsigned long func __asm__("%o5");
628 register unsigned long arg0 __asm__("%o0");
629 register unsigned long arg1 __asm__("%o1");
630 register unsigned long arg2 __asm__("%o2");
633 func = HV_FAST_CPU_MONDO_SEND;
635 arg1 = tb->cpu_list_pa;
636 arg2 = tb->cpu_mondo_block_pa;
638 __asm__ __volatile__("ta %8"
639 : "=&r" (func), "=&r" (arg0),
640 "=&r" (arg1), "=&r" (arg2)
641 : "0" (func), "1" (arg0),
642 "2" (arg1), "3" (arg2),
645 if (likely(arg0 == HV_EOK))
648 if (unlikely(++retries > 100)) {
649 printk("CPU[%d]: sun4v mondo error %lu\n",
662 /* Send cross call to all processors mentioned in MASK
665 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
667 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
668 int this_cpu = get_cpu();
670 cpus_and(mask, mask, cpu_online_map);
671 cpu_clear(this_cpu, mask);
673 if (tlb_type == spitfire)
674 spitfire_xcall_deliver(data0, data1, data2, mask);
675 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
676 cheetah_xcall_deliver(data0, data1, data2, mask);
678 hypervisor_xcall_deliver(data0, data1, data2, mask);
679 /* NOTE: Caller runs local copy on master. */
684 extern unsigned long xcall_sync_tick;
686 static void smp_start_sync_tick_client(int cpu)
688 cpumask_t mask = cpumask_of_cpu(cpu);
690 smp_cross_call_masked(&xcall_sync_tick,
694 /* Send cross call to all processors except self. */
695 #define smp_cross_call(func, ctx, data1, data2) \
696 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
698 struct call_data_struct {
699 void (*func) (void *info);
705 static DEFINE_SPINLOCK(call_lock);
706 static struct call_data_struct *call_data;
708 extern unsigned long xcall_call_function;
711 * You must not call this function with disabled interrupts or from a
712 * hardware interrupt handler or from a bottom half handler.
714 static int smp_call_function_mask(void (*func)(void *info), void *info,
715 int nonatomic, int wait, cpumask_t mask)
717 struct call_data_struct data;
718 int cpus = cpus_weight(mask) - 1;
724 /* Can deadlock when called with interrupts disabled */
725 WARN_ON(irqs_disabled());
729 atomic_set(&data.finished, 0);
732 spin_lock(&call_lock);
736 smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
739 * Wait for other cpus to complete function or at
740 * least snap the call data.
743 while (atomic_read(&data.finished) != cpus) {
750 spin_unlock(&call_lock);
755 spin_unlock(&call_lock);
756 printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
757 (long) num_online_cpus() - 1L,
758 (long) atomic_read(&data.finished));
762 int smp_call_function(void (*func)(void *info), void *info,
763 int nonatomic, int wait)
765 return smp_call_function_mask(func, info, nonatomic, wait,
769 void smp_call_function_client(int irq, struct pt_regs *regs)
771 void (*func) (void *info) = call_data->func;
772 void *info = call_data->info;
774 clear_softint(1 << irq);
775 if (call_data->wait) {
776 /* let initiator proceed only after completion */
778 atomic_inc(&call_data->finished);
780 /* let initiator proceed after getting data */
781 atomic_inc(&call_data->finished);
786 static void tsb_sync(void *info)
788 struct mm_struct *mm = info;
790 if (current->active_mm == mm)
791 tsb_context_switch(mm);
794 void smp_tsb_sync(struct mm_struct *mm)
796 smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
799 extern unsigned long xcall_flush_tlb_mm;
800 extern unsigned long xcall_flush_tlb_pending;
801 extern unsigned long xcall_flush_tlb_kernel_range;
802 extern unsigned long xcall_report_regs;
803 extern unsigned long xcall_receive_signal;
805 #ifdef DCACHE_ALIASING_POSSIBLE
806 extern unsigned long xcall_flush_dcache_page_cheetah;
808 extern unsigned long xcall_flush_dcache_page_spitfire;
810 #ifdef CONFIG_DEBUG_DCFLUSH
811 extern atomic_t dcpage_flushes;
812 extern atomic_t dcpage_flushes_xcall;
815 static __inline__ void __local_flush_dcache_page(struct page *page)
817 #ifdef DCACHE_ALIASING_POSSIBLE
818 __flush_dcache_page(page_address(page),
819 ((tlb_type == spitfire) &&
820 page_mapping(page) != NULL));
822 if (page_mapping(page) != NULL &&
823 tlb_type == spitfire)
824 __flush_icache_page(__pa(page_address(page)));
828 void smp_flush_dcache_page_impl(struct page *page, int cpu)
830 cpumask_t mask = cpumask_of_cpu(cpu);
833 if (tlb_type == hypervisor)
836 #ifdef CONFIG_DEBUG_DCFLUSH
837 atomic_inc(&dcpage_flushes);
840 this_cpu = get_cpu();
842 if (cpu == this_cpu) {
843 __local_flush_dcache_page(page);
844 } else if (cpu_online(cpu)) {
845 void *pg_addr = page_address(page);
848 if (tlb_type == spitfire) {
850 ((u64)&xcall_flush_dcache_page_spitfire);
851 if (page_mapping(page) != NULL)
852 data0 |= ((u64)1 << 32);
853 spitfire_xcall_deliver(data0,
857 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
858 #ifdef DCACHE_ALIASING_POSSIBLE
860 ((u64)&xcall_flush_dcache_page_cheetah);
861 cheetah_xcall_deliver(data0,
866 #ifdef CONFIG_DEBUG_DCFLUSH
867 atomic_inc(&dcpage_flushes_xcall);
874 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
876 void *pg_addr = page_address(page);
877 cpumask_t mask = cpu_online_map;
881 if (tlb_type == hypervisor)
884 this_cpu = get_cpu();
886 cpu_clear(this_cpu, mask);
888 #ifdef CONFIG_DEBUG_DCFLUSH
889 atomic_inc(&dcpage_flushes);
891 if (cpus_empty(mask))
893 if (tlb_type == spitfire) {
894 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
895 if (page_mapping(page) != NULL)
896 data0 |= ((u64)1 << 32);
897 spitfire_xcall_deliver(data0,
901 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
902 #ifdef DCACHE_ALIASING_POSSIBLE
903 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
904 cheetah_xcall_deliver(data0,
909 #ifdef CONFIG_DEBUG_DCFLUSH
910 atomic_inc(&dcpage_flushes_xcall);
913 __local_flush_dcache_page(page);
918 void smp_receive_signal(int cpu)
920 cpumask_t mask = cpumask_of_cpu(cpu);
922 if (cpu_online(cpu)) {
923 u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
925 if (tlb_type == spitfire)
926 spitfire_xcall_deliver(data0, 0, 0, mask);
927 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
928 cheetah_xcall_deliver(data0, 0, 0, mask);
929 else if (tlb_type == hypervisor)
930 hypervisor_xcall_deliver(data0, 0, 0, mask);
934 void smp_receive_signal_client(int irq, struct pt_regs *regs)
936 /* Just return, rtrap takes care of the rest. */
937 clear_softint(1 << irq);
940 void smp_report_regs(void)
942 smp_cross_call(&xcall_report_regs, 0, 0, 0);
945 /* We know that the window frames of the user have been flushed
946 * to the stack before we get here because all callers of us
947 * are flush_tlb_*() routines, and these run after flush_cache_*()
948 * which performs the flushw.
950 * The SMP TLB coherency scheme we use works as follows:
952 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
953 * space has (potentially) executed on, this is the heuristic
954 * we use to avoid doing cross calls.
956 * Also, for flushing from kswapd and also for clones, we
957 * use cpu_vm_mask as the list of cpus to make run the TLB.
959 * 2) TLB context numbers are shared globally across all processors
960 * in the system, this allows us to play several games to avoid
963 * One invariant is that when a cpu switches to a process, and
964 * that processes tsk->active_mm->cpu_vm_mask does not have the
965 * current cpu's bit set, that tlb context is flushed locally.
967 * If the address space is non-shared (ie. mm->count == 1) we avoid
968 * cross calls when we want to flush the currently running process's
969 * tlb state. This is done by clearing all cpu bits except the current
970 * processor's in current->active_mm->cpu_vm_mask and performing the
971 * flush locally only. This will force any subsequent cpus which run
972 * this task to flush the context from the local tlb if the process
973 * migrates to another cpu (again).
975 * 3) For shared address spaces (threads) and swapping we bite the
976 * bullet for most cases and perform the cross call (but only to
977 * the cpus listed in cpu_vm_mask).
979 * The performance gain from "optimizing" away the cross call for threads is
980 * questionable (in theory the big win for threads is the massive sharing of
981 * address space state across processors).
984 /* This currently is only used by the hugetlb arch pre-fault
985 * hook on UltraSPARC-III+ and later when changing the pagesize
986 * bits of the context register for an address space.
988 void smp_flush_tlb_mm(struct mm_struct *mm)
990 u32 ctx = CTX_HWBITS(mm->context);
993 if (atomic_read(&mm->mm_users) == 1) {
994 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
995 goto local_flush_and_out;
998 smp_cross_call_masked(&xcall_flush_tlb_mm,
1002 local_flush_and_out:
1003 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1008 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1010 u32 ctx = CTX_HWBITS(mm->context);
1011 int cpu = get_cpu();
1013 if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1014 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1016 smp_cross_call_masked(&xcall_flush_tlb_pending,
1017 ctx, nr, (unsigned long) vaddrs,
1020 __flush_tlb_pending(ctx, nr, vaddrs);
1025 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1028 end = PAGE_ALIGN(end);
1030 smp_cross_call(&xcall_flush_tlb_kernel_range,
1033 __flush_tlb_kernel_range(start, end);
1038 /* #define CAPTURE_DEBUG */
1039 extern unsigned long xcall_capture;
1041 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1042 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1043 static unsigned long penguins_are_doing_time;
1045 void smp_capture(void)
1047 int result = atomic_add_ret(1, &smp_capture_depth);
1050 int ncpus = num_online_cpus();
1052 #ifdef CAPTURE_DEBUG
1053 printk("CPU[%d]: Sending penguins to jail...",
1054 smp_processor_id());
1056 penguins_are_doing_time = 1;
1057 membar_storestore_loadstore();
1058 atomic_inc(&smp_capture_registry);
1059 smp_cross_call(&xcall_capture, 0, 0, 0);
1060 while (atomic_read(&smp_capture_registry) != ncpus)
1062 #ifdef CAPTURE_DEBUG
1068 void smp_release(void)
1070 if (atomic_dec_and_test(&smp_capture_depth)) {
1071 #ifdef CAPTURE_DEBUG
1072 printk("CPU[%d]: Giving pardon to "
1073 "imprisoned penguins\n",
1074 smp_processor_id());
1076 penguins_are_doing_time = 0;
1077 membar_storeload_storestore();
1078 atomic_dec(&smp_capture_registry);
1082 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1083 * can service tlb flush xcalls...
1085 extern void prom_world(int);
1087 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1089 clear_softint(1 << irq);
1093 __asm__ __volatile__("flushw");
1095 atomic_inc(&smp_capture_registry);
1096 membar_storeload_storestore();
1097 while (penguins_are_doing_time)
1099 atomic_dec(&smp_capture_registry);
1105 #define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
1106 #define prof_counter(__cpu) cpu_data(__cpu).counter
1108 void smp_percpu_timer_interrupt(struct pt_regs *regs)
1110 unsigned long compare, tick, pstate;
1111 int cpu = smp_processor_id();
1112 int user = user_mode(regs);
1115 * Check for level 14 softint.
1118 unsigned long tick_mask = tick_ops->softint_mask;
1120 if (!(get_softint() & tick_mask)) {
1121 extern void handler_irq(int, struct pt_regs *);
1123 handler_irq(14, regs);
1126 clear_softint(tick_mask);
1130 profile_tick(CPU_PROFILING, regs);
1131 if (!--prof_counter(cpu)) {
1134 if (cpu == boot_cpu_id) {
1135 kstat_this_cpu.irqs[0]++;
1136 timer_tick_interrupt(regs);
1139 update_process_times(user);
1143 prof_counter(cpu) = prof_multiplier(cpu);
1146 /* Guarantee that the following sequences execute
1149 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
1150 "wrpr %0, %1, %%pstate"
1154 compare = tick_ops->add_compare(current_tick_offset);
1155 tick = tick_ops->get_tick();
1157 /* Restore PSTATE_IE. */
1158 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
1161 } while (time_after_eq(tick, compare));
1164 static void __init smp_setup_percpu_timer(void)
1166 int cpu = smp_processor_id();
1167 unsigned long pstate;
1169 prof_counter(cpu) = prof_multiplier(cpu) = 1;
1171 /* Guarantee that the following sequences execute
1174 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
1175 "wrpr %0, %1, %%pstate"
1179 tick_ops->init_tick(current_tick_offset);
1181 /* Restore PSTATE_IE. */
1182 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
1187 void __init smp_tick_init(void)
1189 boot_cpu_id = hard_smp_processor_id();
1190 current_tick_offset = timer_tick_offset;
1192 cpu_set(boot_cpu_id, cpu_online_map);
1193 prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1196 /* /proc/profile writes can call this, don't __init it please. */
1197 static DEFINE_SPINLOCK(prof_setup_lock);
1199 int setup_profiling_timer(unsigned int multiplier)
1201 unsigned long flags;
1204 if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1207 spin_lock_irqsave(&prof_setup_lock, flags);
1208 for (i = 0; i < NR_CPUS; i++)
1209 prof_multiplier(i) = multiplier;
1210 current_tick_offset = (timer_tick_offset / multiplier);
1211 spin_unlock_irqrestore(&prof_setup_lock, flags);
1216 /* Constrain the number of cpus to max_cpus. */
1217 void __init smp_prepare_cpus(unsigned int max_cpus)
1219 if (num_possible_cpus() > max_cpus) {
1223 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1224 if (mid != boot_cpu_id) {
1225 cpu_clear(mid, phys_cpu_present_map);
1226 if (num_possible_cpus() <= max_cpus)
1233 smp_store_cpu_info(boot_cpu_id);
1236 /* Set this up early so that things like the scheduler can init
1237 * properly. We use the same cpu mask for both the present and
1240 void __init smp_setup_cpu_possible_map(void)
1245 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1247 cpu_set(mid, phys_cpu_present_map);
1252 void __devinit smp_prepare_boot_cpu(void)
1254 int cpu = hard_smp_processor_id();
1256 if (cpu >= NR_CPUS) {
1257 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1261 current_thread_info()->cpu = cpu;
1262 __local_per_cpu_offset = __per_cpu_offset(cpu);
1264 cpu_set(smp_processor_id(), cpu_online_map);
1265 cpu_set(smp_processor_id(), phys_cpu_present_map);
1268 int __devinit __cpu_up(unsigned int cpu)
1270 int ret = smp_boot_one_cpu(cpu);
1273 cpu_set(cpu, smp_commenced_mask);
1274 while (!cpu_isset(cpu, cpu_online_map))
1276 if (!cpu_isset(cpu, cpu_online_map)) {
1279 /* On SUN4V, writes to %tick and %stick are
1282 if (tlb_type != hypervisor)
1283 smp_synchronize_one_tick(cpu);
1289 void __init smp_cpus_done(unsigned int max_cpus)
1291 unsigned long bogosum = 0;
1294 for (i = 0; i < NR_CPUS; i++) {
1296 bogosum += cpu_data(i).udelay_val;
1298 printk("Total of %ld processors activated "
1299 "(%lu.%02lu BogoMIPS).\n",
1300 (long) num_online_cpus(),
1301 bogosum/(500000/HZ),
1302 (bogosum/(5000/HZ))%100);
1305 void smp_send_reschedule(int cpu)
1307 smp_receive_signal(cpu);
1310 /* This is a nop because we capture all other cpus
1311 * anyways when making the PROM active.
1313 void smp_send_stop(void)
1317 unsigned long __per_cpu_base __read_mostly;
1318 unsigned long __per_cpu_shift __read_mostly;
1320 EXPORT_SYMBOL(__per_cpu_base);
1321 EXPORT_SYMBOL(__per_cpu_shift);
1323 void __init setup_per_cpu_areas(void)
1325 unsigned long goal, size, i;
1328 /* Copy section for each CPU (we discard the original) */
1329 goal = ALIGN(__per_cpu_end - __per_cpu_start, SMP_CACHE_BYTES);
1330 #ifdef CONFIG_MODULES
1331 if (goal < PERCPU_ENOUGH_ROOM)
1332 goal = PERCPU_ENOUGH_ROOM;
1334 __per_cpu_shift = 0;
1335 for (size = 1UL; size < goal; size <<= 1UL)
1338 ptr = alloc_bootmem(size * NR_CPUS);
1340 __per_cpu_base = ptr - __per_cpu_start;
1342 for (i = 0; i < NR_CPUS; i++, ptr += size)
1343 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);