1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
19 #include <linux/seq_file.h>
20 #include <linux/cache.h>
21 #include <linux/jiffies.h>
22 #include <linux/profile.h>
23 #include <linux/bootmem.h>
26 #include <asm/ptrace.h>
27 #include <asm/atomic.h>
28 #include <asm/tlbflush.h>
29 #include <asm/mmu_context.h>
30 #include <asm/cpudata.h>
33 #include <asm/irq_regs.h>
35 #include <asm/pgtable.h>
36 #include <asm/oplib.h>
37 #include <asm/uaccess.h>
38 #include <asm/timer.h>
39 #include <asm/starfire.h>
41 #include <asm/sections.h>
43 #include <asm/mdesc.h>
45 extern void calibrate_delay(void);
47 /* Please don't make this stuff initdata!!! --DaveM */
48 unsigned char boot_cpu_id;
50 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
51 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
52 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly =
53 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
54 static cpumask_t smp_commenced_mask;
55 static cpumask_t cpu_callout_map;
57 void smp_info(struct seq_file *m)
61 seq_printf(m, "State:\n");
62 for_each_online_cpu(i)
63 seq_printf(m, "CPU%d:\t\tonline\n", i);
66 void smp_bogo(struct seq_file *m)
70 for_each_online_cpu(i)
72 "Cpu%dBogo\t: %lu.%02lu\n"
73 "Cpu%dClkTck\t: %016lx\n",
74 i, cpu_data(i).udelay_val / (500000/HZ),
75 (cpu_data(i).udelay_val / (5000/HZ)) % 100,
76 i, cpu_data(i).clock_tick);
79 extern void setup_sparc64_timer(void);
81 static volatile unsigned long callin_flag = 0;
83 void __init smp_callin(void)
85 int cpuid = hard_smp_processor_id();
87 __local_per_cpu_offset = __per_cpu_offset(cpuid);
89 if (tlb_type == hypervisor)
90 sun4v_ktsb_register();
94 setup_sparc64_timer();
96 if (cheetah_pcache_forced_on)
97 cheetah_enable_pcache();
102 cpu_data(cpuid).udelay_val = loops_per_jiffy;
104 __asm__ __volatile__("membar #Sync\n\t"
105 "flush %%g6" : : : "memory");
107 /* Clear this or we will die instantly when we
108 * schedule back to this idler...
110 current_thread_info()->new_child = 0;
112 /* Attach to the address space of init_task. */
113 atomic_inc(&init_mm.mm_count);
114 current->active_mm = &init_mm;
116 while (!cpu_isset(cpuid, smp_commenced_mask))
119 cpu_set(cpuid, cpu_online_map);
121 /* idle thread is expected to have preempt disabled */
127 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
128 panic("SMP bolixed\n");
131 /* This tick register synchronization scheme is taken entirely from
132 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
134 * The only change I've made is to rework it so that the master
135 * initiates the synchonization instead of the slave. -DaveM
139 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
141 #define NUM_ROUNDS 64 /* magic value */
142 #define NUM_ITERS 5 /* likewise */
144 static DEFINE_SPINLOCK(itc_sync_lock);
145 static unsigned long go[SLAVE + 1];
147 #define DEBUG_TICK_SYNC 0
149 static inline long get_delta (long *rt, long *master)
151 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
152 unsigned long tcenter, t0, t1, tm;
155 for (i = 0; i < NUM_ITERS; i++) {
156 t0 = tick_ops->get_tick();
159 while (!(tm = go[SLAVE]))
163 t1 = tick_ops->get_tick();
165 if (t1 - t0 < best_t1 - best_t0)
166 best_t0 = t0, best_t1 = t1, best_tm = tm;
169 *rt = best_t1 - best_t0;
170 *master = best_tm - best_t0;
172 /* average best_t0 and best_t1 without overflow: */
173 tcenter = (best_t0/2 + best_t1/2);
174 if (best_t0 % 2 + best_t1 % 2 == 2)
176 return tcenter - best_tm;
179 void smp_synchronize_tick_client(void)
181 long i, delta, adj, adjust_latency = 0, done = 0;
182 unsigned long flags, rt, master_time_stamp, bound;
185 long rt; /* roundtrip time */
186 long master; /* master's timestamp */
187 long diff; /* difference between midpoint and master's timestamp */
188 long lat; /* estimate of itc adjustment latency */
197 local_irq_save(flags);
199 for (i = 0; i < NUM_ROUNDS; i++) {
200 delta = get_delta(&rt, &master_time_stamp);
202 done = 1; /* let's lock on to this... */
208 adjust_latency += -delta;
209 adj = -delta + adjust_latency/4;
213 tick_ops->add_tick(adj);
217 t[i].master = master_time_stamp;
219 t[i].lat = adjust_latency/4;
223 local_irq_restore(flags);
226 for (i = 0; i < NUM_ROUNDS; i++)
227 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
228 t[i].rt, t[i].master, t[i].diff, t[i].lat);
231 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
232 "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
235 static void smp_start_sync_tick_client(int cpu);
237 static void smp_synchronize_one_tick(int cpu)
239 unsigned long flags, i;
243 smp_start_sync_tick_client(cpu);
245 /* wait for client to be ready */
249 /* now let the client proceed into his loop */
253 spin_lock_irqsave(&itc_sync_lock, flags);
255 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
260 go[SLAVE] = tick_ops->get_tick();
264 spin_unlock_irqrestore(&itc_sync_lock, flags);
267 extern void sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load);
269 extern unsigned long sparc64_cpu_startup;
271 /* The OBP cpu startup callback truncates the 3rd arg cookie to
272 * 32-bits (I think) so to be safe we have it read the pointer
273 * contained here so we work on >4GB machines. -DaveM
275 static struct thread_info *cpu_new_thread = NULL;
277 static int __devinit smp_boot_one_cpu(unsigned int cpu)
279 unsigned long entry =
280 (unsigned long)(&sparc64_cpu_startup);
281 unsigned long cookie =
282 (unsigned long)(&cpu_new_thread);
283 struct task_struct *p;
288 cpu_new_thread = task_thread_info(p);
289 cpu_set(cpu, cpu_callout_map);
291 if (tlb_type == hypervisor) {
292 /* Alloc the mondo queues, cpu will load them. */
293 sun4v_init_mondo_queues(0, cpu, 1, 0);
295 prom_startcpu_cpuid(cpu, entry, cookie);
297 struct device_node *dp = of_find_node_by_cpuid(cpu);
299 prom_startcpu(dp->node, entry, cookie);
302 for (timeout = 0; timeout < 5000000; timeout++) {
311 printk("Processor %d is stuck.\n", cpu);
312 cpu_clear(cpu, cpu_callout_map);
315 cpu_new_thread = NULL;
320 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
325 if (this_is_starfire) {
326 /* map to real upaid */
327 cpu = (((cpu & 0x3c) << 1) |
328 ((cpu & 0x40) >> 4) |
332 target = (cpu << 14) | 0x70;
334 /* Ok, this is the real Spitfire Errata #54.
335 * One must read back from a UDB internal register
336 * after writes to the UDB interrupt dispatch, but
337 * before the membar Sync for that write.
338 * So we use the high UDB control register (ASI 0x7f,
339 * ADDR 0x20) for the dummy read. -DaveM
342 __asm__ __volatile__(
343 "wrpr %1, %2, %%pstate\n\t"
344 "stxa %4, [%0] %3\n\t"
345 "stxa %5, [%0+%8] %3\n\t"
347 "stxa %6, [%0+%8] %3\n\t"
349 "stxa %%g0, [%7] %3\n\t"
352 "ldxa [%%g1] 0x7f, %%g0\n\t"
355 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
356 "r" (data0), "r" (data1), "r" (data2), "r" (target),
357 "r" (0x10), "0" (tmp)
360 /* NOTE: PSTATE_IE is still clear. */
363 __asm__ __volatile__("ldxa [%%g0] %1, %0"
365 : "i" (ASI_INTR_DISPATCH_STAT));
367 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
374 } while (result & 0x1);
375 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
378 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
379 smp_processor_id(), result);
386 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
391 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
392 for_each_cpu_mask(i, mask)
393 spitfire_xcall_helper(data0, data1, data2, pstate, i);
396 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
397 * packet, but we have no use for that. However we do take advantage of
398 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
400 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
403 int nack_busy_id, is_jbus, need_more;
405 if (cpus_empty(mask))
408 /* Unfortunately, someone at Sun had the brilliant idea to make the
409 * busy/nack fields hard-coded by ITID number for this Ultra-III
410 * derivative processor.
412 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
413 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
414 (ver >> 32) == __SERRANO_ID);
416 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
420 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
421 : : "r" (pstate), "i" (PSTATE_IE));
423 /* Setup the dispatch data registers. */
424 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
425 "stxa %1, [%4] %6\n\t"
426 "stxa %2, [%5] %6\n\t"
429 : "r" (data0), "r" (data1), "r" (data2),
430 "r" (0x40), "r" (0x50), "r" (0x60),
437 for_each_cpu_mask(i, mask) {
438 u64 target = (i << 14) | 0x70;
441 target |= (nack_busy_id << 24);
442 __asm__ __volatile__(
443 "stxa %%g0, [%0] %1\n\t"
446 : "r" (target), "i" (ASI_INTR_W));
448 if (nack_busy_id == 32) {
455 /* Now, poll for completion. */
460 stuck = 100000 * nack_busy_id;
462 __asm__ __volatile__("ldxa [%%g0] %1, %0"
463 : "=r" (dispatch_stat)
464 : "i" (ASI_INTR_DISPATCH_STAT));
465 if (dispatch_stat == 0UL) {
466 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
468 if (unlikely(need_more)) {
470 for_each_cpu_mask(i, mask) {
482 } while (dispatch_stat & 0x5555555555555555UL);
484 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
487 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
488 /* Busy bits will not clear, continue instead
489 * of freezing up on this cpu.
491 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
492 smp_processor_id(), dispatch_stat);
494 int i, this_busy_nack = 0;
496 /* Delay some random time with interrupts enabled
497 * to prevent deadlock.
499 udelay(2 * nack_busy_id);
501 /* Clear out the mask bits for cpus which did not
504 for_each_cpu_mask(i, mask) {
508 check_mask = (0x2UL << (2*i));
510 check_mask = (0x2UL <<
512 if ((dispatch_stat & check_mask) == 0)
515 if (this_busy_nack == 64)
524 /* Multi-cpu list version. */
525 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
527 struct trap_per_cpu *tb;
530 cpumask_t error_mask;
531 unsigned long flags, status;
532 int cnt, retries, this_cpu, prev_sent, i;
534 if (cpus_empty(mask))
537 /* We have to do this whole thing with interrupts fully disabled.
538 * Otherwise if we send an xcall from interrupt context it will
539 * corrupt both our mondo block and cpu list state.
541 * One consequence of this is that we cannot use timeout mechanisms
542 * that depend upon interrupts being delivered locally. So, for
543 * example, we cannot sample jiffies and expect it to advance.
545 * Fortunately, udelay() uses %stick/%tick so we can use that.
547 local_irq_save(flags);
549 this_cpu = smp_processor_id();
550 tb = &trap_block[this_cpu];
552 mondo = __va(tb->cpu_mondo_block_pa);
558 cpu_list = __va(tb->cpu_list_pa);
560 /* Setup the initial cpu list. */
562 for_each_cpu_mask(i, mask)
565 cpus_clear(error_mask);
569 int forward_progress, n_sent;
571 status = sun4v_cpu_mondo_send(cnt,
573 tb->cpu_mondo_block_pa);
575 /* HV_EOK means all cpus received the xcall, we're done. */
576 if (likely(status == HV_EOK))
579 /* First, see if we made any forward progress.
581 * The hypervisor indicates successful sends by setting
582 * cpu list entries to the value 0xffff.
585 for (i = 0; i < cnt; i++) {
586 if (likely(cpu_list[i] == 0xffff))
590 forward_progress = 0;
591 if (n_sent > prev_sent)
592 forward_progress = 1;
596 /* If we get a HV_ECPUERROR, then one or more of the cpus
597 * in the list are in error state. Use the cpu_state()
598 * hypervisor call to find out which cpus are in error state.
600 if (unlikely(status == HV_ECPUERROR)) {
601 for (i = 0; i < cnt; i++) {
609 err = sun4v_cpu_state(cpu);
611 err == HV_CPU_STATE_ERROR) {
612 cpu_list[i] = 0xffff;
613 cpu_set(cpu, error_mask);
616 } else if (unlikely(status != HV_EWOULDBLOCK))
617 goto fatal_mondo_error;
619 /* Don't bother rewriting the CPU list, just leave the
620 * 0xffff and non-0xffff entries in there and the
621 * hypervisor will do the right thing.
623 * Only advance timeout state if we didn't make any
626 if (unlikely(!forward_progress)) {
627 if (unlikely(++retries > 10000))
628 goto fatal_mondo_timeout;
630 /* Delay a little bit to let other cpus catch up
631 * on their cpu mondo queue work.
637 local_irq_restore(flags);
639 if (unlikely(!cpus_empty(error_mask)))
640 goto fatal_mondo_cpu_error;
644 fatal_mondo_cpu_error:
645 printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
646 "were in error state\n",
648 printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu);
649 for_each_cpu_mask(i, error_mask)
655 local_irq_restore(flags);
656 printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
657 " progress after %d retries.\n",
659 goto dump_cpu_list_and_out;
662 local_irq_restore(flags);
663 printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
665 printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
666 "mondo_block_pa(%lx)\n",
667 this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
669 dump_cpu_list_and_out:
670 printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
671 for (i = 0; i < cnt; i++)
672 printk("%u ", cpu_list[i]);
676 /* Send cross call to all processors mentioned in MASK
679 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
681 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
682 int this_cpu = get_cpu();
684 cpus_and(mask, mask, cpu_online_map);
685 cpu_clear(this_cpu, mask);
687 if (tlb_type == spitfire)
688 spitfire_xcall_deliver(data0, data1, data2, mask);
689 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
690 cheetah_xcall_deliver(data0, data1, data2, mask);
692 hypervisor_xcall_deliver(data0, data1, data2, mask);
693 /* NOTE: Caller runs local copy on master. */
698 extern unsigned long xcall_sync_tick;
700 static void smp_start_sync_tick_client(int cpu)
702 cpumask_t mask = cpumask_of_cpu(cpu);
704 smp_cross_call_masked(&xcall_sync_tick,
708 /* Send cross call to all processors except self. */
709 #define smp_cross_call(func, ctx, data1, data2) \
710 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
712 struct call_data_struct {
713 void (*func) (void *info);
719 static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock);
720 static struct call_data_struct *call_data;
722 extern unsigned long xcall_call_function;
725 * smp_call_function(): Run a function on all other CPUs.
726 * @func: The function to run. This must be fast and non-blocking.
727 * @info: An arbitrary pointer to pass to the function.
728 * @nonatomic: currently unused.
729 * @wait: If true, wait (atomically) until function has completed on other CPUs.
731 * Returns 0 on success, else a negative status code. Does not return until
732 * remote CPUs are nearly ready to execute <<func>> or are or have executed.
734 * You must not call this function with disabled interrupts or from a
735 * hardware interrupt handler or from a bottom half handler.
737 static int smp_call_function_mask(void (*func)(void *info), void *info,
738 int nonatomic, int wait, cpumask_t mask)
740 struct call_data_struct data;
743 /* Can deadlock when called with interrupts disabled */
744 WARN_ON(irqs_disabled());
748 atomic_set(&data.finished, 0);
751 spin_lock(&call_lock);
753 cpu_clear(smp_processor_id(), mask);
754 cpus = cpus_weight(mask);
761 smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
763 /* Wait for response */
764 while (atomic_read(&data.finished) != cpus)
768 spin_unlock(&call_lock);
773 int smp_call_function(void (*func)(void *info), void *info,
774 int nonatomic, int wait)
776 return smp_call_function_mask(func, info, nonatomic, wait,
780 void smp_call_function_client(int irq, struct pt_regs *regs)
782 void (*func) (void *info) = call_data->func;
783 void *info = call_data->info;
785 clear_softint(1 << irq);
786 if (call_data->wait) {
787 /* let initiator proceed only after completion */
789 atomic_inc(&call_data->finished);
791 /* let initiator proceed after getting data */
792 atomic_inc(&call_data->finished);
797 static void tsb_sync(void *info)
799 struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
800 struct mm_struct *mm = info;
802 /* It is not valid to test "currrent->active_mm == mm" here.
804 * The value of "current" is not changed atomically with
805 * switch_mm(). But that's OK, we just need to check the
806 * current cpu's trap block PGD physical address.
808 if (tp->pgd_paddr == __pa(mm->pgd))
809 tsb_context_switch(mm);
812 void smp_tsb_sync(struct mm_struct *mm)
814 smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask);
817 extern unsigned long xcall_flush_tlb_mm;
818 extern unsigned long xcall_flush_tlb_pending;
819 extern unsigned long xcall_flush_tlb_kernel_range;
820 extern unsigned long xcall_report_regs;
821 extern unsigned long xcall_receive_signal;
822 extern unsigned long xcall_new_mmu_context_version;
824 #ifdef DCACHE_ALIASING_POSSIBLE
825 extern unsigned long xcall_flush_dcache_page_cheetah;
827 extern unsigned long xcall_flush_dcache_page_spitfire;
829 #ifdef CONFIG_DEBUG_DCFLUSH
830 extern atomic_t dcpage_flushes;
831 extern atomic_t dcpage_flushes_xcall;
834 static __inline__ void __local_flush_dcache_page(struct page *page)
836 #ifdef DCACHE_ALIASING_POSSIBLE
837 __flush_dcache_page(page_address(page),
838 ((tlb_type == spitfire) &&
839 page_mapping(page) != NULL));
841 if (page_mapping(page) != NULL &&
842 tlb_type == spitfire)
843 __flush_icache_page(__pa(page_address(page)));
847 void smp_flush_dcache_page_impl(struct page *page, int cpu)
849 cpumask_t mask = cpumask_of_cpu(cpu);
852 if (tlb_type == hypervisor)
855 #ifdef CONFIG_DEBUG_DCFLUSH
856 atomic_inc(&dcpage_flushes);
859 this_cpu = get_cpu();
861 if (cpu == this_cpu) {
862 __local_flush_dcache_page(page);
863 } else if (cpu_online(cpu)) {
864 void *pg_addr = page_address(page);
867 if (tlb_type == spitfire) {
869 ((u64)&xcall_flush_dcache_page_spitfire);
870 if (page_mapping(page) != NULL)
871 data0 |= ((u64)1 << 32);
872 spitfire_xcall_deliver(data0,
876 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
877 #ifdef DCACHE_ALIASING_POSSIBLE
879 ((u64)&xcall_flush_dcache_page_cheetah);
880 cheetah_xcall_deliver(data0,
885 #ifdef CONFIG_DEBUG_DCFLUSH
886 atomic_inc(&dcpage_flushes_xcall);
893 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
895 void *pg_addr = page_address(page);
896 cpumask_t mask = cpu_online_map;
900 if (tlb_type == hypervisor)
903 this_cpu = get_cpu();
905 cpu_clear(this_cpu, mask);
907 #ifdef CONFIG_DEBUG_DCFLUSH
908 atomic_inc(&dcpage_flushes);
910 if (cpus_empty(mask))
912 if (tlb_type == spitfire) {
913 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
914 if (page_mapping(page) != NULL)
915 data0 |= ((u64)1 << 32);
916 spitfire_xcall_deliver(data0,
920 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
921 #ifdef DCACHE_ALIASING_POSSIBLE
922 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
923 cheetah_xcall_deliver(data0,
928 #ifdef CONFIG_DEBUG_DCFLUSH
929 atomic_inc(&dcpage_flushes_xcall);
932 __local_flush_dcache_page(page);
937 static void __smp_receive_signal_mask(cpumask_t mask)
939 smp_cross_call_masked(&xcall_receive_signal, 0, 0, 0, mask);
942 void smp_receive_signal(int cpu)
944 cpumask_t mask = cpumask_of_cpu(cpu);
947 __smp_receive_signal_mask(mask);
950 void smp_receive_signal_client(int irq, struct pt_regs *regs)
952 clear_softint(1 << irq);
955 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
957 struct mm_struct *mm;
960 clear_softint(1 << irq);
962 /* See if we need to allocate a new TLB context because
963 * the version of the one we are using is now out of date.
965 mm = current->active_mm;
966 if (unlikely(!mm || (mm == &init_mm)))
969 spin_lock_irqsave(&mm->context.lock, flags);
971 if (unlikely(!CTX_VALID(mm->context)))
972 get_new_mmu_context(mm);
974 spin_unlock_irqrestore(&mm->context.lock, flags);
976 load_secondary_context(mm);
977 __flush_tlb_mm(CTX_HWBITS(mm->context),
981 void smp_new_mmu_context_version(void)
983 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
986 void smp_report_regs(void)
988 smp_cross_call(&xcall_report_regs, 0, 0, 0);
991 /* We know that the window frames of the user have been flushed
992 * to the stack before we get here because all callers of us
993 * are flush_tlb_*() routines, and these run after flush_cache_*()
994 * which performs the flushw.
996 * The SMP TLB coherency scheme we use works as follows:
998 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
999 * space has (potentially) executed on, this is the heuristic
1000 * we use to avoid doing cross calls.
1002 * Also, for flushing from kswapd and also for clones, we
1003 * use cpu_vm_mask as the list of cpus to make run the TLB.
1005 * 2) TLB context numbers are shared globally across all processors
1006 * in the system, this allows us to play several games to avoid
1009 * One invariant is that when a cpu switches to a process, and
1010 * that processes tsk->active_mm->cpu_vm_mask does not have the
1011 * current cpu's bit set, that tlb context is flushed locally.
1013 * If the address space is non-shared (ie. mm->count == 1) we avoid
1014 * cross calls when we want to flush the currently running process's
1015 * tlb state. This is done by clearing all cpu bits except the current
1016 * processor's in current->active_mm->cpu_vm_mask and performing the
1017 * flush locally only. This will force any subsequent cpus which run
1018 * this task to flush the context from the local tlb if the process
1019 * migrates to another cpu (again).
1021 * 3) For shared address spaces (threads) and swapping we bite the
1022 * bullet for most cases and perform the cross call (but only to
1023 * the cpus listed in cpu_vm_mask).
1025 * The performance gain from "optimizing" away the cross call for threads is
1026 * questionable (in theory the big win for threads is the massive sharing of
1027 * address space state across processors).
1030 /* This currently is only used by the hugetlb arch pre-fault
1031 * hook on UltraSPARC-III+ and later when changing the pagesize
1032 * bits of the context register for an address space.
1034 void smp_flush_tlb_mm(struct mm_struct *mm)
1036 u32 ctx = CTX_HWBITS(mm->context);
1037 int cpu = get_cpu();
1039 if (atomic_read(&mm->mm_users) == 1) {
1040 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1041 goto local_flush_and_out;
1044 smp_cross_call_masked(&xcall_flush_tlb_mm,
1048 local_flush_and_out:
1049 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1054 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1056 u32 ctx = CTX_HWBITS(mm->context);
1057 int cpu = get_cpu();
1059 if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1060 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1062 smp_cross_call_masked(&xcall_flush_tlb_pending,
1063 ctx, nr, (unsigned long) vaddrs,
1066 __flush_tlb_pending(ctx, nr, vaddrs);
1071 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1074 end = PAGE_ALIGN(end);
1076 smp_cross_call(&xcall_flush_tlb_kernel_range,
1079 __flush_tlb_kernel_range(start, end);
1084 /* #define CAPTURE_DEBUG */
1085 extern unsigned long xcall_capture;
1087 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1088 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1089 static unsigned long penguins_are_doing_time;
1091 void smp_capture(void)
1093 int result = atomic_add_ret(1, &smp_capture_depth);
1096 int ncpus = num_online_cpus();
1098 #ifdef CAPTURE_DEBUG
1099 printk("CPU[%d]: Sending penguins to jail...",
1100 smp_processor_id());
1102 penguins_are_doing_time = 1;
1103 membar_storestore_loadstore();
1104 atomic_inc(&smp_capture_registry);
1105 smp_cross_call(&xcall_capture, 0, 0, 0);
1106 while (atomic_read(&smp_capture_registry) != ncpus)
1108 #ifdef CAPTURE_DEBUG
1114 void smp_release(void)
1116 if (atomic_dec_and_test(&smp_capture_depth)) {
1117 #ifdef CAPTURE_DEBUG
1118 printk("CPU[%d]: Giving pardon to "
1119 "imprisoned penguins\n",
1120 smp_processor_id());
1122 penguins_are_doing_time = 0;
1123 membar_storeload_storestore();
1124 atomic_dec(&smp_capture_registry);
1128 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1129 * can service tlb flush xcalls...
1131 extern void prom_world(int);
1133 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1135 clear_softint(1 << irq);
1139 __asm__ __volatile__("flushw");
1141 atomic_inc(&smp_capture_registry);
1142 membar_storeload_storestore();
1143 while (penguins_are_doing_time)
1145 atomic_dec(&smp_capture_registry);
1151 void __init smp_tick_init(void)
1153 boot_cpu_id = hard_smp_processor_id();
1156 /* /proc/profile writes can call this, don't __init it please. */
1157 int setup_profiling_timer(unsigned int multiplier)
1162 static void __init smp_tune_scheduling(void)
1164 unsigned int smallest = ~0U;
1167 for (i = 0; i < NR_CPUS; i++) {
1168 unsigned int val = cpu_data(i).ecache_size;
1170 if (val && val < smallest)
1174 /* Any value less than 256K is nonsense. */
1175 if (smallest < (256U * 1024U))
1176 smallest = 256 * 1024;
1178 max_cache_size = smallest;
1180 if (smallest < 1U * 1024U * 1024U)
1181 printk(KERN_INFO "Using max_cache_size of %uKB\n",
1184 printk(KERN_INFO "Using max_cache_size of %uMB\n",
1185 smallest / 1024U / 1024U);
1188 /* Constrain the number of cpus to max_cpus. */
1189 void __init smp_prepare_cpus(unsigned int max_cpus)
1193 if (num_possible_cpus() > max_cpus) {
1194 for_each_possible_cpu(i) {
1195 if (i != boot_cpu_id) {
1196 cpu_clear(i, phys_cpu_present_map);
1197 cpu_clear(i, cpu_present_map);
1198 if (num_possible_cpus() <= max_cpus)
1204 cpu_data(boot_cpu_id).udelay_val = loops_per_jiffy;
1205 smp_tune_scheduling();
1208 void __devinit smp_prepare_boot_cpu(void)
1212 void __devinit smp_fill_in_sib_core_maps(void)
1216 for_each_possible_cpu(i) {
1219 if (cpu_data(i).core_id == 0) {
1220 cpu_set(i, cpu_sibling_map[i]);
1224 for_each_possible_cpu(j) {
1225 if (cpu_data(i).core_id ==
1226 cpu_data(j).core_id)
1227 cpu_set(j, cpu_sibling_map[i]);
1232 int __cpuinit __cpu_up(unsigned int cpu)
1234 int ret = smp_boot_one_cpu(cpu);
1237 cpu_set(cpu, smp_commenced_mask);
1238 while (!cpu_isset(cpu, cpu_online_map))
1240 if (!cpu_isset(cpu, cpu_online_map)) {
1243 /* On SUN4V, writes to %tick and %stick are
1246 if (tlb_type != hypervisor)
1247 smp_synchronize_one_tick(cpu);
1253 void __init smp_cpus_done(unsigned int max_cpus)
1255 unsigned long bogosum = 0;
1258 for_each_online_cpu(i)
1259 bogosum += cpu_data(i).udelay_val;
1260 printk("Total of %ld processors activated "
1261 "(%lu.%02lu BogoMIPS).\n",
1262 (long) num_online_cpus(),
1263 bogosum/(500000/HZ),
1264 (bogosum/(5000/HZ))%100);
1267 void smp_send_reschedule(int cpu)
1269 smp_receive_signal(cpu);
1272 /* This is a nop because we capture all other cpus
1273 * anyways when making the PROM active.
1275 void smp_send_stop(void)
1279 unsigned long __per_cpu_base __read_mostly;
1280 unsigned long __per_cpu_shift __read_mostly;
1282 EXPORT_SYMBOL(__per_cpu_base);
1283 EXPORT_SYMBOL(__per_cpu_shift);
1285 void __init real_setup_per_cpu_areas(void)
1287 unsigned long goal, size, i;
1290 /* Copy section for each CPU (we discard the original) */
1291 goal = PERCPU_ENOUGH_ROOM;
1293 __per_cpu_shift = PAGE_SHIFT;
1294 for (size = PAGE_SIZE; size < goal; size <<= 1UL)
1297 ptr = alloc_bootmem_pages(size * NR_CPUS);
1299 __per_cpu_base = ptr - __per_cpu_start;
1301 for (i = 0; i < NR_CPUS; i++, ptr += size)
1302 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1304 /* Setup %g5 for the boot cpu. */
1305 __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());