1 /* tsb.S: Sparc64 TSB table handling.
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
11 /* Invoked from TLB miss handler, we are in the
12 * MMU global registers and they are setup like
15 * %g1: TSB entry pointer
16 * %g2: available temporary
17 * %g3: FAULT_CODE_{D,I}TLB
18 * %g4: available temporary
19 * %g5: available temporary
21 * %g7: physical address base of the linux page
22 * tables for the current address space
26 mov TLB_TAG_ACCESS, %g4
27 ldxa [%g4] ASI_DMMU, %g4
28 ba,pt %xcc, tsb_miss_page_table_walk
33 mov TLB_TAG_ACCESS, %g4
34 ldxa [%g4] ASI_IMMU, %g4
35 ba,pt %xcc, tsb_miss_page_table_walk
38 tsb_miss_page_table_walk:
39 TRAP_LOAD_PGD_PHYS(%g7, %g5)
41 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
44 TSB_LOCK_TAG(%g1, %g2, %g4)
46 /* Load and check PTE. */
47 ldxa [%g5] ASI_PHYS_USE_EC, %g5
48 brgez,a,pn %g5, tsb_do_fault
51 /* If it is larger than the base page size, don't
52 * bother putting it into the TSB.
55 sethi %hi(_PAGE_ALL_SZ_BITS >> 32), %g4
56 sethi %hi(_PAGE_SZBITS >> 32), %g7
59 bne,a,pn %xcc, tsb_tlb_reload
62 TSB_WRITE(%g1, %g5, %g6)
64 /* Finally, load TLB and return from trap. */
66 cmp %g3, FAULT_CODE_DTLB
67 bne,pn %xcc, tsb_itlb_load
71 stxa %g5, [%g0] ASI_DTLB_DATA_IN
75 stxa %g5, [%g0] ASI_ITLB_DATA_IN
78 /* No valid entry in the page tables, do full fault
84 cmp %g3, FAULT_CODE_DTLB
86 bne,pn %xcc, tsb_do_itlb_fault
87 wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
92 mov TLB_TAG_ACCESS, %g4
93 ldxa [%g4] ASI_DMMU, %g5
94 be,pt %xcc, sparc64_realfault_common
95 mov FAULT_CODE_DTLB, %g4
96 ba,pt %xcc, winfix_trampoline
101 ba,pt %xcc, sparc64_realfault_common
102 mov FAULT_CODE_ITLB, %g4
104 .globl sparc64_realfault_common
105 sparc64_realfault_common:
106 /* fault code in %g4, fault address in %g5, etrap will
107 * preserve these two values in %l4 and %l5 respectively
109 ba,pt %xcc, etrap ! Save trap state
111 stb %l4, [%g6 + TI_FAULT_CODE] ! Save fault code
112 stx %l5, [%g6 + TI_FAULT_ADDR] ! Save fault address
113 call do_sparc64_fault ! Call fault handler
114 add %sp, PTREGS_OFF, %o0 ! Compute pt_regs arg
115 ba,pt %xcc, rtrap_clr_l6 ! Restore cpu state
116 nop ! Delay slot (fill me)
118 .globl winfix_trampoline
120 rdpr %tpc, %g3 ! Prepare winfixup TNPC
121 or %g3, 0x7c, %g3 ! Compute branch offset
122 wrpr %g3, %tnpc ! Write it into TNPC
125 /* Insert an entry into the TSB.
127 * %o0: TSB entry pointer (virt or phys address)
135 wrpr %o5, PSTATE_IE, %pstate
136 TSB_LOCK_TAG(%o0, %g2, %g3)
137 TSB_WRITE(%o0, %o2, %o1)
142 /* Flush the given TSB entry if it has the matching
145 * %o0: TSB entry pointer (virt or phys address)
151 sethi %hi(TSB_TAG_LOCK_HIGH), %g2
152 1: TSB_LOAD_TAG(%o0, %g1)
160 TSB_CAS_TAG(%o0, %g1, %o3)
167 /* Reload MMU related context switch state at
170 * %o0: page table physical address
171 * %o1: TSB register value
172 * %o2: TSB virtual address
173 * %o3: TSB mapping locked PTE
175 * We have to run this whole thing with interrupts
176 * disabled so that the current cpu doesn't change
180 .globl __tsb_context_switch
181 __tsb_context_switch:
183 wrpr %o5, PSTATE_IE, %pstate
185 ldub [%g6 + TI_CPU], %g1
186 sethi %hi(trap_block), %g2
187 sllx %g1, TRAP_BLOCK_SZ_SHIFT, %g1
188 or %g2, %lo(trap_block), %g2
190 stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR]
193 stxa %o1, [%g1] ASI_DMMU
196 stxa %o1, [%g1] ASI_IMMU
202 sethi %hi(sparc64_highest_unlocked_tlb_ent), %o4
203 mov TLB_TAG_ACCESS, %g1
204 lduw [%o4 + %lo(sparc64_highest_unlocked_tlb_ent)], %g2
205 stxa %o2, [%g1] ASI_DMMU
208 stxa %o3, [%g2] ASI_DTLB_DATA_ACCESS