1 /* mb.S: Out of line memory barriers.
3 * Copyright (C) 2005 David S. Miller (davem@davemloft.net)
6 /* These are here in an effort to more fully work around
7 * Spitfire Errata #51. Essentially, if a memory barrier
8 * occurs soon after a mispredicted branch, the chip can stop
9 * executing instructions until a trap occurs. Therefore, if
10 * interrupts are disabled, the chip can hang forever.
12 * It used to be believed that the memory barrier had to be
13 * right in the delay slot, but a case has been traced
14 * recently wherein the memory barrier was one instruction
15 * after the branch delay slot and the chip still hung. The
16 * offending sequence was the following in sym_wakeup_done()
17 * of the sym53c8xx_2 driver:
19 * call sym_ccb_from_dsa, 0
25 * The branch has to be mispredicted for the bug to occur.
26 * Therefore, we put the memory barrier explicitly into a
27 * "branch always, predicted taken" delay slot to avoid the
38 membar #LoadLoad | #LoadStore | #StoreStore | #StoreLoad
51 .globl membar_storeload
55 .size membar_storeload, .-membar_storeload
57 .globl membar_storeload_storestore
58 membar_storeload_storestore:
60 membar #StoreLoad | #StoreStore
61 .size membar_storeload_storestore, .-membar_storeload_storestore
63 .globl membar_storeload_loadload
64 membar_storeload_loadload:
66 membar #StoreLoad | #LoadLoad
67 .size membar_storeload_loadload, .-membar_storeload_loadload
69 .globl membar_storestore_loadstore
70 membar_storestore_loadstore:
72 membar #StoreStore | #LoadStore
73 .size membar_storestore_loadstore, .-membar_storestore_loadstore