1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/config.h>
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/bootmem.h>
16 #include <linux/hugetlb.h>
17 #include <linux/slab.h>
18 #include <linux/initrd.h>
19 #include <linux/swap.h>
20 #include <linux/pagemap.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
28 #include <asm/system.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/oplib.h>
33 #include <asm/iommu.h>
35 #include <asm/uaccess.h>
36 #include <asm/mmu_context.h>
37 #include <asm/tlbflush.h>
39 #include <asm/starfire.h>
41 #include <asm/spitfire.h>
42 #include <asm/sections.h>
44 #include <asm/hypervisor.h>
46 extern void device_scan(void);
48 #define MAX_PHYS_ADDRESS (1UL << 42UL)
49 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
50 #define KPTE_BITMAP_BYTES \
51 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
53 unsigned long kern_linear_pte_xor[2] __read_mostly;
55 /* A bitmap, one bit for every 256MB of physical memory. If the bit
56 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
57 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
59 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
63 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
64 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
65 static int pavail_ents __initdata;
66 static int pavail_rescan_ents __initdata;
68 static int cmp_p64(const void *a, const void *b)
70 const struct linux_prom64_registers *x = a, *y = b;
72 if (x->phys_addr > y->phys_addr)
74 if (x->phys_addr < y->phys_addr)
79 static void __init read_obp_memory(const char *property,
80 struct linux_prom64_registers *regs,
83 int node = prom_finddevice("/memory");
84 int prop_size = prom_getproplen(node, property);
87 ents = prop_size / sizeof(struct linux_prom64_registers);
88 if (ents > MAX_BANKS) {
89 prom_printf("The machine has more %s property entries than "
90 "this kernel can support (%d).\n",
95 ret = prom_getproperty(node, property, (char *) regs, prop_size);
97 prom_printf("Couldn't get %s property from /memory.\n");
103 /* Sanitize what we got from the firmware, by page aligning
106 for (i = 0; i < ents; i++) {
107 unsigned long base, size;
109 base = regs[i].phys_addr;
110 size = regs[i].reg_size;
113 if (base & ~PAGE_MASK) {
114 unsigned long new_base = PAGE_ALIGN(base);
116 size -= new_base - base;
117 if ((long) size < 0L)
121 regs[i].phys_addr = base;
122 regs[i].reg_size = size;
124 sort(regs, ents, sizeof(struct linux_prom64_registers),
128 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
130 /* Ugly, but necessary... -DaveM */
131 unsigned long phys_base __read_mostly;
132 unsigned long kern_base __read_mostly;
133 unsigned long kern_size __read_mostly;
134 unsigned long pfn_base __read_mostly;
136 /* get_new_mmu_context() uses "cache + 1". */
137 DEFINE_SPINLOCK(ctx_alloc_lock);
138 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
139 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
140 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
142 /* References to special section boundaries */
143 extern char _start[], _end[];
145 /* Initial ramdisk setup */
146 extern unsigned long sparc_ramdisk_image64;
147 extern unsigned int sparc_ramdisk_image;
148 extern unsigned int sparc_ramdisk_size;
150 struct page *mem_map_zero __read_mostly;
152 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
154 unsigned long sparc64_kern_pri_context __read_mostly;
155 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
156 unsigned long sparc64_kern_sec_context __read_mostly;
160 kmem_cache_t *pgtable_cache __read_mostly;
162 static void zero_ctor(void *addr, kmem_cache_t *cache, unsigned long flags)
167 void pgtable_cache_init(void)
169 pgtable_cache = kmem_cache_create("pgtable_cache",
170 PAGE_SIZE, PAGE_SIZE,
172 SLAB_MUST_HWCACHE_ALIGN,
175 if (!pgtable_cache) {
176 prom_printf("pgtable_cache_init(): Could not create!\n");
181 #ifdef CONFIG_DEBUG_DCFLUSH
182 atomic_t dcpage_flushes = ATOMIC_INIT(0);
184 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
188 __inline__ void flush_dcache_page_impl(struct page *page)
190 #ifdef CONFIG_DEBUG_DCFLUSH
191 atomic_inc(&dcpage_flushes);
194 #ifdef DCACHE_ALIASING_POSSIBLE
195 __flush_dcache_page(page_address(page),
196 ((tlb_type == spitfire) &&
197 page_mapping(page) != NULL));
199 if (page_mapping(page) != NULL &&
200 tlb_type == spitfire)
201 __flush_icache_page(__pa(page_address(page)));
205 #define PG_dcache_dirty PG_arch_1
206 #define PG_dcache_cpu_shift 24
207 #define PG_dcache_cpu_mask (256 - 1)
210 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
213 #define dcache_dirty_cpu(page) \
214 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
216 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
218 unsigned long mask = this_cpu;
219 unsigned long non_cpu_bits;
221 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
222 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
224 __asm__ __volatile__("1:\n\t"
226 "and %%g7, %1, %%g1\n\t"
227 "or %%g1, %0, %%g1\n\t"
228 "casx [%2], %%g7, %%g1\n\t"
230 "membar #StoreLoad | #StoreStore\n\t"
231 "bne,pn %%xcc, 1b\n\t"
234 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
238 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
240 unsigned long mask = (1UL << PG_dcache_dirty);
242 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
245 "srlx %%g7, %4, %%g1\n\t"
246 "and %%g1, %3, %%g1\n\t"
248 "bne,pn %%icc, 2f\n\t"
249 " andn %%g7, %1, %%g1\n\t"
250 "casx [%2], %%g7, %%g1\n\t"
252 "membar #StoreLoad | #StoreStore\n\t"
253 "bne,pn %%xcc, 1b\n\t"
257 : "r" (cpu), "r" (mask), "r" (&page->flags),
258 "i" (PG_dcache_cpu_mask),
259 "i" (PG_dcache_cpu_shift)
263 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
265 unsigned long tsb_addr = (unsigned long) ent;
267 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
268 tsb_addr = __pa(tsb_addr);
270 __tsb_insert(tsb_addr, tag, pte);
273 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
274 unsigned long _PAGE_SZBITS __read_mostly;
276 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
278 struct mm_struct *mm;
281 unsigned long pg_flags;
284 if (pfn_valid(pfn) &&
285 (page = pfn_to_page(pfn), page_mapping(page)) &&
286 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
287 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
289 int this_cpu = get_cpu();
291 /* This is just to optimize away some function calls
295 flush_dcache_page_impl(page);
297 smp_flush_dcache_page_impl(page, cpu);
299 clear_dcache_dirty_cpu(page, cpu);
305 if ((pte_val(pte) & _PAGE_ALL_SZ_BITS) == _PAGE_SZBITS) {
309 tsb = &mm->context.tsb[(address >> PAGE_SHIFT) &
310 (mm->context.tsb_nentries - 1UL)];
311 tag = (address >> 22UL);
312 tsb_insert(tsb, tag, pte_val(pte));
316 void flush_dcache_page(struct page *page)
318 struct address_space *mapping;
321 /* Do not bother with the expensive D-cache flush if it
322 * is merely the zero page. The 'bigcore' testcase in GDB
323 * causes this case to run millions of times.
325 if (page == ZERO_PAGE(0))
328 this_cpu = get_cpu();
330 mapping = page_mapping(page);
331 if (mapping && !mapping_mapped(mapping)) {
332 int dirty = test_bit(PG_dcache_dirty, &page->flags);
334 int dirty_cpu = dcache_dirty_cpu(page);
336 if (dirty_cpu == this_cpu)
338 smp_flush_dcache_page_impl(page, dirty_cpu);
340 set_dcache_dirty(page, this_cpu);
342 /* We could delay the flush for the !page_mapping
343 * case too. But that case is for exec env/arg
344 * pages and those are %99 certainly going to get
345 * faulted into the tlb (and thus flushed) anyways.
347 flush_dcache_page_impl(page);
354 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
356 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
357 if (tlb_type == spitfire) {
360 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
361 __flush_icache_page(__get_phys(kaddr));
365 unsigned long page_to_pfn(struct page *page)
367 return (unsigned long) ((page - mem_map) + pfn_base);
370 struct page *pfn_to_page(unsigned long pfn)
372 return (mem_map + (pfn - pfn_base));
377 printk("Mem-info:\n");
379 printk("Free swap: %6ldkB\n",
380 nr_swap_pages << (PAGE_SHIFT-10));
381 printk("%ld pages of RAM\n", num_physpages);
382 printk("%d free pages\n", nr_free_pages());
385 void mmu_info(struct seq_file *m)
387 if (tlb_type == cheetah)
388 seq_printf(m, "MMU Type\t: Cheetah\n");
389 else if (tlb_type == cheetah_plus)
390 seq_printf(m, "MMU Type\t: Cheetah+\n");
391 else if (tlb_type == spitfire)
392 seq_printf(m, "MMU Type\t: Spitfire\n");
393 else if (tlb_type == hypervisor)
394 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
396 seq_printf(m, "MMU Type\t: ???\n");
398 #ifdef CONFIG_DEBUG_DCFLUSH
399 seq_printf(m, "DCPageFlushes\t: %d\n",
400 atomic_read(&dcpage_flushes));
402 seq_printf(m, "DCPageFlushesXC\t: %d\n",
403 atomic_read(&dcpage_flushes_xcall));
404 #endif /* CONFIG_SMP */
405 #endif /* CONFIG_DEBUG_DCFLUSH */
408 struct linux_prom_translation {
414 /* Exported for kernel TLB miss handling in ktlb.S */
415 struct linux_prom_translation prom_trans[512] __read_mostly;
416 unsigned int prom_trans_ents __read_mostly;
418 /* Exported for SMP bootup purposes. */
419 unsigned long kern_locked_tte_data;
421 /* The obp translations are saved based on 8k pagesize, since obp can
422 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
423 * HI_OBP_ADDRESS range are handled in ktlb.S.
425 static inline int in_obp_range(unsigned long vaddr)
427 return (vaddr >= LOW_OBP_ADDRESS &&
428 vaddr < HI_OBP_ADDRESS);
431 static int cmp_ptrans(const void *a, const void *b)
433 const struct linux_prom_translation *x = a, *y = b;
435 if (x->virt > y->virt)
437 if (x->virt < y->virt)
442 /* Read OBP translations property into 'prom_trans[]'. */
443 static void __init read_obp_translations(void)
445 int n, node, ents, first, last, i;
447 node = prom_finddevice("/virtual-memory");
448 n = prom_getproplen(node, "translations");
449 if (unlikely(n == 0 || n == -1)) {
450 prom_printf("prom_mappings: Couldn't get size.\n");
453 if (unlikely(n > sizeof(prom_trans))) {
454 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
458 if ((n = prom_getproperty(node, "translations",
459 (char *)&prom_trans[0],
460 sizeof(prom_trans))) == -1) {
461 prom_printf("prom_mappings: Couldn't get property.\n");
465 n = n / sizeof(struct linux_prom_translation);
469 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
472 /* Now kick out all the non-OBP entries. */
473 for (i = 0; i < ents; i++) {
474 if (in_obp_range(prom_trans[i].virt))
478 for (; i < ents; i++) {
479 if (!in_obp_range(prom_trans[i].virt))
484 for (i = 0; i < (last - first); i++) {
485 struct linux_prom_translation *src = &prom_trans[i + first];
486 struct linux_prom_translation *dest = &prom_trans[i];
490 for (; i < ents; i++) {
491 struct linux_prom_translation *dest = &prom_trans[i];
492 dest->virt = dest->size = dest->data = 0x0UL;
495 prom_trans_ents = last - first;
497 if (tlb_type == spitfire) {
498 /* Clear diag TTE bits. */
499 for (i = 0; i < prom_trans_ents; i++)
500 prom_trans[i].data &= ~0x0003fe0000000000UL;
504 static void __init hypervisor_tlb_lock(unsigned long vaddr,
508 register unsigned long func asm("%o5");
509 register unsigned long arg0 asm("%o0");
510 register unsigned long arg1 asm("%o1");
511 register unsigned long arg2 asm("%o2");
512 register unsigned long arg3 asm("%o3");
514 func = HV_FAST_MMU_MAP_PERM_ADDR;
519 __asm__ __volatile__("ta 0x80"
520 : "=&r" (func), "=&r" (arg0),
521 "=&r" (arg1), "=&r" (arg2),
523 : "0" (func), "1" (arg0), "2" (arg1),
524 "3" (arg2), "4" (arg3));
526 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
527 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
532 static unsigned long kern_large_tte(unsigned long paddr);
534 static void __init remap_kernel(void)
536 unsigned long phys_page, tte_vaddr, tte_data;
537 int tlb_ent = sparc64_highest_locked_tlbent();
539 tte_vaddr = (unsigned long) KERNBASE;
540 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
541 tte_data = kern_large_tte(phys_page);
543 kern_locked_tte_data = tte_data;
545 /* Now lock us into the TLBs via Hypervisor or OBP. */
546 if (tlb_type == hypervisor) {
547 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
548 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
550 tte_vaddr += 0x400000;
551 tte_data += 0x400000;
552 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
553 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
556 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
557 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
560 prom_dtlb_load(tlb_ent,
562 tte_vaddr + 0x400000);
563 prom_itlb_load(tlb_ent,
565 tte_vaddr + 0x400000);
567 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
569 if (tlb_type == cheetah_plus) {
570 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
571 CTX_CHEETAH_PLUS_NUC);
572 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
573 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
578 static void __init inherit_prom_mappings(void)
580 read_obp_translations();
582 /* Now fixup OBP's idea about where we really are mapped. */
583 prom_printf("Remapping the kernel... ");
585 prom_printf("done.\n");
588 void prom_world(int enter)
591 set_fs((mm_segment_t) { get_thread_current_ds() });
593 __asm__ __volatile__("flushw");
596 #ifdef DCACHE_ALIASING_POSSIBLE
597 void __flush_dcache_range(unsigned long start, unsigned long end)
601 if (tlb_type == spitfire) {
604 for (va = start; va < end; va += 32) {
605 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
609 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
612 for (va = start; va < end; va += 32)
613 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
617 "i" (ASI_DCACHE_INVALIDATE));
620 #endif /* DCACHE_ALIASING_POSSIBLE */
622 /* Caller does TLB context flushing on local CPU if necessary.
623 * The caller also ensures that CTX_VALID(mm->context) is false.
625 * We must be careful about boundary cases so that we never
626 * let the user have CTX 0 (nucleus) or we ever use a CTX
627 * version of zero (and thus NO_CONTEXT would not be caught
628 * by version mis-match tests in mmu_context.h).
630 void get_new_mmu_context(struct mm_struct *mm)
632 unsigned long ctx, new_ctx;
633 unsigned long orig_pgsz_bits;
636 spin_lock(&ctx_alloc_lock);
637 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
638 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
639 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
640 if (new_ctx >= (1 << CTX_NR_BITS)) {
641 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
642 if (new_ctx >= ctx) {
644 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
647 new_ctx = CTX_FIRST_VERSION;
649 /* Don't call memset, for 16 entries that's just
652 mmu_context_bmap[0] = 3;
653 mmu_context_bmap[1] = 0;
654 mmu_context_bmap[2] = 0;
655 mmu_context_bmap[3] = 0;
656 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
657 mmu_context_bmap[i + 0] = 0;
658 mmu_context_bmap[i + 1] = 0;
659 mmu_context_bmap[i + 2] = 0;
660 mmu_context_bmap[i + 3] = 0;
665 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
666 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
668 tlb_context_cache = new_ctx;
669 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
670 spin_unlock(&ctx_alloc_lock);
673 void sparc_ultra_dump_itlb(void)
677 if (tlb_type == spitfire) {
678 printk ("Contents of itlb: ");
679 for (slot = 0; slot < 14; slot++) printk (" ");
680 printk ("%2x:%016lx,%016lx\n",
682 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
683 for (slot = 1; slot < 64; slot+=3) {
684 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
686 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
688 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
690 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
692 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
693 printk ("Contents of itlb0:\n");
694 for (slot = 0; slot < 16; slot+=2) {
695 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
697 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
699 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
701 printk ("Contents of itlb2:\n");
702 for (slot = 0; slot < 128; slot+=2) {
703 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
705 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
707 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
712 void sparc_ultra_dump_dtlb(void)
716 if (tlb_type == spitfire) {
717 printk ("Contents of dtlb: ");
718 for (slot = 0; slot < 14; slot++) printk (" ");
719 printk ("%2x:%016lx,%016lx\n", 0,
720 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
721 for (slot = 1; slot < 64; slot+=3) {
722 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
724 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
726 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
728 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
730 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
731 printk ("Contents of dtlb0:\n");
732 for (slot = 0; slot < 16; slot+=2) {
733 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
735 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
737 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
739 printk ("Contents of dtlb2:\n");
740 for (slot = 0; slot < 512; slot+=2) {
741 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
743 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
745 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
747 if (tlb_type == cheetah_plus) {
748 printk ("Contents of dtlb3:\n");
749 for (slot = 0; slot < 512; slot+=2) {
750 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
752 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
754 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
760 extern unsigned long cmdline_memory_size;
762 unsigned long __init bootmem_init(unsigned long *pages_avail)
764 unsigned long bootmap_size, start_pfn, end_pfn;
765 unsigned long end_of_phys_memory = 0UL;
766 unsigned long bootmap_pfn, bytes_avail, size;
769 #ifdef CONFIG_DEBUG_BOOTMEM
770 prom_printf("bootmem_init: Scan pavail, ");
774 for (i = 0; i < pavail_ents; i++) {
775 end_of_phys_memory = pavail[i].phys_addr +
777 bytes_avail += pavail[i].reg_size;
778 if (cmdline_memory_size) {
779 if (bytes_avail > cmdline_memory_size) {
780 unsigned long slack = bytes_avail - cmdline_memory_size;
782 bytes_avail -= slack;
783 end_of_phys_memory -= slack;
785 pavail[i].reg_size -= slack;
786 if ((long)pavail[i].reg_size <= 0L) {
787 pavail[i].phys_addr = 0xdeadbeefUL;
788 pavail[i].reg_size = 0UL;
791 pavail[i+1].reg_size = 0Ul;
792 pavail[i+1].phys_addr = 0xdeadbeefUL;
800 *pages_avail = bytes_avail >> PAGE_SHIFT;
802 /* Start with page aligned address of last symbol in kernel
803 * image. The kernel is hard mapped below PAGE_OFFSET in a
804 * 4MB locked TLB translation.
806 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
808 bootmap_pfn = start_pfn;
810 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
812 #ifdef CONFIG_BLK_DEV_INITRD
813 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
814 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
815 unsigned long ramdisk_image = sparc_ramdisk_image ?
816 sparc_ramdisk_image : sparc_ramdisk_image64;
817 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
818 ramdisk_image -= KERNBASE;
819 initrd_start = ramdisk_image + phys_base;
820 initrd_end = initrd_start + sparc_ramdisk_size;
821 if (initrd_end > end_of_phys_memory) {
822 printk(KERN_CRIT "initrd extends beyond end of memory "
823 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
824 initrd_end, end_of_phys_memory);
828 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
829 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
830 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
834 /* Initialize the boot-time allocator. */
835 max_pfn = max_low_pfn = end_pfn;
836 min_low_pfn = pfn_base;
838 #ifdef CONFIG_DEBUG_BOOTMEM
839 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
840 min_low_pfn, bootmap_pfn, max_low_pfn);
842 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
844 /* Now register the available physical memory with the
847 for (i = 0; i < pavail_ents; i++) {
848 #ifdef CONFIG_DEBUG_BOOTMEM
849 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
850 i, pavail[i].phys_addr, pavail[i].reg_size);
852 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
855 #ifdef CONFIG_BLK_DEV_INITRD
857 size = initrd_end - initrd_start;
859 /* Resert the initrd image area. */
860 #ifdef CONFIG_DEBUG_BOOTMEM
861 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
862 initrd_start, initrd_end);
864 reserve_bootmem(initrd_start, size);
865 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
867 initrd_start += PAGE_OFFSET;
868 initrd_end += PAGE_OFFSET;
871 /* Reserve the kernel text/data/bss. */
872 #ifdef CONFIG_DEBUG_BOOTMEM
873 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
875 reserve_bootmem(kern_base, kern_size);
876 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
878 /* Reserve the bootmem map. We do not account for it
879 * in pages_avail because we will release that memory
880 * in free_all_bootmem.
883 #ifdef CONFIG_DEBUG_BOOTMEM
884 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
885 (bootmap_pfn << PAGE_SHIFT), size);
887 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
888 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
893 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
894 static int pall_ents __initdata;
896 #ifdef CONFIG_DEBUG_PAGEALLOC
897 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
899 unsigned long vstart = PAGE_OFFSET + pstart;
900 unsigned long vend = PAGE_OFFSET + pend;
901 unsigned long alloc_bytes = 0UL;
903 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
904 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
909 while (vstart < vend) {
910 unsigned long this_end, paddr = __pa(vstart);
911 pgd_t *pgd = pgd_offset_k(vstart);
916 pud = pud_offset(pgd, vstart);
917 if (pud_none(*pud)) {
920 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
921 alloc_bytes += PAGE_SIZE;
922 pud_populate(&init_mm, pud, new);
925 pmd = pmd_offset(pud, vstart);
926 if (!pmd_present(*pmd)) {
929 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
930 alloc_bytes += PAGE_SIZE;
931 pmd_populate_kernel(&init_mm, pmd, new);
934 pte = pte_offset_kernel(pmd, vstart);
935 this_end = (vstart + PMD_SIZE) & PMD_MASK;
939 while (vstart < this_end) {
940 pte_val(*pte) = (paddr | pgprot_val(prot));
951 extern unsigned int kvmap_linear_patch[1];
952 #endif /* CONFIG_DEBUG_PAGEALLOC */
954 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
956 const unsigned long shift_256MB = 28;
957 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
958 const unsigned long size_256MB = (1UL << shift_256MB);
960 while (start < end) {
963 if (start & mask_256MB) {
964 start = (start + size_256MB) & ~mask_256MB;
968 remains = end - start;
969 while (remains >= size_256MB) {
970 unsigned long index = start >> shift_256MB;
972 __set_bit(index, kpte_linear_bitmap);
975 remains -= size_256MB;
980 static void __init kernel_physical_mapping_init(void)
983 #ifdef CONFIG_DEBUG_PAGEALLOC
984 unsigned long mem_alloced = 0UL;
987 read_obp_memory("reg", &pall[0], &pall_ents);
989 for (i = 0; i < pall_ents; i++) {
990 unsigned long phys_start, phys_end;
992 phys_start = pall[i].phys_addr;
993 phys_end = phys_start + pall[i].reg_size;
995 mark_kpte_bitmap(phys_start, phys_end);
997 #ifdef CONFIG_DEBUG_PAGEALLOC
998 mem_alloced += kernel_map_range(phys_start, phys_end,
1003 #ifdef CONFIG_DEBUG_PAGEALLOC
1004 printk("Allocated %ld bytes for kernel page tables.\n",
1007 kvmap_linear_patch[0] = 0x01000000; /* nop */
1008 flushi(&kvmap_linear_patch[0]);
1014 #ifdef CONFIG_DEBUG_PAGEALLOC
1015 void kernel_map_pages(struct page *page, int numpages, int enable)
1017 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1018 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1020 kernel_map_range(phys_start, phys_end,
1021 (enable ? PAGE_KERNEL : __pgprot(0)));
1023 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1024 PAGE_OFFSET + phys_end);
1026 /* we should perform an IPI and flush all tlbs,
1027 * but that can deadlock->flush only current cpu.
1029 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1030 PAGE_OFFSET + phys_end);
1034 unsigned long __init find_ecache_flush_span(unsigned long size)
1038 for (i = 0; i < pavail_ents; i++) {
1039 if (pavail[i].reg_size >= size)
1040 return pavail[i].phys_addr;
1046 static void __init tsb_phys_patch(void)
1048 struct tsb_ldquad_phys_patch_entry *pquad;
1049 struct tsb_phys_patch_entry *p;
1051 pquad = &__tsb_ldquad_phys_patch;
1052 while (pquad < &__tsb_ldquad_phys_patch_end) {
1053 unsigned long addr = pquad->addr;
1055 if (tlb_type == hypervisor)
1056 *(unsigned int *) addr = pquad->sun4v_insn;
1058 *(unsigned int *) addr = pquad->sun4u_insn;
1060 __asm__ __volatile__("flush %0"
1067 p = &__tsb_phys_patch;
1068 while (p < &__tsb_phys_patch_end) {
1069 unsigned long addr = p->addr;
1071 *(unsigned int *) addr = p->insn;
1073 __asm__ __volatile__("flush %0"
1081 /* Don't mark as init, we give this to the Hypervisor. */
1082 static struct hv_tsb_descr ktsb_descr[2];
1083 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1085 static void __init sun4v_ktsb_init(void)
1087 unsigned long ktsb_pa;
1089 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1091 switch (PAGE_SIZE) {
1094 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1095 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1099 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1100 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1104 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1105 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1108 case 4 * 1024 * 1024:
1109 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1110 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1114 ktsb_descr[0].assoc = 1;
1115 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1116 ktsb_descr[0].ctx_idx = 0;
1117 ktsb_descr[0].tsb_base = ktsb_pa;
1118 ktsb_descr[0].resv = 0;
1120 /* XXX When we have a kernel large page size TSB, describe
1121 * XXX it in ktsb_descr[1] here.
1125 void __cpuinit sun4v_ktsb_register(void)
1127 register unsigned long func asm("%o5");
1128 register unsigned long arg0 asm("%o0");
1129 register unsigned long arg1 asm("%o1");
1132 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1134 func = HV_FAST_MMU_TSB_CTX0;
1135 /* XXX set arg0 to 2 when we use ktsb_descr[1], see above XXX */
1138 __asm__ __volatile__("ta %6"
1139 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1140 : "0" (func), "1" (arg0), "2" (arg1),
1141 "i" (HV_FAST_TRAP));
1144 /* paging_init() sets up the page tables */
1146 extern void cheetah_ecache_flush_init(void);
1147 extern void sun4v_patch_tlb_handlers(void);
1149 static unsigned long last_valid_pfn;
1150 pgd_t swapper_pg_dir[2048];
1152 static void sun4u_pgprot_init(void);
1153 static void sun4v_pgprot_init(void);
1155 void __init paging_init(void)
1157 unsigned long end_pfn, pages_avail, shift;
1158 unsigned long real_end, i;
1160 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1161 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1163 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1165 if (tlb_type == hypervisor)
1166 sun4v_pgprot_init();
1168 sun4u_pgprot_init();
1170 if (tlb_type == cheetah_plus ||
1171 tlb_type == hypervisor)
1174 if (tlb_type == hypervisor) {
1175 sun4v_patch_tlb_handlers();
1179 /* Find available physical memory... */
1180 read_obp_memory("available", &pavail[0], &pavail_ents);
1182 phys_base = 0xffffffffffffffffUL;
1183 for (i = 0; i < pavail_ents; i++)
1184 phys_base = min(phys_base, pavail[i].phys_addr);
1186 pfn_base = phys_base >> PAGE_SHIFT;
1188 set_bit(0, mmu_context_bmap);
1190 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1192 real_end = (unsigned long)_end;
1193 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1195 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1196 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1200 /* Set kernel pgd to upper alias so physical page computations
1203 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1205 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1207 /* Now can init the kernel/bad page tables. */
1208 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1209 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1211 inherit_prom_mappings();
1213 /* Ok, we can use our TLB miss and window trap handlers safely. */
1218 if (tlb_type == hypervisor)
1219 sun4v_ktsb_register();
1221 /* Setup bootmem... */
1223 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1225 kernel_physical_mapping_init();
1228 unsigned long zones_size[MAX_NR_ZONES];
1229 unsigned long zholes_size[MAX_NR_ZONES];
1230 unsigned long npages;
1233 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1234 zones_size[znum] = zholes_size[znum] = 0;
1236 npages = end_pfn - pfn_base;
1237 zones_size[ZONE_DMA] = npages;
1238 zholes_size[ZONE_DMA] = npages - pages_avail;
1240 free_area_init_node(0, &contig_page_data, zones_size,
1241 phys_base >> PAGE_SHIFT, zholes_size);
1247 static void __init taint_real_pages(void)
1251 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1253 /* Find changes discovered in the physmem available rescan and
1254 * reserve the lost portions in the bootmem maps.
1256 for (i = 0; i < pavail_ents; i++) {
1257 unsigned long old_start, old_end;
1259 old_start = pavail[i].phys_addr;
1260 old_end = old_start +
1262 while (old_start < old_end) {
1265 for (n = 0; pavail_rescan_ents; n++) {
1266 unsigned long new_start, new_end;
1268 new_start = pavail_rescan[n].phys_addr;
1269 new_end = new_start +
1270 pavail_rescan[n].reg_size;
1272 if (new_start <= old_start &&
1273 new_end >= (old_start + PAGE_SIZE)) {
1274 set_bit(old_start >> 22,
1275 sparc64_valid_addr_bitmap);
1279 reserve_bootmem(old_start, PAGE_SIZE);
1282 old_start += PAGE_SIZE;
1287 void __init mem_init(void)
1289 unsigned long codepages, datapages, initpages;
1290 unsigned long addr, last;
1293 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1295 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1296 if (sparc64_valid_addr_bitmap == NULL) {
1297 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1300 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1302 addr = PAGE_OFFSET + kern_base;
1303 last = PAGE_ALIGN(kern_size) + addr;
1304 while (addr < last) {
1305 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1311 max_mapnr = last_valid_pfn - pfn_base;
1312 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1314 #ifdef CONFIG_DEBUG_BOOTMEM
1315 prom_printf("mem_init: Calling free_all_bootmem().\n");
1317 totalram_pages = num_physpages = free_all_bootmem() - 1;
1320 * Set up the zero page, mark it reserved, so that page count
1321 * is not manipulated when freeing the page from user ptes.
1323 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1324 if (mem_map_zero == NULL) {
1325 prom_printf("paging_init: Cannot alloc zero page.\n");
1328 SetPageReserved(mem_map_zero);
1330 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1331 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1332 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1333 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1334 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1335 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1337 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1338 nr_free_pages() << (PAGE_SHIFT-10),
1339 codepages << (PAGE_SHIFT-10),
1340 datapages << (PAGE_SHIFT-10),
1341 initpages << (PAGE_SHIFT-10),
1342 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1344 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1345 cheetah_ecache_flush_init();
1348 void free_initmem(void)
1350 unsigned long addr, initend;
1353 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1355 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1356 initend = (unsigned long)(__init_end) & PAGE_MASK;
1357 for (; addr < initend; addr += PAGE_SIZE) {
1362 ((unsigned long) __va(kern_base)) -
1363 ((unsigned long) KERNBASE));
1364 memset((void *)addr, 0xcc, PAGE_SIZE);
1365 p = virt_to_page(page);
1367 ClearPageReserved(p);
1368 set_page_count(p, 1);
1375 #ifdef CONFIG_BLK_DEV_INITRD
1376 void free_initrd_mem(unsigned long start, unsigned long end)
1379 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1380 for (; start < end; start += PAGE_SIZE) {
1381 struct page *p = virt_to_page(start);
1383 ClearPageReserved(p);
1384 set_page_count(p, 1);
1392 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1393 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1394 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1395 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1396 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1397 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1399 pgprot_t PAGE_KERNEL __read_mostly;
1400 EXPORT_SYMBOL(PAGE_KERNEL);
1402 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1403 pgprot_t PAGE_COPY __read_mostly;
1405 pgprot_t PAGE_SHARED __read_mostly;
1406 EXPORT_SYMBOL(PAGE_SHARED);
1408 pgprot_t PAGE_EXEC __read_mostly;
1409 unsigned long pg_iobits __read_mostly;
1411 unsigned long _PAGE_IE __read_mostly;
1412 unsigned long _PAGE_E __read_mostly;
1413 unsigned long _PAGE_CACHE __read_mostly;
1415 static void prot_init_common(unsigned long page_none,
1416 unsigned long page_shared,
1417 unsigned long page_copy,
1418 unsigned long page_readonly,
1419 unsigned long page_exec_bit)
1421 PAGE_COPY = __pgprot(page_copy);
1422 PAGE_SHARED = __pgprot(page_shared);
1424 protection_map[0x0] = __pgprot(page_none);
1425 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1426 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1427 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1428 protection_map[0x4] = __pgprot(page_readonly);
1429 protection_map[0x5] = __pgprot(page_readonly);
1430 protection_map[0x6] = __pgprot(page_copy);
1431 protection_map[0x7] = __pgprot(page_copy);
1432 protection_map[0x8] = __pgprot(page_none);
1433 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1434 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1435 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1436 protection_map[0xc] = __pgprot(page_readonly);
1437 protection_map[0xd] = __pgprot(page_readonly);
1438 protection_map[0xe] = __pgprot(page_shared);
1439 protection_map[0xf] = __pgprot(page_shared);
1442 static void __init sun4u_pgprot_init(void)
1444 unsigned long page_none, page_shared, page_copy, page_readonly;
1445 unsigned long page_exec_bit;
1447 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1448 _PAGE_CACHE_4U | _PAGE_P_4U |
1449 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1451 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1452 _PAGE_CACHE_4U | _PAGE_P_4U |
1453 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1454 _PAGE_EXEC_4U | _PAGE_L_4U);
1455 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1457 _PAGE_IE = _PAGE_IE_4U;
1458 _PAGE_E = _PAGE_E_4U;
1459 _PAGE_CACHE = _PAGE_CACHE_4U;
1461 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1462 __ACCESS_BITS_4U | _PAGE_E_4U);
1464 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1466 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1467 _PAGE_P_4U | _PAGE_W_4U);
1469 /* XXX Should use 256MB on Panther. XXX */
1470 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1472 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1473 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1474 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1475 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1478 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1479 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1480 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1481 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1482 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1483 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1484 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1486 page_exec_bit = _PAGE_EXEC_4U;
1488 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1492 static void __init sun4v_pgprot_init(void)
1494 unsigned long page_none, page_shared, page_copy, page_readonly;
1495 unsigned long page_exec_bit;
1497 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1498 _PAGE_CACHE_4V | _PAGE_P_4V |
1499 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1501 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1502 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1504 _PAGE_IE = _PAGE_IE_4V;
1505 _PAGE_E = _PAGE_E_4V;
1506 _PAGE_CACHE = _PAGE_CACHE_4V;
1508 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1510 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1511 _PAGE_P_4V | _PAGE_W_4V);
1513 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1515 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1516 _PAGE_P_4V | _PAGE_W_4V);
1518 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1519 __ACCESS_BITS_4V | _PAGE_E_4V);
1521 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1522 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1523 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1524 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1525 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1527 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1528 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1529 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1530 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1531 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1532 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1533 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1535 page_exec_bit = _PAGE_EXEC_4V;
1537 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1541 unsigned long pte_sz_bits(unsigned long sz)
1543 if (tlb_type == hypervisor) {
1547 return _PAGE_SZ8K_4V;
1549 return _PAGE_SZ64K_4V;
1551 return _PAGE_SZ512K_4V;
1552 case 4 * 1024 * 1024:
1553 return _PAGE_SZ4MB_4V;
1559 return _PAGE_SZ8K_4U;
1561 return _PAGE_SZ64K_4U;
1563 return _PAGE_SZ512K_4U;
1564 case 4 * 1024 * 1024:
1565 return _PAGE_SZ4MB_4U;
1570 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1574 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1575 pte_val(pte) |= (((unsigned long)space) << 32);
1576 pte_val(pte) |= pte_sz_bits(page_size);
1581 static unsigned long kern_large_tte(unsigned long paddr)
1585 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1586 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1587 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1588 if (tlb_type == hypervisor)
1589 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1590 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1591 _PAGE_EXEC_4V | _PAGE_W_4V);
1597 * Translate PROM's mapping we capture at boot time into physical address.
1598 * The second parameter is only set from prom_callback() invocations.
1600 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1605 mask = _PAGE_PADDR_4U;
1606 if (tlb_type == hypervisor)
1607 mask = _PAGE_PADDR_4V;
1609 for (i = 0; i < prom_trans_ents; i++) {
1610 struct linux_prom_translation *p = &prom_trans[i];
1612 if (promva >= p->virt &&
1613 promva < (p->virt + p->size)) {
1614 unsigned long base = p->data & mask;
1618 return base + (promva & (8192 - 1));
1626 /* XXX We should kill off this ugly thing at so me point. XXX */
1627 unsigned long sun4u_get_pte(unsigned long addr)
1633 unsigned long mask = _PAGE_PADDR_4U;
1635 if (tlb_type == hypervisor)
1636 mask = _PAGE_PADDR_4V;
1638 if (addr >= PAGE_OFFSET)
1641 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1642 return prom_virt_to_phys(addr, NULL);
1644 pgdp = pgd_offset_k(addr);
1645 pudp = pud_offset(pgdp, addr);
1646 pmdp = pmd_offset(pudp, addr);
1647 ptep = pte_offset_kernel(pmdp, addr);
1649 return pte_val(*ptep) & mask;
1652 /* If not locked, zap it. */
1653 void __flush_tlb_all(void)
1655 unsigned long pstate;
1658 __asm__ __volatile__("flushw\n\t"
1659 "rdpr %%pstate, %0\n\t"
1660 "wrpr %0, %1, %%pstate"
1663 if (tlb_type == spitfire) {
1664 for (i = 0; i < 64; i++) {
1665 /* Spitfire Errata #32 workaround */
1666 /* NOTE: Always runs on spitfire, so no
1667 * cheetah+ page size encodings.
1669 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1673 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1675 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1676 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1679 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1680 spitfire_put_dtlb_data(i, 0x0UL);
1683 /* Spitfire Errata #32 workaround */
1684 /* NOTE: Always runs on spitfire, so no
1685 * cheetah+ page size encodings.
1687 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1691 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1693 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1694 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1697 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1698 spitfire_put_itlb_data(i, 0x0UL);
1701 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1702 cheetah_flush_dtlb_all();
1703 cheetah_flush_itlb_all();
1705 __asm__ __volatile__("wrpr %0, 0, %%pstate"