1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
28 #include <asm/system.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/oplib.h>
33 #include <asm/iommu.h>
35 #include <asm/uaccess.h>
36 #include <asm/mmu_context.h>
37 #include <asm/tlbflush.h>
39 #include <asm/starfire.h>
41 #include <asm/spitfire.h>
42 #include <asm/sections.h>
44 #include <asm/hypervisor.h>
47 extern void device_scan(void);
49 #define MAX_PHYS_ADDRESS (1UL << 42UL)
50 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
51 #define KPTE_BITMAP_BYTES \
52 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
54 unsigned long kern_linear_pte_xor[2] __read_mostly;
56 /* A bitmap, one bit for every 256MB of physical memory. If the bit
57 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
58 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62 #ifndef CONFIG_DEBUG_PAGEALLOC
63 /* A special kernel TSB for 4MB and 256MB linear mappings. */
64 struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
69 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
70 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
71 static int pavail_ents __initdata;
72 static int pavail_rescan_ents __initdata;
74 static int cmp_p64(const void *a, const void *b)
76 const struct linux_prom64_registers *x = a, *y = b;
78 if (x->phys_addr > y->phys_addr)
80 if (x->phys_addr < y->phys_addr)
85 static void __init read_obp_memory(const char *property,
86 struct linux_prom64_registers *regs,
89 int node = prom_finddevice("/memory");
90 int prop_size = prom_getproplen(node, property);
93 ents = prop_size / sizeof(struct linux_prom64_registers);
94 if (ents > MAX_BANKS) {
95 prom_printf("The machine has more %s property entries than "
96 "this kernel can support (%d).\n",
101 ret = prom_getproperty(node, property, (char *) regs, prop_size);
103 prom_printf("Couldn't get %s property from /memory.\n");
107 /* Sanitize what we got from the firmware, by page aligning
110 for (i = 0; i < ents; i++) {
111 unsigned long base, size;
113 base = regs[i].phys_addr;
114 size = regs[i].reg_size;
117 if (base & ~PAGE_MASK) {
118 unsigned long new_base = PAGE_ALIGN(base);
120 size -= new_base - base;
121 if ((long) size < 0L)
126 /* If it is empty, simply get rid of it.
127 * This simplifies the logic of the other
128 * functions that process these arrays.
130 memmove(®s[i], ®s[i + 1],
131 (ents - i - 1) * sizeof(regs[0]));
136 regs[i].phys_addr = base;
137 regs[i].reg_size = size;
142 sort(regs, ents, sizeof(struct linux_prom64_registers),
146 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
148 /* Kernel physical address base and size in bytes. */
149 unsigned long kern_base __read_mostly;
150 unsigned long kern_size __read_mostly;
152 /* Initial ramdisk setup */
153 extern unsigned long sparc_ramdisk_image64;
154 extern unsigned int sparc_ramdisk_image;
155 extern unsigned int sparc_ramdisk_size;
157 struct page *mem_map_zero __read_mostly;
159 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
161 unsigned long sparc64_kern_pri_context __read_mostly;
162 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
163 unsigned long sparc64_kern_sec_context __read_mostly;
167 struct kmem_cache *pgtable_cache __read_mostly;
169 static void zero_ctor(void *addr, struct kmem_cache *cache, unsigned long flags)
174 extern void tsb_cache_init(void);
176 void pgtable_cache_init(void)
178 pgtable_cache = kmem_cache_create("pgtable_cache",
179 PAGE_SIZE, PAGE_SIZE,
181 SLAB_MUST_HWCACHE_ALIGN,
184 if (!pgtable_cache) {
185 prom_printf("Could not create pgtable_cache\n");
191 #ifdef CONFIG_DEBUG_DCFLUSH
192 atomic_t dcpage_flushes = ATOMIC_INIT(0);
194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
198 inline void flush_dcache_page_impl(struct page *page)
200 BUG_ON(tlb_type == hypervisor);
201 #ifdef CONFIG_DEBUG_DCFLUSH
202 atomic_inc(&dcpage_flushes);
205 #ifdef DCACHE_ALIASING_POSSIBLE
206 __flush_dcache_page(page_address(page),
207 ((tlb_type == spitfire) &&
208 page_mapping(page) != NULL));
210 if (page_mapping(page) != NULL &&
211 tlb_type == spitfire)
212 __flush_icache_page(__pa(page_address(page)));
216 #define PG_dcache_dirty PG_arch_1
217 #define PG_dcache_cpu_shift 24UL
218 #define PG_dcache_cpu_mask (256UL - 1UL)
221 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
224 #define dcache_dirty_cpu(page) \
225 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
227 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
229 unsigned long mask = this_cpu;
230 unsigned long non_cpu_bits;
232 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
233 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
235 __asm__ __volatile__("1:\n\t"
237 "and %%g7, %1, %%g1\n\t"
238 "or %%g1, %0, %%g1\n\t"
239 "casx [%2], %%g7, %%g1\n\t"
241 "membar #StoreLoad | #StoreStore\n\t"
242 "bne,pn %%xcc, 1b\n\t"
245 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
249 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
251 unsigned long mask = (1UL << PG_dcache_dirty);
253 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
256 "srlx %%g7, %4, %%g1\n\t"
257 "and %%g1, %3, %%g1\n\t"
259 "bne,pn %%icc, 2f\n\t"
260 " andn %%g7, %1, %%g1\n\t"
261 "casx [%2], %%g7, %%g1\n\t"
263 "membar #StoreLoad | #StoreStore\n\t"
264 "bne,pn %%xcc, 1b\n\t"
268 : "r" (cpu), "r" (mask), "r" (&page->flags),
269 "i" (PG_dcache_cpu_mask),
270 "i" (PG_dcache_cpu_shift)
274 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
276 unsigned long tsb_addr = (unsigned long) ent;
278 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
279 tsb_addr = __pa(tsb_addr);
281 __tsb_insert(tsb_addr, tag, pte);
284 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
285 unsigned long _PAGE_SZBITS __read_mostly;
287 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
289 struct mm_struct *mm;
291 unsigned long tag, flags;
292 unsigned long tsb_index, tsb_hash_shift;
294 if (tlb_type != hypervisor) {
295 unsigned long pfn = pte_pfn(pte);
296 unsigned long pg_flags;
299 if (pfn_valid(pfn) &&
300 (page = pfn_to_page(pfn), page_mapping(page)) &&
301 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
302 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
304 int this_cpu = get_cpu();
306 /* This is just to optimize away some function calls
310 flush_dcache_page_impl(page);
312 smp_flush_dcache_page_impl(page, cpu);
314 clear_dcache_dirty_cpu(page, cpu);
322 tsb_index = MM_TSB_BASE;
323 tsb_hash_shift = PAGE_SHIFT;
325 spin_lock_irqsave(&mm->context.lock, flags);
327 #ifdef CONFIG_HUGETLB_PAGE
328 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
329 if ((tlb_type == hypervisor &&
330 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
331 (tlb_type != hypervisor &&
332 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
333 tsb_index = MM_TSB_HUGE;
334 tsb_hash_shift = HPAGE_SHIFT;
339 tsb = mm->context.tsb_block[tsb_index].tsb;
340 tsb += ((address >> tsb_hash_shift) &
341 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
342 tag = (address >> 22UL);
343 tsb_insert(tsb, tag, pte_val(pte));
345 spin_unlock_irqrestore(&mm->context.lock, flags);
348 void flush_dcache_page(struct page *page)
350 struct address_space *mapping;
353 if (tlb_type == hypervisor)
356 /* Do not bother with the expensive D-cache flush if it
357 * is merely the zero page. The 'bigcore' testcase in GDB
358 * causes this case to run millions of times.
360 if (page == ZERO_PAGE(0))
363 this_cpu = get_cpu();
365 mapping = page_mapping(page);
366 if (mapping && !mapping_mapped(mapping)) {
367 int dirty = test_bit(PG_dcache_dirty, &page->flags);
369 int dirty_cpu = dcache_dirty_cpu(page);
371 if (dirty_cpu == this_cpu)
373 smp_flush_dcache_page_impl(page, dirty_cpu);
375 set_dcache_dirty(page, this_cpu);
377 /* We could delay the flush for the !page_mapping
378 * case too. But that case is for exec env/arg
379 * pages and those are %99 certainly going to get
380 * faulted into the tlb (and thus flushed) anyways.
382 flush_dcache_page_impl(page);
389 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
391 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
392 if (tlb_type == spitfire) {
395 /* This code only runs on Spitfire cpus so this is
396 * why we can assume _PAGE_PADDR_4U.
398 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
399 unsigned long paddr, mask = _PAGE_PADDR_4U;
401 if (kaddr >= PAGE_OFFSET)
402 paddr = kaddr & mask;
404 pgd_t *pgdp = pgd_offset_k(kaddr);
405 pud_t *pudp = pud_offset(pgdp, kaddr);
406 pmd_t *pmdp = pmd_offset(pudp, kaddr);
407 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
409 paddr = pte_val(*ptep) & mask;
411 __flush_icache_page(paddr);
418 unsigned long total = 0, reserved = 0;
419 unsigned long shared = 0, cached = 0;
422 printk(KERN_INFO "Mem-info:\n");
424 printk(KERN_INFO "Free swap: %6ldkB\n",
425 nr_swap_pages << (PAGE_SHIFT-10));
426 for_each_online_pgdat(pgdat) {
427 unsigned long i, flags;
429 pgdat_resize_lock(pgdat, &flags);
430 for (i = 0; i < pgdat->node_spanned_pages; i++) {
431 struct page *page = pgdat_page_nr(pgdat, i);
433 if (PageReserved(page))
435 else if (PageSwapCache(page))
437 else if (page_count(page))
438 shared += page_count(page) - 1;
440 pgdat_resize_unlock(pgdat, &flags);
443 printk(KERN_INFO "%lu pages of RAM\n", total);
444 printk(KERN_INFO "%lu reserved pages\n", reserved);
445 printk(KERN_INFO "%lu pages shared\n", shared);
446 printk(KERN_INFO "%lu pages swap cached\n", cached);
448 printk(KERN_INFO "%lu pages dirty\n",
449 global_page_state(NR_FILE_DIRTY));
450 printk(KERN_INFO "%lu pages writeback\n",
451 global_page_state(NR_WRITEBACK));
452 printk(KERN_INFO "%lu pages mapped\n",
453 global_page_state(NR_FILE_MAPPED));
454 printk(KERN_INFO "%lu pages slab\n",
455 global_page_state(NR_SLAB_RECLAIMABLE) +
456 global_page_state(NR_SLAB_UNRECLAIMABLE));
457 printk(KERN_INFO "%lu pages pagetables\n",
458 global_page_state(NR_PAGETABLE));
461 void mmu_info(struct seq_file *m)
463 if (tlb_type == cheetah)
464 seq_printf(m, "MMU Type\t: Cheetah\n");
465 else if (tlb_type == cheetah_plus)
466 seq_printf(m, "MMU Type\t: Cheetah+\n");
467 else if (tlb_type == spitfire)
468 seq_printf(m, "MMU Type\t: Spitfire\n");
469 else if (tlb_type == hypervisor)
470 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
472 seq_printf(m, "MMU Type\t: ???\n");
474 #ifdef CONFIG_DEBUG_DCFLUSH
475 seq_printf(m, "DCPageFlushes\t: %d\n",
476 atomic_read(&dcpage_flushes));
478 seq_printf(m, "DCPageFlushesXC\t: %d\n",
479 atomic_read(&dcpage_flushes_xcall));
480 #endif /* CONFIG_SMP */
481 #endif /* CONFIG_DEBUG_DCFLUSH */
484 struct linux_prom_translation {
490 /* Exported for kernel TLB miss handling in ktlb.S */
491 struct linux_prom_translation prom_trans[512] __read_mostly;
492 unsigned int prom_trans_ents __read_mostly;
494 /* Exported for SMP bootup purposes. */
495 unsigned long kern_locked_tte_data;
497 /* The obp translations are saved based on 8k pagesize, since obp can
498 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
499 * HI_OBP_ADDRESS range are handled in ktlb.S.
501 static inline int in_obp_range(unsigned long vaddr)
503 return (vaddr >= LOW_OBP_ADDRESS &&
504 vaddr < HI_OBP_ADDRESS);
507 static int cmp_ptrans(const void *a, const void *b)
509 const struct linux_prom_translation *x = a, *y = b;
511 if (x->virt > y->virt)
513 if (x->virt < y->virt)
518 /* Read OBP translations property into 'prom_trans[]'. */
519 static void __init read_obp_translations(void)
521 int n, node, ents, first, last, i;
523 node = prom_finddevice("/virtual-memory");
524 n = prom_getproplen(node, "translations");
525 if (unlikely(n == 0 || n == -1)) {
526 prom_printf("prom_mappings: Couldn't get size.\n");
529 if (unlikely(n > sizeof(prom_trans))) {
530 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
534 if ((n = prom_getproperty(node, "translations",
535 (char *)&prom_trans[0],
536 sizeof(prom_trans))) == -1) {
537 prom_printf("prom_mappings: Couldn't get property.\n");
541 n = n / sizeof(struct linux_prom_translation);
545 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
548 /* Now kick out all the non-OBP entries. */
549 for (i = 0; i < ents; i++) {
550 if (in_obp_range(prom_trans[i].virt))
554 for (; i < ents; i++) {
555 if (!in_obp_range(prom_trans[i].virt))
560 for (i = 0; i < (last - first); i++) {
561 struct linux_prom_translation *src = &prom_trans[i + first];
562 struct linux_prom_translation *dest = &prom_trans[i];
566 for (; i < ents; i++) {
567 struct linux_prom_translation *dest = &prom_trans[i];
568 dest->virt = dest->size = dest->data = 0x0UL;
571 prom_trans_ents = last - first;
573 if (tlb_type == spitfire) {
574 /* Clear diag TTE bits. */
575 for (i = 0; i < prom_trans_ents; i++)
576 prom_trans[i].data &= ~0x0003fe0000000000UL;
580 static void __init hypervisor_tlb_lock(unsigned long vaddr,
584 register unsigned long func asm("%o5");
585 register unsigned long arg0 asm("%o0");
586 register unsigned long arg1 asm("%o1");
587 register unsigned long arg2 asm("%o2");
588 register unsigned long arg3 asm("%o3");
590 func = HV_FAST_MMU_MAP_PERM_ADDR;
595 __asm__ __volatile__("ta 0x80"
596 : "=&r" (func), "=&r" (arg0),
597 "=&r" (arg1), "=&r" (arg2),
599 : "0" (func), "1" (arg0), "2" (arg1),
600 "3" (arg2), "4" (arg3));
602 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
603 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
608 static unsigned long kern_large_tte(unsigned long paddr);
610 static void __init remap_kernel(void)
612 unsigned long phys_page, tte_vaddr, tte_data;
613 int tlb_ent = sparc64_highest_locked_tlbent();
615 tte_vaddr = (unsigned long) KERNBASE;
616 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
617 tte_data = kern_large_tte(phys_page);
619 kern_locked_tte_data = tte_data;
621 /* Now lock us into the TLBs via Hypervisor or OBP. */
622 if (tlb_type == hypervisor) {
623 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
624 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
626 tte_vaddr += 0x400000;
627 tte_data += 0x400000;
628 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
629 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
632 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
633 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
636 prom_dtlb_load(tlb_ent,
638 tte_vaddr + 0x400000);
639 prom_itlb_load(tlb_ent,
641 tte_vaddr + 0x400000);
643 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
645 if (tlb_type == cheetah_plus) {
646 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
647 CTX_CHEETAH_PLUS_NUC);
648 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
649 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
654 static void __init inherit_prom_mappings(void)
656 read_obp_translations();
658 /* Now fixup OBP's idea about where we really are mapped. */
659 prom_printf("Remapping the kernel... ");
661 prom_printf("done.\n");
664 void prom_world(int enter)
667 set_fs((mm_segment_t) { get_thread_current_ds() });
669 __asm__ __volatile__("flushw");
672 #ifdef DCACHE_ALIASING_POSSIBLE
673 void __flush_dcache_range(unsigned long start, unsigned long end)
677 if (tlb_type == spitfire) {
680 for (va = start; va < end; va += 32) {
681 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
685 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
688 for (va = start; va < end; va += 32)
689 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
693 "i" (ASI_DCACHE_INVALIDATE));
696 #endif /* DCACHE_ALIASING_POSSIBLE */
698 /* get_new_mmu_context() uses "cache + 1". */
699 DEFINE_SPINLOCK(ctx_alloc_lock);
700 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
701 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
702 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
703 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
705 /* Caller does TLB context flushing on local CPU if necessary.
706 * The caller also ensures that CTX_VALID(mm->context) is false.
708 * We must be careful about boundary cases so that we never
709 * let the user have CTX 0 (nucleus) or we ever use a CTX
710 * version of zero (and thus NO_CONTEXT would not be caught
711 * by version mis-match tests in mmu_context.h).
713 * Always invoked with interrupts disabled.
715 void get_new_mmu_context(struct mm_struct *mm)
717 unsigned long ctx, new_ctx;
718 unsigned long orig_pgsz_bits;
722 spin_lock_irqsave(&ctx_alloc_lock, flags);
723 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
724 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
725 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
727 if (new_ctx >= (1 << CTX_NR_BITS)) {
728 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
729 if (new_ctx >= ctx) {
731 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
734 new_ctx = CTX_FIRST_VERSION;
736 /* Don't call memset, for 16 entries that's just
739 mmu_context_bmap[0] = 3;
740 mmu_context_bmap[1] = 0;
741 mmu_context_bmap[2] = 0;
742 mmu_context_bmap[3] = 0;
743 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
744 mmu_context_bmap[i + 0] = 0;
745 mmu_context_bmap[i + 1] = 0;
746 mmu_context_bmap[i + 2] = 0;
747 mmu_context_bmap[i + 3] = 0;
753 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
754 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
756 tlb_context_cache = new_ctx;
757 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
758 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
760 if (unlikely(new_version))
761 smp_new_mmu_context_version();
764 /* Find a free area for the bootmem map, avoiding the kernel image
765 * and the initial ramdisk.
767 static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
768 unsigned long end_pfn)
770 unsigned long avoid_start, avoid_end, bootmap_size;
773 bootmap_size = bootmem_bootmap_pages(end_pfn - start_pfn);
774 bootmap_size <<= PAGE_SHIFT;
776 avoid_start = avoid_end = 0;
777 #ifdef CONFIG_BLK_DEV_INITRD
778 avoid_start = initrd_start;
779 avoid_end = PAGE_ALIGN(initrd_end);
782 #ifdef CONFIG_DEBUG_BOOTMEM
783 prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
784 kern_base, PAGE_ALIGN(kern_base + kern_size),
785 avoid_start, avoid_end);
787 for (i = 0; i < pavail_ents; i++) {
788 unsigned long start, end;
790 start = pavail[i].phys_addr;
791 end = start + pavail[i].reg_size;
793 while (start < end) {
794 if (start >= kern_base &&
795 start < PAGE_ALIGN(kern_base + kern_size)) {
796 start = PAGE_ALIGN(kern_base + kern_size);
799 if (start >= avoid_start && start < avoid_end) {
804 if ((end - start) < bootmap_size)
807 if (start < kern_base &&
808 (start + bootmap_size) > kern_base) {
809 start = PAGE_ALIGN(kern_base + kern_size);
813 if (start < avoid_start &&
814 (start + bootmap_size) > avoid_start) {
819 /* OK, it doesn't overlap anything, use it. */
820 #ifdef CONFIG_DEBUG_BOOTMEM
821 prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
822 start >> PAGE_SHIFT, start);
824 return start >> PAGE_SHIFT;
828 prom_printf("Cannot find free area for bootmap, aborting.\n");
832 static void __init trim_pavail(unsigned long *cur_size_p,
833 unsigned long *end_of_phys_p)
835 unsigned long to_trim = *cur_size_p - cmdline_memory_size;
836 unsigned long avoid_start, avoid_end;
839 to_trim = PAGE_ALIGN(to_trim);
841 avoid_start = avoid_end = 0;
842 #ifdef CONFIG_BLK_DEV_INITRD
843 avoid_start = initrd_start;
844 avoid_end = PAGE_ALIGN(initrd_end);
847 /* Trim some pavail[] entries in order to satisfy the
848 * requested "mem=xxx" kernel command line specification.
850 * We must not trim off the kernel image area nor the
851 * initial ramdisk range (if any). Also, we must not trim
852 * any pavail[] entry down to zero in order to preserve
853 * the invariant that all pavail[] entries have a non-zero
854 * size which is assumed by all of the code in here.
856 for (i = 0; i < pavail_ents; i++) {
857 unsigned long start, end, kern_end;
858 unsigned long trim_low, trim_high, n;
860 kern_end = PAGE_ALIGN(kern_base + kern_size);
862 trim_low = start = pavail[i].phys_addr;
863 trim_high = end = start + pavail[i].reg_size;
865 if (kern_base >= start &&
867 trim_low = kern_base;
871 if (kern_end >= start &&
873 trim_high = kern_end;
876 avoid_start >= start &&
878 if (trim_low > avoid_start)
879 trim_low = avoid_start;
880 if (avoid_end >= end)
884 avoid_end >= start &&
886 if (trim_high < avoid_end)
887 trim_high = avoid_end;
890 if (trim_high <= trim_low)
893 if (trim_low == start && trim_high == end) {
894 /* Whole chunk is available for trimming.
895 * Trim all except one page, in order to keep
898 n = (end - start) - PAGE_SIZE;
903 pavail[i].phys_addr += n;
904 pavail[i].reg_size -= n;
908 n = (trim_low - start);
913 pavail[i].phys_addr += n;
914 pavail[i].reg_size -= n;
922 pavail[i].reg_size -= n;
934 for (i = 0; i < pavail_ents; i++) {
935 *end_of_phys_p = pavail[i].phys_addr +
937 *cur_size_p += pavail[i].reg_size;
941 /* About pages_avail, this is the value we will use to calculate
942 * the zholes_size[] argument given to free_area_init_node(). The
943 * page allocator uses this to calculate nr_kernel_pages,
944 * nr_all_pages and zone->present_pages. On NUMA it is used
945 * to calculate zone->min_unmapped_pages and zone->min_slab_pages.
947 * So this number should really be set to what the page allocator
948 * actually ends up with. This means:
949 * 1) It should include bootmem map pages, we'll release those.
950 * 2) It should not include the kernel image, except for the
951 * __init sections which we will also release.
952 * 3) It should include the initrd image, since we'll release
955 static unsigned long __init bootmem_init(unsigned long *pages_avail,
956 unsigned long phys_base)
958 unsigned long bootmap_size, end_pfn;
959 unsigned long end_of_phys_memory = 0UL;
960 unsigned long bootmap_pfn, bytes_avail, size;
963 #ifdef CONFIG_DEBUG_BOOTMEM
964 prom_printf("bootmem_init: Scan pavail, ");
968 for (i = 0; i < pavail_ents; i++) {
969 end_of_phys_memory = pavail[i].phys_addr +
971 bytes_avail += pavail[i].reg_size;
974 /* Determine the location of the initial ramdisk before trying
975 * to honor the "mem=xxx" command line argument. We must know
976 * where the kernel image and the ramdisk image are so that we
977 * do not trim those two areas from the physical memory map.
980 #ifdef CONFIG_BLK_DEV_INITRD
981 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
982 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
983 unsigned long ramdisk_image = sparc_ramdisk_image ?
984 sparc_ramdisk_image : sparc_ramdisk_image64;
985 ramdisk_image -= KERNBASE;
986 initrd_start = ramdisk_image + phys_base;
987 initrd_end = initrd_start + sparc_ramdisk_size;
988 if (initrd_end > end_of_phys_memory) {
989 printk(KERN_CRIT "initrd extends beyond end of memory "
990 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
991 initrd_end, end_of_phys_memory);
998 if (cmdline_memory_size &&
999 bytes_avail > cmdline_memory_size)
1000 trim_pavail(&bytes_avail,
1001 &end_of_phys_memory);
1003 *pages_avail = bytes_avail >> PAGE_SHIFT;
1005 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1007 /* Initialize the boot-time allocator. */
1008 max_pfn = max_low_pfn = end_pfn;
1009 min_low_pfn = (phys_base >> PAGE_SHIFT);
1011 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
1013 #ifdef CONFIG_DEBUG_BOOTMEM
1014 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1015 min_low_pfn, bootmap_pfn, max_low_pfn);
1017 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
1018 min_low_pfn, end_pfn);
1020 /* Now register the available physical memory with the
1023 for (i = 0; i < pavail_ents; i++) {
1024 #ifdef CONFIG_DEBUG_BOOTMEM
1025 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
1026 i, pavail[i].phys_addr, pavail[i].reg_size);
1028 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1031 #ifdef CONFIG_BLK_DEV_INITRD
1033 size = initrd_end - initrd_start;
1035 /* Resert the initrd image area. */
1036 #ifdef CONFIG_DEBUG_BOOTMEM
1037 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1038 initrd_start, initrd_end);
1040 reserve_bootmem(initrd_start, size);
1042 initrd_start += PAGE_OFFSET;
1043 initrd_end += PAGE_OFFSET;
1046 /* Reserve the kernel text/data/bss. */
1047 #ifdef CONFIG_DEBUG_BOOTMEM
1048 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1050 reserve_bootmem(kern_base, kern_size);
1051 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1053 /* Add back in the initmem pages. */
1054 size = ((unsigned long)(__init_end) & PAGE_MASK) -
1055 PAGE_ALIGN((unsigned long)__init_begin);
1056 *pages_avail += size >> PAGE_SHIFT;
1058 /* Reserve the bootmem map. We do not account for it
1059 * in pages_avail because we will release that memory
1060 * in free_all_bootmem.
1062 size = bootmap_size;
1063 #ifdef CONFIG_DEBUG_BOOTMEM
1064 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1065 (bootmap_pfn << PAGE_SHIFT), size);
1067 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1069 for (i = 0; i < pavail_ents; i++) {
1070 unsigned long start_pfn, end_pfn;
1072 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
1073 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
1074 #ifdef CONFIG_DEBUG_BOOTMEM
1075 prom_printf("memory_present(0, %lx, %lx)\n",
1076 start_pfn, end_pfn);
1078 memory_present(0, start_pfn, end_pfn);
1086 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1087 static int pall_ents __initdata;
1089 #ifdef CONFIG_DEBUG_PAGEALLOC
1090 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1092 unsigned long vstart = PAGE_OFFSET + pstart;
1093 unsigned long vend = PAGE_OFFSET + pend;
1094 unsigned long alloc_bytes = 0UL;
1096 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1097 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1102 while (vstart < vend) {
1103 unsigned long this_end, paddr = __pa(vstart);
1104 pgd_t *pgd = pgd_offset_k(vstart);
1109 pud = pud_offset(pgd, vstart);
1110 if (pud_none(*pud)) {
1113 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1114 alloc_bytes += PAGE_SIZE;
1115 pud_populate(&init_mm, pud, new);
1118 pmd = pmd_offset(pud, vstart);
1119 if (!pmd_present(*pmd)) {
1122 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1123 alloc_bytes += PAGE_SIZE;
1124 pmd_populate_kernel(&init_mm, pmd, new);
1127 pte = pte_offset_kernel(pmd, vstart);
1128 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1129 if (this_end > vend)
1132 while (vstart < this_end) {
1133 pte_val(*pte) = (paddr | pgprot_val(prot));
1135 vstart += PAGE_SIZE;
1144 extern unsigned int kvmap_linear_patch[1];
1145 #endif /* CONFIG_DEBUG_PAGEALLOC */
1147 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1149 const unsigned long shift_256MB = 28;
1150 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1151 const unsigned long size_256MB = (1UL << shift_256MB);
1153 while (start < end) {
1156 remains = end - start;
1157 if (remains < size_256MB)
1160 if (start & mask_256MB) {
1161 start = (start + size_256MB) & ~mask_256MB;
1165 while (remains >= size_256MB) {
1166 unsigned long index = start >> shift_256MB;
1168 __set_bit(index, kpte_linear_bitmap);
1170 start += size_256MB;
1171 remains -= size_256MB;
1176 static void __init kernel_physical_mapping_init(void)
1179 #ifdef CONFIG_DEBUG_PAGEALLOC
1180 unsigned long mem_alloced = 0UL;
1183 read_obp_memory("reg", &pall[0], &pall_ents);
1185 for (i = 0; i < pall_ents; i++) {
1186 unsigned long phys_start, phys_end;
1188 phys_start = pall[i].phys_addr;
1189 phys_end = phys_start + pall[i].reg_size;
1191 mark_kpte_bitmap(phys_start, phys_end);
1193 #ifdef CONFIG_DEBUG_PAGEALLOC
1194 mem_alloced += kernel_map_range(phys_start, phys_end,
1199 #ifdef CONFIG_DEBUG_PAGEALLOC
1200 printk("Allocated %ld bytes for kernel page tables.\n",
1203 kvmap_linear_patch[0] = 0x01000000; /* nop */
1204 flushi(&kvmap_linear_patch[0]);
1210 #ifdef CONFIG_DEBUG_PAGEALLOC
1211 void kernel_map_pages(struct page *page, int numpages, int enable)
1213 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1214 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1216 kernel_map_range(phys_start, phys_end,
1217 (enable ? PAGE_KERNEL : __pgprot(0)));
1219 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1220 PAGE_OFFSET + phys_end);
1222 /* we should perform an IPI and flush all tlbs,
1223 * but that can deadlock->flush only current cpu.
1225 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1226 PAGE_OFFSET + phys_end);
1230 unsigned long __init find_ecache_flush_span(unsigned long size)
1234 for (i = 0; i < pavail_ents; i++) {
1235 if (pavail[i].reg_size >= size)
1236 return pavail[i].phys_addr;
1242 static void __init tsb_phys_patch(void)
1244 struct tsb_ldquad_phys_patch_entry *pquad;
1245 struct tsb_phys_patch_entry *p;
1247 pquad = &__tsb_ldquad_phys_patch;
1248 while (pquad < &__tsb_ldquad_phys_patch_end) {
1249 unsigned long addr = pquad->addr;
1251 if (tlb_type == hypervisor)
1252 *(unsigned int *) addr = pquad->sun4v_insn;
1254 *(unsigned int *) addr = pquad->sun4u_insn;
1256 __asm__ __volatile__("flush %0"
1263 p = &__tsb_phys_patch;
1264 while (p < &__tsb_phys_patch_end) {
1265 unsigned long addr = p->addr;
1267 *(unsigned int *) addr = p->insn;
1269 __asm__ __volatile__("flush %0"
1277 /* Don't mark as init, we give this to the Hypervisor. */
1278 #ifndef CONFIG_DEBUG_PAGEALLOC
1279 #define NUM_KTSB_DESCR 2
1281 #define NUM_KTSB_DESCR 1
1283 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1284 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1286 static void __init sun4v_ktsb_init(void)
1288 unsigned long ktsb_pa;
1290 /* First KTSB for PAGE_SIZE mappings. */
1291 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1293 switch (PAGE_SIZE) {
1296 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1297 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1301 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1302 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1306 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1307 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1310 case 4 * 1024 * 1024:
1311 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1312 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1316 ktsb_descr[0].assoc = 1;
1317 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1318 ktsb_descr[0].ctx_idx = 0;
1319 ktsb_descr[0].tsb_base = ktsb_pa;
1320 ktsb_descr[0].resv = 0;
1322 #ifndef CONFIG_DEBUG_PAGEALLOC
1323 /* Second KTSB for 4MB/256MB mappings. */
1324 ktsb_pa = (kern_base +
1325 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1327 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1328 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1329 HV_PGSZ_MASK_256MB);
1330 ktsb_descr[1].assoc = 1;
1331 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1332 ktsb_descr[1].ctx_idx = 0;
1333 ktsb_descr[1].tsb_base = ktsb_pa;
1334 ktsb_descr[1].resv = 0;
1338 void __cpuinit sun4v_ktsb_register(void)
1340 register unsigned long func asm("%o5");
1341 register unsigned long arg0 asm("%o0");
1342 register unsigned long arg1 asm("%o1");
1345 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1347 func = HV_FAST_MMU_TSB_CTX0;
1348 arg0 = NUM_KTSB_DESCR;
1350 __asm__ __volatile__("ta %6"
1351 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1352 : "0" (func), "1" (arg0), "2" (arg1),
1353 "i" (HV_FAST_TRAP));
1356 /* paging_init() sets up the page tables */
1358 extern void cheetah_ecache_flush_init(void);
1359 extern void sun4v_patch_tlb_handlers(void);
1361 static unsigned long last_valid_pfn;
1362 pgd_t swapper_pg_dir[2048];
1364 static void sun4u_pgprot_init(void);
1365 static void sun4v_pgprot_init(void);
1367 void __init paging_init(void)
1369 unsigned long end_pfn, pages_avail, shift, phys_base;
1370 unsigned long real_end, i;
1372 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1373 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1375 /* Invalidate both kernel TSBs. */
1376 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1377 #ifndef CONFIG_DEBUG_PAGEALLOC
1378 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1381 if (tlb_type == hypervisor)
1382 sun4v_pgprot_init();
1384 sun4u_pgprot_init();
1386 if (tlb_type == cheetah_plus ||
1387 tlb_type == hypervisor)
1390 if (tlb_type == hypervisor) {
1391 sun4v_patch_tlb_handlers();
1395 /* Find available physical memory... */
1396 read_obp_memory("available", &pavail[0], &pavail_ents);
1398 phys_base = 0xffffffffffffffffUL;
1399 for (i = 0; i < pavail_ents; i++)
1400 phys_base = min(phys_base, pavail[i].phys_addr);
1402 set_bit(0, mmu_context_bmap);
1404 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1406 real_end = (unsigned long)_end;
1407 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1409 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1410 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1414 /* Set kernel pgd to upper alias so physical page computations
1417 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1419 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1421 /* Now can init the kernel/bad page tables. */
1422 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1423 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1425 inherit_prom_mappings();
1427 /* Ok, we can use our TLB miss and window trap handlers safely. */
1432 if (tlb_type == hypervisor)
1433 sun4v_ktsb_register();
1435 /* Setup bootmem... */
1437 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1439 max_mapnr = last_valid_pfn;
1441 kernel_physical_mapping_init();
1443 prom_build_devicetree();
1446 unsigned long zones_size[MAX_NR_ZONES];
1447 unsigned long zholes_size[MAX_NR_ZONES];
1450 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1451 zones_size[znum] = zholes_size[znum] = 0;
1453 zones_size[ZONE_NORMAL] = end_pfn;
1454 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1456 free_area_init_node(0, &contig_page_data, zones_size,
1457 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1464 static void __init taint_real_pages(void)
1468 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1470 /* Find changes discovered in the physmem available rescan and
1471 * reserve the lost portions in the bootmem maps.
1473 for (i = 0; i < pavail_ents; i++) {
1474 unsigned long old_start, old_end;
1476 old_start = pavail[i].phys_addr;
1477 old_end = old_start +
1479 while (old_start < old_end) {
1482 for (n = 0; n < pavail_rescan_ents; n++) {
1483 unsigned long new_start, new_end;
1485 new_start = pavail_rescan[n].phys_addr;
1486 new_end = new_start +
1487 pavail_rescan[n].reg_size;
1489 if (new_start <= old_start &&
1490 new_end >= (old_start + PAGE_SIZE)) {
1491 set_bit(old_start >> 22,
1492 sparc64_valid_addr_bitmap);
1496 reserve_bootmem(old_start, PAGE_SIZE);
1499 old_start += PAGE_SIZE;
1504 int __init page_in_phys_avail(unsigned long paddr)
1510 for (i = 0; i < pavail_rescan_ents; i++) {
1511 unsigned long start, end;
1513 start = pavail_rescan[i].phys_addr;
1514 end = start + pavail_rescan[i].reg_size;
1516 if (paddr >= start && paddr < end)
1519 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1521 #ifdef CONFIG_BLK_DEV_INITRD
1522 if (paddr >= __pa(initrd_start) &&
1523 paddr < __pa(PAGE_ALIGN(initrd_end)))
1530 void __init mem_init(void)
1532 unsigned long codepages, datapages, initpages;
1533 unsigned long addr, last;
1536 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1538 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1539 if (sparc64_valid_addr_bitmap == NULL) {
1540 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1543 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1545 addr = PAGE_OFFSET + kern_base;
1546 last = PAGE_ALIGN(kern_size) + addr;
1547 while (addr < last) {
1548 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1554 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1556 #ifdef CONFIG_DEBUG_BOOTMEM
1557 prom_printf("mem_init: Calling free_all_bootmem().\n");
1560 /* We subtract one to account for the mem_map_zero page
1563 totalram_pages = num_physpages = free_all_bootmem() - 1;
1566 * Set up the zero page, mark it reserved, so that page count
1567 * is not manipulated when freeing the page from user ptes.
1569 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1570 if (mem_map_zero == NULL) {
1571 prom_printf("paging_init: Cannot alloc zero page.\n");
1574 SetPageReserved(mem_map_zero);
1576 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1577 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1578 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1579 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1580 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1581 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1583 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1584 nr_free_pages() << (PAGE_SHIFT-10),
1585 codepages << (PAGE_SHIFT-10),
1586 datapages << (PAGE_SHIFT-10),
1587 initpages << (PAGE_SHIFT-10),
1588 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1590 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1591 cheetah_ecache_flush_init();
1594 void free_initmem(void)
1596 unsigned long addr, initend;
1599 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1601 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1602 initend = (unsigned long)(__init_end) & PAGE_MASK;
1603 for (; addr < initend; addr += PAGE_SIZE) {
1608 ((unsigned long) __va(kern_base)) -
1609 ((unsigned long) KERNBASE));
1610 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1611 p = virt_to_page(page);
1613 ClearPageReserved(p);
1621 #ifdef CONFIG_BLK_DEV_INITRD
1622 void free_initrd_mem(unsigned long start, unsigned long end)
1625 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1626 for (; start < end; start += PAGE_SIZE) {
1627 struct page *p = virt_to_page(start);
1629 ClearPageReserved(p);
1638 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1639 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1640 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1641 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1642 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1643 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1645 pgprot_t PAGE_KERNEL __read_mostly;
1646 EXPORT_SYMBOL(PAGE_KERNEL);
1648 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1649 pgprot_t PAGE_COPY __read_mostly;
1651 pgprot_t PAGE_SHARED __read_mostly;
1652 EXPORT_SYMBOL(PAGE_SHARED);
1654 pgprot_t PAGE_EXEC __read_mostly;
1655 unsigned long pg_iobits __read_mostly;
1657 unsigned long _PAGE_IE __read_mostly;
1658 EXPORT_SYMBOL(_PAGE_IE);
1660 unsigned long _PAGE_E __read_mostly;
1661 EXPORT_SYMBOL(_PAGE_E);
1663 unsigned long _PAGE_CACHE __read_mostly;
1664 EXPORT_SYMBOL(_PAGE_CACHE);
1666 static void prot_init_common(unsigned long page_none,
1667 unsigned long page_shared,
1668 unsigned long page_copy,
1669 unsigned long page_readonly,
1670 unsigned long page_exec_bit)
1672 PAGE_COPY = __pgprot(page_copy);
1673 PAGE_SHARED = __pgprot(page_shared);
1675 protection_map[0x0] = __pgprot(page_none);
1676 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1677 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1678 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1679 protection_map[0x4] = __pgprot(page_readonly);
1680 protection_map[0x5] = __pgprot(page_readonly);
1681 protection_map[0x6] = __pgprot(page_copy);
1682 protection_map[0x7] = __pgprot(page_copy);
1683 protection_map[0x8] = __pgprot(page_none);
1684 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1685 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1686 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1687 protection_map[0xc] = __pgprot(page_readonly);
1688 protection_map[0xd] = __pgprot(page_readonly);
1689 protection_map[0xe] = __pgprot(page_shared);
1690 protection_map[0xf] = __pgprot(page_shared);
1693 static void __init sun4u_pgprot_init(void)
1695 unsigned long page_none, page_shared, page_copy, page_readonly;
1696 unsigned long page_exec_bit;
1698 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1699 _PAGE_CACHE_4U | _PAGE_P_4U |
1700 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1702 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1703 _PAGE_CACHE_4U | _PAGE_P_4U |
1704 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1705 _PAGE_EXEC_4U | _PAGE_L_4U);
1706 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1708 _PAGE_IE = _PAGE_IE_4U;
1709 _PAGE_E = _PAGE_E_4U;
1710 _PAGE_CACHE = _PAGE_CACHE_4U;
1712 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1713 __ACCESS_BITS_4U | _PAGE_E_4U);
1715 #ifdef CONFIG_DEBUG_PAGEALLOC
1716 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1719 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1722 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1723 _PAGE_P_4U | _PAGE_W_4U);
1725 /* XXX Should use 256MB on Panther. XXX */
1726 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1728 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1729 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1730 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1731 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1734 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1735 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1736 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1737 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1738 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1739 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1740 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1742 page_exec_bit = _PAGE_EXEC_4U;
1744 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1748 static void __init sun4v_pgprot_init(void)
1750 unsigned long page_none, page_shared, page_copy, page_readonly;
1751 unsigned long page_exec_bit;
1753 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1754 _PAGE_CACHE_4V | _PAGE_P_4V |
1755 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1757 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1758 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1760 _PAGE_IE = _PAGE_IE_4V;
1761 _PAGE_E = _PAGE_E_4V;
1762 _PAGE_CACHE = _PAGE_CACHE_4V;
1764 #ifdef CONFIG_DEBUG_PAGEALLOC
1765 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1768 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1771 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1772 _PAGE_P_4V | _PAGE_W_4V);
1774 #ifdef CONFIG_DEBUG_PAGEALLOC
1775 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1778 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1781 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1782 _PAGE_P_4V | _PAGE_W_4V);
1784 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1785 __ACCESS_BITS_4V | _PAGE_E_4V);
1787 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1788 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1789 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1790 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1791 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1793 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1794 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1795 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1796 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1797 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1798 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1799 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1801 page_exec_bit = _PAGE_EXEC_4V;
1803 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1807 unsigned long pte_sz_bits(unsigned long sz)
1809 if (tlb_type == hypervisor) {
1813 return _PAGE_SZ8K_4V;
1815 return _PAGE_SZ64K_4V;
1817 return _PAGE_SZ512K_4V;
1818 case 4 * 1024 * 1024:
1819 return _PAGE_SZ4MB_4V;
1825 return _PAGE_SZ8K_4U;
1827 return _PAGE_SZ64K_4U;
1829 return _PAGE_SZ512K_4U;
1830 case 4 * 1024 * 1024:
1831 return _PAGE_SZ4MB_4U;
1836 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1840 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1841 pte_val(pte) |= (((unsigned long)space) << 32);
1842 pte_val(pte) |= pte_sz_bits(page_size);
1847 static unsigned long kern_large_tte(unsigned long paddr)
1851 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1852 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1853 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1854 if (tlb_type == hypervisor)
1855 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1856 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1857 _PAGE_EXEC_4V | _PAGE_W_4V);
1862 /* If not locked, zap it. */
1863 void __flush_tlb_all(void)
1865 unsigned long pstate;
1868 __asm__ __volatile__("flushw\n\t"
1869 "rdpr %%pstate, %0\n\t"
1870 "wrpr %0, %1, %%pstate"
1873 if (tlb_type == spitfire) {
1874 for (i = 0; i < 64; i++) {
1875 /* Spitfire Errata #32 workaround */
1876 /* NOTE: Always runs on spitfire, so no
1877 * cheetah+ page size encodings.
1879 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1883 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1885 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1886 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1889 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1890 spitfire_put_dtlb_data(i, 0x0UL);
1893 /* Spitfire Errata #32 workaround */
1894 /* NOTE: Always runs on spitfire, so no
1895 * cheetah+ page size encodings.
1897 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1901 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1903 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1904 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1907 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1908 spitfire_put_itlb_data(i, 0x0UL);
1911 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1912 cheetah_flush_dtlb_all();
1913 cheetah_flush_itlb_all();
1915 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1919 #ifdef CONFIG_MEMORY_HOTPLUG
1921 void online_page(struct page *page)
1923 ClearPageReserved(page);
1924 init_page_count(page);
1930 int remove_memory(u64 start, u64 size)
1935 #endif /* CONFIG_MEMORY_HOTPLUG */