1 /* arch/sparc64/mm/tsb.c
3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net>
6 #include <linux/kernel.h>
7 #include <asm/system.h>
9 #include <asm/tlbflush.h>
11 #include <asm/mmu_context.h>
12 #include <asm/pgtable.h>
15 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
17 static inline unsigned long tsb_hash(unsigned long vaddr, unsigned long nentries)
20 return vaddr & (nentries - 1);
23 static inline int tag_compare(unsigned long tag, unsigned long vaddr, unsigned long context)
25 return (tag == ((vaddr >> 22) | (context << 48)));
28 /* TSB flushes need only occur on the processor initiating the address
29 * space modification, not on each cpu the address space has run on.
30 * Only the TLB flush needs that treatment.
33 void flush_tsb_kernel_range(unsigned long start, unsigned long end)
37 for (v = start; v < end; v += PAGE_SIZE) {
38 unsigned long hash = tsb_hash(v, KERNEL_TSB_NENTRIES);
39 struct tsb *ent = &swapper_tsb[hash];
41 if (tag_compare(ent->tag, v, 0)) {
43 membar_storeload_storestore();
48 void flush_tsb_user(struct mmu_gather *mp)
50 struct mm_struct *mm = mp->mm;
51 struct tsb *tsb = mm->context.tsb;
52 unsigned long nentries = mm->context.tsb_nentries;
53 unsigned long ctx, base;
56 if (unlikely(!CTX_VALID(mm->context)))
59 ctx = CTX_HWBITS(mm->context);
61 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
64 base = (unsigned long) tsb;
66 for (i = 0; i < mp->tlb_nr; i++) {
67 unsigned long v = mp->vaddrs[i];
68 unsigned long tag, ent, hash;
72 hash = tsb_hash(v, nentries);
73 ent = base + (hash * sizeof(struct tsb));
74 tag = (v >> 22UL) | (ctx << 48UL);
80 static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_bytes)
82 unsigned long tsb_reg, base, tsb_paddr;
83 unsigned long page_sz, tte;
85 mm->context.tsb_nentries = tsb_bytes / sizeof(struct tsb);
88 tte = pgprot_val(PAGE_KERNEL_LOCKED);
89 tsb_paddr = __pa(mm->context.tsb);
90 BUG_ON(tsb_paddr & (tsb_bytes - 1UL));
92 /* Use the smallest page size that can map the whole TSB
98 #ifdef DCACHE_ALIASING_POSSIBLE
99 base += (tsb_paddr & 8192);
121 page_sz = 512 * 1024;
126 page_sz = 512 * 1024;
131 page_sz = 512 * 1024;
136 page_sz = 4 * 1024 * 1024;
142 tte |= pte_sz_bits(page_sz);
144 if (tlb_type == cheetah_plus || tlb_type == hypervisor) {
145 /* Physical mapping, no locked TLB entry for TSB. */
146 tsb_reg |= tsb_paddr;
148 mm->context.tsb_reg_val = tsb_reg;
149 mm->context.tsb_map_vaddr = 0;
150 mm->context.tsb_map_pte = 0;
153 tsb_reg |= (tsb_paddr & (page_sz - 1UL));
154 tte |= (tsb_paddr & ~(page_sz - 1UL));
156 mm->context.tsb_reg_val = tsb_reg;
157 mm->context.tsb_map_vaddr = base;
158 mm->context.tsb_map_pte = tte;
161 /* Setup the Hypervisor TSB descriptor. */
162 if (tlb_type == hypervisor) {
163 struct hv_tsb_descr *hp = &mm->context.tsb_descr;
168 hp->pgsz_idx = HV_PGSZ_IDX_8K;
172 hp->pgsz_idx = HV_PGSZ_IDX_64K;
176 hp->pgsz_idx = HV_PGSZ_IDX_512K;
179 case 4 * 1024 * 1024:
180 hp->pgsz_idx = HV_PGSZ_IDX_4MB;
184 hp->num_ttes = tsb_bytes / 16;
189 hp->pgsz_mask = HV_PGSZ_MASK_8K;
193 hp->pgsz_mask = HV_PGSZ_MASK_64K;
197 hp->pgsz_mask = HV_PGSZ_MASK_512K;
200 case 4 * 1024 * 1024:
201 hp->pgsz_mask = HV_PGSZ_MASK_4MB;
204 hp->tsb_base = tsb_paddr;
209 /* The page tables are locked against modifications while this
212 * XXX do some prefetching...
214 static void copy_tsb(struct tsb *old_tsb, unsigned long old_size,
215 struct tsb *new_tsb, unsigned long new_size)
217 unsigned long old_nentries = old_size / sizeof(struct tsb);
218 unsigned long new_nentries = new_size / sizeof(struct tsb);
221 for (i = 0; i < old_nentries; i++) {
222 register unsigned long tag asm("o4");
223 register unsigned long pte asm("o5");
224 unsigned long v, hash;
226 if (tlb_type == hypervisor) {
227 __asm__ __volatile__(
229 : "=r" (tag), "=r" (pte)
230 : "r" (__pa(&old_tsb[i])),
231 "i" (ASI_QUAD_LDD_PHYS_4V));
232 } else if (tlb_type == cheetah_plus) {
233 __asm__ __volatile__(
235 : "=r" (tag), "=r" (pte)
236 : "r" (__pa(&old_tsb[i])),
237 "i" (ASI_QUAD_LDD_PHYS));
239 __asm__ __volatile__(
241 : "=r" (tag), "=r" (pte)
243 "i" (ASI_NUCLEUS_QUAD_LDD));
246 if (!tag || (tag & (1UL << TSB_TAG_LOCK_BIT)))
249 /* We only put base page size PTEs into the TSB,
250 * but that might change in the future. This code
251 * would need to be changed if we start putting larger
252 * page size PTEs into there.
254 WARN_ON((pte & _PAGE_ALL_SZ_BITS) != _PAGE_SZBITS);
256 /* The tag holds bits 22 to 63 of the virtual address
257 * and the context. Clear out the context, and shift
258 * up to make a virtual address.
260 v = (tag & ((1UL << 42UL) - 1UL)) << 22UL;
262 /* The implied bits of the tag (bits 13 to 21) are
263 * determined by the TSB entry index, so fill that in.
265 v |= (i & (512UL - 1UL)) << 13UL;
267 hash = tsb_hash(v, new_nentries);
268 if (tlb_type == cheetah_plus ||
269 tlb_type == hypervisor) {
270 __asm__ __volatile__(
271 "stxa %0, [%1] %2\n\t"
275 "r" (__pa(&new_tsb[hash].tag)),
276 "i" (ASI_PHYS_USE_EC),
278 "r" (__pa(&new_tsb[hash].pte)));
280 new_tsb[hash].tag = tag;
281 new_tsb[hash].pte = pte;
286 /* When the RSS of an address space exceeds mm->context.tsb_rss_limit,
287 * update_mmu_cache() invokes this routine to try and grow the TSB.
288 * When we reach the maximum TSB size supported, we stick ~0UL into
289 * mm->context.tsb_rss_limit so the grow checks in update_mmu_cache()
290 * will not trigger any longer.
292 * The TSB can be anywhere from 8K to 1MB in size, in increasing powers
293 * of two. The TSB must be aligned to it's size, so f.e. a 512K TSB
294 * must be 512K aligned.
296 * The idea here is to grow the TSB when the RSS of the process approaches
297 * the number of entries that the current TSB can hold at once. Currently,
298 * we trigger when the RSS hits 3/4 of the TSB capacity.
300 void tsb_grow(struct mm_struct *mm, unsigned long rss, gfp_t gfp_flags)
302 unsigned long max_tsb_size = 1 * 1024 * 1024;
303 unsigned long size, old_size;
307 if (max_tsb_size > (PAGE_SIZE << MAX_ORDER))
308 max_tsb_size = (PAGE_SIZE << MAX_ORDER);
310 for (size = PAGE_SIZE; size < max_tsb_size; size <<= 1UL) {
311 unsigned long n_entries = size / sizeof(struct tsb);
313 n_entries = (n_entries * 3) / 4;
318 page = alloc_pages(gfp_flags | __GFP_ZERO, get_order(size));
322 if (size == max_tsb_size)
323 mm->context.tsb_rss_limit = ~0UL;
325 mm->context.tsb_rss_limit =
326 ((size / sizeof(struct tsb)) * 3) / 4;
328 old_tsb = mm->context.tsb;
329 old_size = mm->context.tsb_nentries * sizeof(struct tsb);
332 copy_tsb(old_tsb, old_size, page_address(page), size);
334 mm->context.tsb = page_address(page);
335 setup_tsb_params(mm, size);
337 /* If old_tsb is NULL, we're being invoked for the first time
338 * from init_new_context().
341 /* Now force all other processors to reload the new
346 /* Finally reload it on the local cpu. No further
347 * references will remain to the old TSB and we can
350 tsb_context_switch(mm);
352 free_pages((unsigned long) old_tsb, get_order(old_size));
356 int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
359 mm->context.sparc64_ctx_val = 0UL;
361 /* copy_mm() copies over the parent's mm_struct before calling
362 * us, so we need to zero out the TSB pointer or else tsb_grow()
363 * will be confused and think there is an older TSB to free up.
365 mm->context.tsb = NULL;
366 tsb_grow(mm, 0, GFP_KERNEL);
368 if (unlikely(!mm->context.tsb))
374 void destroy_context(struct mm_struct *mm)
376 unsigned long size = mm->context.tsb_nentries * sizeof(struct tsb);
378 free_pages((unsigned long) mm->context.tsb, get_order(size));
380 /* We can remove these later, but for now it's useful
381 * to catch any bogus post-destroy_context() references
384 mm->context.tsb = NULL;
385 mm->context.tsb_reg_val = 0UL;
387 spin_lock(&ctx_alloc_lock);
389 if (CTX_VALID(mm->context)) {
390 unsigned long nr = CTX_NRBITS(mm->context);
391 mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63));
394 spin_unlock(&ctx_alloc_lock);