2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/iommu-helper.h>
26 #ifdef CONFIG_IOMMU_API
27 #include <linux/iommu.h>
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
45 #ifdef CONFIG_IOMMU_API
46 static struct iommu_ops amd_iommu_ops;
50 * general struct to manage commands send to an IOMMU
56 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
57 struct unity_map_entry *e);
58 static struct dma_ops_domain *find_protection_domain(u16 devid);
61 #ifdef CONFIG_AMD_IOMMU_STATS
64 * Initialization code for statistics collection
67 DECLARE_STATS_COUNTER(compl_wait);
68 DECLARE_STATS_COUNTER(cnt_map_single);
69 DECLARE_STATS_COUNTER(cnt_unmap_single);
71 static struct dentry *stats_dir;
72 static struct dentry *de_isolate;
73 static struct dentry *de_fflush;
75 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
77 if (stats_dir == NULL)
80 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
84 static void amd_iommu_stats_init(void)
86 stats_dir = debugfs_create_dir("amd-iommu", NULL);
87 if (stats_dir == NULL)
90 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
91 (u32 *)&amd_iommu_isolate);
93 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
94 (u32 *)&amd_iommu_unmap_flush);
96 amd_iommu_stats_add(&compl_wait);
97 amd_iommu_stats_add(&cnt_map_single);
98 amd_iommu_stats_add(&cnt_unmap_single);
103 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
104 static int iommu_has_npcache(struct amd_iommu *iommu)
106 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
109 /****************************************************************************
111 * Interrupt handling functions
113 ****************************************************************************/
115 static void iommu_print_event(void *__evt)
118 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
119 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
120 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
121 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
122 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
124 printk(KERN_ERR "AMD IOMMU: Event logged [");
127 case EVENT_TYPE_ILL_DEV:
128 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
129 "address=0x%016llx flags=0x%04x]\n",
130 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
133 case EVENT_TYPE_IO_FAULT:
134 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
135 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
136 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
137 domid, address, flags);
139 case EVENT_TYPE_DEV_TAB_ERR:
140 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
141 "address=0x%016llx flags=0x%04x]\n",
142 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
145 case EVENT_TYPE_PAGE_TAB_ERR:
146 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
147 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
148 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
149 domid, address, flags);
151 case EVENT_TYPE_ILL_CMD:
152 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
154 case EVENT_TYPE_CMD_HARD_ERR:
155 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
156 "flags=0x%04x]\n", address, flags);
158 case EVENT_TYPE_IOTLB_INV_TO:
159 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
160 "address=0x%016llx]\n",
161 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
164 case EVENT_TYPE_INV_DEV_REQ:
165 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
166 "address=0x%016llx flags=0x%04x]\n",
167 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
171 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
175 static void iommu_poll_events(struct amd_iommu *iommu)
180 spin_lock_irqsave(&iommu->lock, flags);
182 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
183 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
185 while (head != tail) {
186 iommu_print_event(iommu->evt_buf + head);
187 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
190 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
192 spin_unlock_irqrestore(&iommu->lock, flags);
195 irqreturn_t amd_iommu_int_handler(int irq, void *data)
197 struct amd_iommu *iommu;
199 list_for_each_entry(iommu, &amd_iommu_list, list)
200 iommu_poll_events(iommu);
205 /****************************************************************************
207 * IOMMU command queuing functions
209 ****************************************************************************/
212 * Writes the command to the IOMMUs command buffer and informs the
213 * hardware about the new command. Must be called with iommu->lock held.
215 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
220 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
221 target = iommu->cmd_buf + tail;
222 memcpy_toio(target, cmd, sizeof(*cmd));
223 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
224 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
227 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
233 * General queuing function for commands. Takes iommu->lock and calls
234 * __iommu_queue_command().
236 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
241 spin_lock_irqsave(&iommu->lock, flags);
242 ret = __iommu_queue_command(iommu, cmd);
244 iommu->need_sync = true;
245 spin_unlock_irqrestore(&iommu->lock, flags);
251 * This function waits until an IOMMU has completed a completion
254 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
260 INC_STATS_COUNTER(compl_wait);
262 while (!ready && (i < EXIT_LOOP_COUNT)) {
264 /* wait for the bit to become one */
265 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
266 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
269 /* set bit back to zero */
270 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
271 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
273 if (unlikely(i == EXIT_LOOP_COUNT))
274 panic("AMD IOMMU: Completion wait loop failed\n");
278 * This function queues a completion wait command into the command
281 static int __iommu_completion_wait(struct amd_iommu *iommu)
283 struct iommu_cmd cmd;
285 memset(&cmd, 0, sizeof(cmd));
286 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
287 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
289 return __iommu_queue_command(iommu, &cmd);
293 * This function is called whenever we need to ensure that the IOMMU has
294 * completed execution of all commands we sent. It sends a
295 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
296 * us about that by writing a value to a physical address we pass with
299 static int iommu_completion_wait(struct amd_iommu *iommu)
304 spin_lock_irqsave(&iommu->lock, flags);
306 if (!iommu->need_sync)
309 ret = __iommu_completion_wait(iommu);
311 iommu->need_sync = false;
316 __iommu_wait_for_completion(iommu);
319 spin_unlock_irqrestore(&iommu->lock, flags);
325 * Command send function for invalidating a device table entry
327 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
329 struct iommu_cmd cmd;
332 BUG_ON(iommu == NULL);
334 memset(&cmd, 0, sizeof(cmd));
335 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
338 ret = iommu_queue_command(iommu, &cmd);
343 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
344 u16 domid, int pde, int s)
346 memset(cmd, 0, sizeof(*cmd));
347 address &= PAGE_MASK;
348 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
349 cmd->data[1] |= domid;
350 cmd->data[2] = lower_32_bits(address);
351 cmd->data[3] = upper_32_bits(address);
352 if (s) /* size bit - we flush more than one 4kb page */
353 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
354 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
355 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
359 * Generic command send function for invalidaing TLB entries
361 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
362 u64 address, u16 domid, int pde, int s)
364 struct iommu_cmd cmd;
367 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
369 ret = iommu_queue_command(iommu, &cmd);
375 * TLB invalidation function which is called from the mapping functions.
376 * It invalidates a single PTE if the range to flush is within a single
377 * page. Otherwise it flushes the whole TLB of the IOMMU.
379 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
380 u64 address, size_t size)
383 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
385 address &= PAGE_MASK;
389 * If we have to flush more than one page, flush all
390 * TLB entries for this domain
392 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
396 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
401 /* Flush the whole IO/TLB for a given protection domain */
402 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
404 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
406 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
409 #ifdef CONFIG_IOMMU_API
411 * This function is used to flush the IO/TLB for a given protection domain
412 * on every IOMMU in the system
414 static void iommu_flush_domain(u16 domid)
417 struct amd_iommu *iommu;
418 struct iommu_cmd cmd;
420 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
423 list_for_each_entry(iommu, &amd_iommu_list, list) {
424 spin_lock_irqsave(&iommu->lock, flags);
425 __iommu_queue_command(iommu, &cmd);
426 __iommu_completion_wait(iommu);
427 __iommu_wait_for_completion(iommu);
428 spin_unlock_irqrestore(&iommu->lock, flags);
433 /****************************************************************************
435 * The functions below are used the create the page table mappings for
436 * unity mapped regions.
438 ****************************************************************************/
441 * Generic mapping functions. It maps a physical address into a DMA
442 * address space. It allocates the page table pages if necessary.
443 * In the future it can be extended to a generic mapping function
444 * supporting all features of AMD IOMMU page tables like level skipping
445 * and full 64 bit address spaces.
447 static int iommu_map_page(struct protection_domain *dom,
448 unsigned long bus_addr,
449 unsigned long phys_addr,
452 u64 __pte, *pte, *page;
454 bus_addr = PAGE_ALIGN(bus_addr);
455 phys_addr = PAGE_ALIGN(phys_addr);
457 /* only support 512GB address spaces for now */
458 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
461 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
463 if (!IOMMU_PTE_PRESENT(*pte)) {
464 page = (u64 *)get_zeroed_page(GFP_KERNEL);
467 *pte = IOMMU_L2_PDE(virt_to_phys(page));
470 pte = IOMMU_PTE_PAGE(*pte);
471 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
473 if (!IOMMU_PTE_PRESENT(*pte)) {
474 page = (u64 *)get_zeroed_page(GFP_KERNEL);
477 *pte = IOMMU_L1_PDE(virt_to_phys(page));
480 pte = IOMMU_PTE_PAGE(*pte);
481 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
483 if (IOMMU_PTE_PRESENT(*pte))
486 __pte = phys_addr | IOMMU_PTE_P;
487 if (prot & IOMMU_PROT_IR)
488 __pte |= IOMMU_PTE_IR;
489 if (prot & IOMMU_PROT_IW)
490 __pte |= IOMMU_PTE_IW;
497 #ifdef CONFIG_IOMMU_API
498 static void iommu_unmap_page(struct protection_domain *dom,
499 unsigned long bus_addr)
503 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
505 if (!IOMMU_PTE_PRESENT(*pte))
508 pte = IOMMU_PTE_PAGE(*pte);
509 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
511 if (!IOMMU_PTE_PRESENT(*pte))
514 pte = IOMMU_PTE_PAGE(*pte);
515 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
522 * This function checks if a specific unity mapping entry is needed for
523 * this specific IOMMU.
525 static int iommu_for_unity_map(struct amd_iommu *iommu,
526 struct unity_map_entry *entry)
530 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
531 bdf = amd_iommu_alias_table[i];
532 if (amd_iommu_rlookup_table[bdf] == iommu)
540 * Init the unity mappings for a specific IOMMU in the system
542 * Basically iterates over all unity mapping entries and applies them to
543 * the default domain DMA of that IOMMU if necessary.
545 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
547 struct unity_map_entry *entry;
550 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
551 if (!iommu_for_unity_map(iommu, entry))
553 ret = dma_ops_unity_map(iommu->default_dom, entry);
562 * This function actually applies the mapping to the page table of the
565 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
566 struct unity_map_entry *e)
571 for (addr = e->address_start; addr < e->address_end;
573 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
577 * if unity mapping is in aperture range mark the page
578 * as allocated in the aperture
580 if (addr < dma_dom->aperture_size)
581 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
588 * Inits the unity mappings required for a specific device
590 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
593 struct unity_map_entry *e;
596 list_for_each_entry(e, &amd_iommu_unity_map, list) {
597 if (!(devid >= e->devid_start && devid <= e->devid_end))
599 ret = dma_ops_unity_map(dma_dom, e);
607 /****************************************************************************
609 * The next functions belong to the address allocator for the dma_ops
610 * interface functions. They work like the allocators in the other IOMMU
611 * drivers. Its basically a bitmap which marks the allocated pages in
612 * the aperture. Maybe it could be enhanced in the future to a more
613 * efficient allocator.
615 ****************************************************************************/
618 * The address allocator core function.
620 * called with domain->lock held
622 static unsigned long dma_ops_alloc_addresses(struct device *dev,
623 struct dma_ops_domain *dom,
625 unsigned long align_mask,
629 unsigned long address;
630 unsigned long boundary_size;
632 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
633 PAGE_SIZE) >> PAGE_SHIFT;
634 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
635 dma_mask >> PAGE_SHIFT);
637 if (dom->next_bit >= limit) {
639 dom->need_flush = true;
642 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
643 0 , boundary_size, align_mask);
645 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
646 0, boundary_size, align_mask);
647 dom->need_flush = true;
650 if (likely(address != -1)) {
651 dom->next_bit = address + pages;
652 address <<= PAGE_SHIFT;
654 address = bad_dma_address;
656 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
662 * The address free function.
664 * called with domain->lock held
666 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
667 unsigned long address,
670 address >>= PAGE_SHIFT;
671 iommu_area_free(dom->bitmap, address, pages);
673 if (address >= dom->next_bit)
674 dom->need_flush = true;
677 /****************************************************************************
679 * The next functions belong to the domain allocation. A domain is
680 * allocated for every IOMMU as the default domain. If device isolation
681 * is enabled, every device get its own domain. The most important thing
682 * about domains is the page table mapping the DMA address space they
685 ****************************************************************************/
687 static u16 domain_id_alloc(void)
692 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
693 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
695 if (id > 0 && id < MAX_DOMAIN_ID)
696 __set_bit(id, amd_iommu_pd_alloc_bitmap);
699 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
704 #ifdef CONFIG_IOMMU_API
705 static void domain_id_free(int id)
709 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
710 if (id > 0 && id < MAX_DOMAIN_ID)
711 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
712 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
717 * Used to reserve address ranges in the aperture (e.g. for exclusion
720 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
721 unsigned long start_page,
724 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
726 if (start_page + pages > last_page)
727 pages = last_page - start_page;
729 iommu_area_reserve(dom->bitmap, start_page, pages);
732 static void free_pagetable(struct protection_domain *domain)
737 p1 = domain->pt_root;
742 for (i = 0; i < 512; ++i) {
743 if (!IOMMU_PTE_PRESENT(p1[i]))
746 p2 = IOMMU_PTE_PAGE(p1[i]);
747 for (j = 0; j < 512; ++j) {
748 if (!IOMMU_PTE_PRESENT(p2[j]))
750 p3 = IOMMU_PTE_PAGE(p2[j]);
751 free_page((unsigned long)p3);
754 free_page((unsigned long)p2);
757 free_page((unsigned long)p1);
759 domain->pt_root = NULL;
763 * Free a domain, only used if something went wrong in the
764 * allocation path and we need to free an already allocated page table
766 static void dma_ops_domain_free(struct dma_ops_domain *dom)
771 free_pagetable(&dom->domain);
773 kfree(dom->pte_pages);
781 * Allocates a new protection domain usable for the dma_ops functions.
782 * It also intializes the page table and the address allocator data
783 * structures required for the dma_ops interface
785 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
788 struct dma_ops_domain *dma_dom;
789 unsigned i, num_pte_pages;
794 * Currently the DMA aperture must be between 32 MB and 1GB in size
796 if ((order < 25) || (order > 30))
799 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
803 spin_lock_init(&dma_dom->domain.lock);
805 dma_dom->domain.id = domain_id_alloc();
806 if (dma_dom->domain.id == 0)
808 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
809 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
810 dma_dom->domain.flags = PD_DMA_OPS_MASK;
811 dma_dom->domain.priv = dma_dom;
812 if (!dma_dom->domain.pt_root)
814 dma_dom->aperture_size = (1ULL << order);
815 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
817 if (!dma_dom->bitmap)
820 * mark the first page as allocated so we never return 0 as
821 * a valid dma-address. So we can use 0 as error value
823 dma_dom->bitmap[0] = 1;
824 dma_dom->next_bit = 0;
826 dma_dom->need_flush = false;
827 dma_dom->target_dev = 0xffff;
829 /* Intialize the exclusion range if necessary */
830 if (iommu->exclusion_start &&
831 iommu->exclusion_start < dma_dom->aperture_size) {
832 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
833 int pages = iommu_num_pages(iommu->exclusion_start,
834 iommu->exclusion_length,
836 dma_ops_reserve_addresses(dma_dom, startpage, pages);
840 * At the last step, build the page tables so we don't need to
841 * allocate page table pages in the dma_ops mapping/unmapping
844 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
845 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
847 if (!dma_dom->pte_pages)
850 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
854 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
856 for (i = 0; i < num_pte_pages; ++i) {
857 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
858 if (!dma_dom->pte_pages[i])
860 address = virt_to_phys(dma_dom->pte_pages[i]);
861 l2_pde[i] = IOMMU_L1_PDE(address);
867 dma_ops_domain_free(dma_dom);
873 * little helper function to check whether a given protection domain is a
876 static bool dma_ops_domain(struct protection_domain *domain)
878 return domain->flags & PD_DMA_OPS_MASK;
882 * Find out the protection domain structure for a given PCI device. This
883 * will give us the pointer to the page table root for example.
885 static struct protection_domain *domain_for_device(u16 devid)
887 struct protection_domain *dom;
890 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
891 dom = amd_iommu_pd_table[devid];
892 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
898 * If a device is not yet associated with a domain, this function does
899 * assigns it visible for the hardware
901 static void attach_device(struct amd_iommu *iommu,
902 struct protection_domain *domain,
906 u64 pte_root = virt_to_phys(domain->pt_root);
908 domain->dev_cnt += 1;
910 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
911 << DEV_ENTRY_MODE_SHIFT;
912 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
914 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
915 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
916 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
917 amd_iommu_dev_table[devid].data[2] = domain->id;
919 amd_iommu_pd_table[devid] = domain;
920 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
922 iommu_queue_inv_dev_entry(iommu, devid);
926 * Removes a device from a protection domain (unlocked)
928 static void __detach_device(struct protection_domain *domain, u16 devid)
932 spin_lock(&domain->lock);
934 /* remove domain from the lookup table */
935 amd_iommu_pd_table[devid] = NULL;
937 /* remove entry from the device table seen by the hardware */
938 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
939 amd_iommu_dev_table[devid].data[1] = 0;
940 amd_iommu_dev_table[devid].data[2] = 0;
942 /* decrease reference counter */
943 domain->dev_cnt -= 1;
946 spin_unlock(&domain->lock);
950 * Removes a device from a protection domain (with devtable_lock held)
952 static void detach_device(struct protection_domain *domain, u16 devid)
956 /* lock device table */
957 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
958 __detach_device(domain, devid);
959 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
962 static int device_change_notifier(struct notifier_block *nb,
963 unsigned long action, void *data)
965 struct device *dev = data;
966 struct pci_dev *pdev = to_pci_dev(dev);
967 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
968 struct protection_domain *domain;
969 struct dma_ops_domain *dma_domain;
970 struct amd_iommu *iommu;
971 int order = amd_iommu_aperture_order;
974 if (devid > amd_iommu_last_bdf)
977 devid = amd_iommu_alias_table[devid];
979 iommu = amd_iommu_rlookup_table[devid];
983 domain = domain_for_device(devid);
985 if (domain && !dma_ops_domain(domain))
986 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
987 "to a non-dma-ops domain\n", dev_name(dev));
990 case BUS_NOTIFY_BOUND_DRIVER:
993 dma_domain = find_protection_domain(devid);
995 dma_domain = iommu->default_dom;
996 attach_device(iommu, &dma_domain->domain, devid);
997 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
998 "device %s\n", dma_domain->domain.id, dev_name(dev));
1000 case BUS_NOTIFY_UNBIND_DRIVER:
1003 detach_device(domain, devid);
1005 case BUS_NOTIFY_ADD_DEVICE:
1006 /* allocate a protection domain if a device is added */
1007 dma_domain = find_protection_domain(devid);
1010 dma_domain = dma_ops_domain_alloc(iommu, order);
1013 dma_domain->target_dev = devid;
1015 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1016 list_add_tail(&dma_domain->list, &iommu_pd_list);
1017 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1024 iommu_queue_inv_dev_entry(iommu, devid);
1025 iommu_completion_wait(iommu);
1031 struct notifier_block device_nb = {
1032 .notifier_call = device_change_notifier,
1035 /*****************************************************************************
1037 * The next functions belong to the dma_ops mapping/unmapping code.
1039 *****************************************************************************/
1042 * This function checks if the driver got a valid device from the caller to
1043 * avoid dereferencing invalid pointers.
1045 static bool check_device(struct device *dev)
1047 if (!dev || !dev->dma_mask)
1054 * In this function the list of preallocated protection domains is traversed to
1055 * find the domain for a specific device
1057 static struct dma_ops_domain *find_protection_domain(u16 devid)
1059 struct dma_ops_domain *entry, *ret = NULL;
1060 unsigned long flags;
1062 if (list_empty(&iommu_pd_list))
1065 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1067 list_for_each_entry(entry, &iommu_pd_list, list) {
1068 if (entry->target_dev == devid) {
1074 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1080 * In the dma_ops path we only have the struct device. This function
1081 * finds the corresponding IOMMU, the protection domain and the
1082 * requestor id for a given device.
1083 * If the device is not yet associated with a domain this is also done
1086 static int get_device_resources(struct device *dev,
1087 struct amd_iommu **iommu,
1088 struct protection_domain **domain,
1091 struct dma_ops_domain *dma_dom;
1092 struct pci_dev *pcidev;
1099 if (dev->bus != &pci_bus_type)
1102 pcidev = to_pci_dev(dev);
1103 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1105 /* device not translated by any IOMMU in the system? */
1106 if (_bdf > amd_iommu_last_bdf)
1109 *bdf = amd_iommu_alias_table[_bdf];
1111 *iommu = amd_iommu_rlookup_table[*bdf];
1114 *domain = domain_for_device(*bdf);
1115 if (*domain == NULL) {
1116 dma_dom = find_protection_domain(*bdf);
1118 dma_dom = (*iommu)->default_dom;
1119 *domain = &dma_dom->domain;
1120 attach_device(*iommu, *domain, *bdf);
1121 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1122 "device %s\n", (*domain)->id, dev_name(dev));
1125 if (domain_for_device(_bdf) == NULL)
1126 attach_device(*iommu, *domain, _bdf);
1132 * This is the generic map function. It maps one 4kb page at paddr to
1133 * the given address in the DMA address space for the domain.
1135 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1136 struct dma_ops_domain *dom,
1137 unsigned long address,
1143 WARN_ON(address > dom->aperture_size);
1147 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1148 pte += IOMMU_PTE_L0_INDEX(address);
1150 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1152 if (direction == DMA_TO_DEVICE)
1153 __pte |= IOMMU_PTE_IR;
1154 else if (direction == DMA_FROM_DEVICE)
1155 __pte |= IOMMU_PTE_IW;
1156 else if (direction == DMA_BIDIRECTIONAL)
1157 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1163 return (dma_addr_t)address;
1167 * The generic unmapping function for on page in the DMA address space.
1169 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1170 struct dma_ops_domain *dom,
1171 unsigned long address)
1175 if (address >= dom->aperture_size)
1178 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1180 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1181 pte += IOMMU_PTE_L0_INDEX(address);
1189 * This function contains common code for mapping of a physically
1190 * contiguous memory region into DMA address space. It is used by all
1191 * mapping functions provided with this IOMMU driver.
1192 * Must be called with the domain lock held.
1194 static dma_addr_t __map_single(struct device *dev,
1195 struct amd_iommu *iommu,
1196 struct dma_ops_domain *dma_dom,
1203 dma_addr_t offset = paddr & ~PAGE_MASK;
1204 dma_addr_t address, start;
1206 unsigned long align_mask = 0;
1209 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1213 align_mask = (1UL << get_order(size)) - 1;
1215 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1217 if (unlikely(address == bad_dma_address))
1221 for (i = 0; i < pages; ++i) {
1222 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1228 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1229 iommu_flush_tlb(iommu, dma_dom->domain.id);
1230 dma_dom->need_flush = false;
1231 } else if (unlikely(iommu_has_npcache(iommu)))
1232 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1239 * Does the reverse of the __map_single function. Must be called with
1240 * the domain lock held too
1242 static void __unmap_single(struct amd_iommu *iommu,
1243 struct dma_ops_domain *dma_dom,
1244 dma_addr_t dma_addr,
1248 dma_addr_t i, start;
1251 if ((dma_addr == bad_dma_address) ||
1252 (dma_addr + size > dma_dom->aperture_size))
1255 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1256 dma_addr &= PAGE_MASK;
1259 for (i = 0; i < pages; ++i) {
1260 dma_ops_domain_unmap(iommu, dma_dom, start);
1264 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1266 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1267 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1268 dma_dom->need_flush = false;
1273 * The exported map_single function for dma_ops.
1275 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1276 size_t size, int dir)
1278 unsigned long flags;
1279 struct amd_iommu *iommu;
1280 struct protection_domain *domain;
1285 INC_STATS_COUNTER(cnt_map_single);
1287 if (!check_device(dev))
1288 return bad_dma_address;
1290 dma_mask = *dev->dma_mask;
1292 get_device_resources(dev, &iommu, &domain, &devid);
1294 if (iommu == NULL || domain == NULL)
1295 /* device not handled by any AMD IOMMU */
1296 return (dma_addr_t)paddr;
1298 if (!dma_ops_domain(domain))
1299 return bad_dma_address;
1301 spin_lock_irqsave(&domain->lock, flags);
1302 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1304 if (addr == bad_dma_address)
1307 iommu_completion_wait(iommu);
1310 spin_unlock_irqrestore(&domain->lock, flags);
1316 * The exported unmap_single function for dma_ops.
1318 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1319 size_t size, int dir)
1321 unsigned long flags;
1322 struct amd_iommu *iommu;
1323 struct protection_domain *domain;
1326 INC_STATS_COUNTER(cnt_unmap_single);
1328 if (!check_device(dev) ||
1329 !get_device_resources(dev, &iommu, &domain, &devid))
1330 /* device not handled by any AMD IOMMU */
1333 if (!dma_ops_domain(domain))
1336 spin_lock_irqsave(&domain->lock, flags);
1338 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1340 iommu_completion_wait(iommu);
1342 spin_unlock_irqrestore(&domain->lock, flags);
1346 * This is a special map_sg function which is used if we should map a
1347 * device which is not handled by an AMD IOMMU in the system.
1349 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1350 int nelems, int dir)
1352 struct scatterlist *s;
1355 for_each_sg(sglist, s, nelems, i) {
1356 s->dma_address = (dma_addr_t)sg_phys(s);
1357 s->dma_length = s->length;
1364 * The exported map_sg function for dma_ops (handles scatter-gather
1367 static int map_sg(struct device *dev, struct scatterlist *sglist,
1368 int nelems, int dir)
1370 unsigned long flags;
1371 struct amd_iommu *iommu;
1372 struct protection_domain *domain;
1375 struct scatterlist *s;
1377 int mapped_elems = 0;
1380 if (!check_device(dev))
1383 dma_mask = *dev->dma_mask;
1385 get_device_resources(dev, &iommu, &domain, &devid);
1387 if (!iommu || !domain)
1388 return map_sg_no_iommu(dev, sglist, nelems, dir);
1390 if (!dma_ops_domain(domain))
1393 spin_lock_irqsave(&domain->lock, flags);
1395 for_each_sg(sglist, s, nelems, i) {
1398 s->dma_address = __map_single(dev, iommu, domain->priv,
1399 paddr, s->length, dir, false,
1402 if (s->dma_address) {
1403 s->dma_length = s->length;
1409 iommu_completion_wait(iommu);
1412 spin_unlock_irqrestore(&domain->lock, flags);
1414 return mapped_elems;
1416 for_each_sg(sglist, s, mapped_elems, i) {
1418 __unmap_single(iommu, domain->priv, s->dma_address,
1419 s->dma_length, dir);
1420 s->dma_address = s->dma_length = 0;
1429 * The exported map_sg function for dma_ops (handles scatter-gather
1432 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1433 int nelems, int dir)
1435 unsigned long flags;
1436 struct amd_iommu *iommu;
1437 struct protection_domain *domain;
1438 struct scatterlist *s;
1442 if (!check_device(dev) ||
1443 !get_device_resources(dev, &iommu, &domain, &devid))
1446 if (!dma_ops_domain(domain))
1449 spin_lock_irqsave(&domain->lock, flags);
1451 for_each_sg(sglist, s, nelems, i) {
1452 __unmap_single(iommu, domain->priv, s->dma_address,
1453 s->dma_length, dir);
1454 s->dma_address = s->dma_length = 0;
1457 iommu_completion_wait(iommu);
1459 spin_unlock_irqrestore(&domain->lock, flags);
1463 * The exported alloc_coherent function for dma_ops.
1465 static void *alloc_coherent(struct device *dev, size_t size,
1466 dma_addr_t *dma_addr, gfp_t flag)
1468 unsigned long flags;
1470 struct amd_iommu *iommu;
1471 struct protection_domain *domain;
1474 u64 dma_mask = dev->coherent_dma_mask;
1476 if (!check_device(dev))
1479 if (!get_device_resources(dev, &iommu, &domain, &devid))
1480 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1483 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1487 paddr = virt_to_phys(virt_addr);
1489 if (!iommu || !domain) {
1490 *dma_addr = (dma_addr_t)paddr;
1494 if (!dma_ops_domain(domain))
1498 dma_mask = *dev->dma_mask;
1500 spin_lock_irqsave(&domain->lock, flags);
1502 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1503 size, DMA_BIDIRECTIONAL, true, dma_mask);
1505 if (*dma_addr == bad_dma_address)
1508 iommu_completion_wait(iommu);
1510 spin_unlock_irqrestore(&domain->lock, flags);
1516 free_pages((unsigned long)virt_addr, get_order(size));
1522 * The exported free_coherent function for dma_ops.
1524 static void free_coherent(struct device *dev, size_t size,
1525 void *virt_addr, dma_addr_t dma_addr)
1527 unsigned long flags;
1528 struct amd_iommu *iommu;
1529 struct protection_domain *domain;
1532 if (!check_device(dev))
1535 get_device_resources(dev, &iommu, &domain, &devid);
1537 if (!iommu || !domain)
1540 if (!dma_ops_domain(domain))
1543 spin_lock_irqsave(&domain->lock, flags);
1545 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1547 iommu_completion_wait(iommu);
1549 spin_unlock_irqrestore(&domain->lock, flags);
1552 free_pages((unsigned long)virt_addr, get_order(size));
1556 * This function is called by the DMA layer to find out if we can handle a
1557 * particular device. It is part of the dma_ops.
1559 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1562 struct pci_dev *pcidev;
1564 /* No device or no PCI device */
1565 if (!dev || dev->bus != &pci_bus_type)
1568 pcidev = to_pci_dev(dev);
1570 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1572 /* Out of our scope? */
1573 if (bdf > amd_iommu_last_bdf)
1580 * The function for pre-allocating protection domains.
1582 * If the driver core informs the DMA layer if a driver grabs a device
1583 * we don't need to preallocate the protection domains anymore.
1584 * For now we have to.
1586 void prealloc_protection_domains(void)
1588 struct pci_dev *dev = NULL;
1589 struct dma_ops_domain *dma_dom;
1590 struct amd_iommu *iommu;
1591 int order = amd_iommu_aperture_order;
1594 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1595 devid = calc_devid(dev->bus->number, dev->devfn);
1596 if (devid > amd_iommu_last_bdf)
1598 devid = amd_iommu_alias_table[devid];
1599 if (domain_for_device(devid))
1601 iommu = amd_iommu_rlookup_table[devid];
1604 dma_dom = dma_ops_domain_alloc(iommu, order);
1607 init_unity_mappings_for_device(dma_dom, devid);
1608 dma_dom->target_dev = devid;
1610 list_add_tail(&dma_dom->list, &iommu_pd_list);
1614 static struct dma_mapping_ops amd_iommu_dma_ops = {
1615 .alloc_coherent = alloc_coherent,
1616 .free_coherent = free_coherent,
1617 .map_single = map_single,
1618 .unmap_single = unmap_single,
1620 .unmap_sg = unmap_sg,
1621 .dma_supported = amd_iommu_dma_supported,
1625 * The function which clues the AMD IOMMU driver into dma_ops.
1627 int __init amd_iommu_init_dma_ops(void)
1629 struct amd_iommu *iommu;
1630 int order = amd_iommu_aperture_order;
1634 * first allocate a default protection domain for every IOMMU we
1635 * found in the system. Devices not assigned to any other
1636 * protection domain will be assigned to the default one.
1638 list_for_each_entry(iommu, &amd_iommu_list, list) {
1639 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1640 if (iommu->default_dom == NULL)
1642 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1643 ret = iommu_init_unity_mappings(iommu);
1649 * If device isolation is enabled, pre-allocate the protection
1650 * domains for each device.
1652 if (amd_iommu_isolate)
1653 prealloc_protection_domains();
1657 bad_dma_address = 0;
1658 #ifdef CONFIG_GART_IOMMU
1659 gart_iommu_aperture_disabled = 1;
1660 gart_iommu_aperture = 0;
1663 /* Make the driver finally visible to the drivers */
1664 dma_ops = &amd_iommu_dma_ops;
1666 #ifdef CONFIG_IOMMU_API
1667 register_iommu(&amd_iommu_ops);
1670 bus_register_notifier(&pci_bus_type, &device_nb);
1672 amd_iommu_stats_init();
1678 list_for_each_entry(iommu, &amd_iommu_list, list) {
1679 if (iommu->default_dom)
1680 dma_ops_domain_free(iommu->default_dom);
1686 /*****************************************************************************
1688 * The following functions belong to the exported interface of AMD IOMMU
1690 * This interface allows access to lower level functions of the IOMMU
1691 * like protection domain handling and assignement of devices to domains
1692 * which is not possible with the dma_ops interface.
1694 *****************************************************************************/
1696 #ifdef CONFIG_IOMMU_API
1698 static void cleanup_domain(struct protection_domain *domain)
1700 unsigned long flags;
1703 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1705 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1706 if (amd_iommu_pd_table[devid] == domain)
1707 __detach_device(domain, devid);
1709 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1712 static int amd_iommu_domain_init(struct iommu_domain *dom)
1714 struct protection_domain *domain;
1716 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1720 spin_lock_init(&domain->lock);
1721 domain->mode = PAGE_MODE_3_LEVEL;
1722 domain->id = domain_id_alloc();
1725 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1726 if (!domain->pt_root)
1739 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1741 struct protection_domain *domain = dom->priv;
1746 if (domain->dev_cnt > 0)
1747 cleanup_domain(domain);
1749 BUG_ON(domain->dev_cnt != 0);
1751 free_pagetable(domain);
1753 domain_id_free(domain->id);
1760 static void amd_iommu_detach_device(struct iommu_domain *dom,
1763 struct protection_domain *domain = dom->priv;
1764 struct amd_iommu *iommu;
1765 struct pci_dev *pdev;
1768 if (dev->bus != &pci_bus_type)
1771 pdev = to_pci_dev(dev);
1773 devid = calc_devid(pdev->bus->number, pdev->devfn);
1776 detach_device(domain, devid);
1778 iommu = amd_iommu_rlookup_table[devid];
1782 iommu_queue_inv_dev_entry(iommu, devid);
1783 iommu_completion_wait(iommu);
1786 static int amd_iommu_attach_device(struct iommu_domain *dom,
1789 struct protection_domain *domain = dom->priv;
1790 struct protection_domain *old_domain;
1791 struct amd_iommu *iommu;
1792 struct pci_dev *pdev;
1795 if (dev->bus != &pci_bus_type)
1798 pdev = to_pci_dev(dev);
1800 devid = calc_devid(pdev->bus->number, pdev->devfn);
1802 if (devid >= amd_iommu_last_bdf ||
1803 devid != amd_iommu_alias_table[devid])
1806 iommu = amd_iommu_rlookup_table[devid];
1810 old_domain = domain_for_device(devid);
1814 attach_device(iommu, domain, devid);
1816 iommu_completion_wait(iommu);
1821 static int amd_iommu_map_range(struct iommu_domain *dom,
1822 unsigned long iova, phys_addr_t paddr,
1823 size_t size, int iommu_prot)
1825 struct protection_domain *domain = dom->priv;
1826 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1830 if (iommu_prot & IOMMU_READ)
1831 prot |= IOMMU_PROT_IR;
1832 if (iommu_prot & IOMMU_WRITE)
1833 prot |= IOMMU_PROT_IW;
1838 for (i = 0; i < npages; ++i) {
1839 ret = iommu_map_page(domain, iova, paddr, prot);
1850 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1851 unsigned long iova, size_t size)
1854 struct protection_domain *domain = dom->priv;
1855 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1859 for (i = 0; i < npages; ++i) {
1860 iommu_unmap_page(domain, iova);
1864 iommu_flush_domain(domain->id);
1867 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1870 struct protection_domain *domain = dom->priv;
1871 unsigned long offset = iova & ~PAGE_MASK;
1875 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1877 if (!IOMMU_PTE_PRESENT(*pte))
1880 pte = IOMMU_PTE_PAGE(*pte);
1881 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1883 if (!IOMMU_PTE_PRESENT(*pte))
1886 pte = IOMMU_PTE_PAGE(*pte);
1887 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1889 if (!IOMMU_PTE_PRESENT(*pte))
1892 paddr = *pte & IOMMU_PAGE_MASK;
1898 static struct iommu_ops amd_iommu_ops = {
1899 .domain_init = amd_iommu_domain_init,
1900 .domain_destroy = amd_iommu_domain_destroy,
1901 .attach_dev = amd_iommu_attach_device,
1902 .detach_dev = amd_iommu_detach_device,
1903 .map = amd_iommu_map_range,
1904 .unmap = amd_iommu_unmap_range,
1905 .iova_to_phys = amd_iommu_iova_to_phys,