2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <asm/pci-direct.h>
26 #include <asm/amd_iommu_types.h>
27 #include <asm/amd_iommu.h>
31 * definitions for the ACPI scanning code
33 #define DEVID(bus, devfn) (((bus) << 8) | (devfn))
34 #define PCI_BUS(x) (((x) >> 8) & 0xff)
35 #define IVRS_HEADER_LENGTH 48
36 #define TBL_SIZE(x) (1 << (PAGE_SHIFT + get_order(amd_iommu_last_bdf * (x))))
38 #define ACPI_IVHD_TYPE 0x10
39 #define ACPI_IVMD_TYPE_ALL 0x20
40 #define ACPI_IVMD_TYPE 0x21
41 #define ACPI_IVMD_TYPE_RANGE 0x22
43 #define IVHD_DEV_ALL 0x01
44 #define IVHD_DEV_SELECT 0x02
45 #define IVHD_DEV_SELECT_RANGE_START 0x03
46 #define IVHD_DEV_RANGE_END 0x04
47 #define IVHD_DEV_ALIAS 0x42
48 #define IVHD_DEV_ALIAS_RANGE 0x43
49 #define IVHD_DEV_EXT_SELECT 0x46
50 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
52 #define IVHD_FLAG_HT_TUN_EN 0x00
53 #define IVHD_FLAG_PASSPW_EN 0x01
54 #define IVHD_FLAG_RESPASSPW_EN 0x02
55 #define IVHD_FLAG_ISOC_EN 0x03
57 #define IVMD_FLAG_EXCL_RANGE 0x08
58 #define IVMD_FLAG_UNITY_MAP 0x01
60 #define ACPI_DEVFLAG_INITPASS 0x01
61 #define ACPI_DEVFLAG_EXTINT 0x02
62 #define ACPI_DEVFLAG_NMI 0x04
63 #define ACPI_DEVFLAG_SYSMGT1 0x10
64 #define ACPI_DEVFLAG_SYSMGT2 0x20
65 #define ACPI_DEVFLAG_LINT0 0x40
66 #define ACPI_DEVFLAG_LINT1 0x80
67 #define ACPI_DEVFLAG_ATSDIS 0x10000000
70 * ACPI table definitions
72 * These data structures are laid over the table to parse the important values
77 * structure describing one IOMMU in the ACPI table. Typically followed by one
78 * or more ivhd_entrys.
90 } __attribute__((packed));
93 * A device entry describing which devices a specific IOMMU translates and
94 * which requestor ids they use.
101 } __attribute__((packed));
104 * An AMD IOMMU memory definition structure. It defines things like exclusion
105 * ranges for devices and regions that should be unity mapped.
116 } __attribute__((packed));
118 static int __initdata amd_iommu_detected;
120 u16 amd_iommu_last_bdf; /* largest PCI device id we have
122 struct list_head amd_iommu_unity_map; /* a list of required unity mappings
124 unsigned amd_iommu_aperture_order = 26; /* size of aperture in power of 2 */
125 int amd_iommu_isolate; /* if 1, device isolation is enabled */
127 struct list_head amd_iommu_list; /* list of all AMD IOMMUs in the
131 * Pointer to the device table which is shared by all AMD IOMMUs
132 * it is indexed by the PCI device id or the HT unit id and contains
133 * information about the domain the device belongs to as well as the
134 * page table root pointer.
136 struct dev_table_entry *amd_iommu_dev_table;
139 * The alias table is a driver specific data structure which contains the
140 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
141 * More than one device can share the same requestor id.
143 u16 *amd_iommu_alias_table;
146 * The rlookup table is used to find the IOMMU which is responsible
147 * for a specific device. It is also indexed by the PCI device id.
149 struct amd_iommu **amd_iommu_rlookup_table;
152 * The pd table (protection domain table) is used to find the protection domain
153 * data structure a device belongs to. Indexed with the PCI device id too.
155 struct protection_domain **amd_iommu_pd_table;
158 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
159 * to know which ones are already in use.
161 unsigned long *amd_iommu_pd_alloc_bitmap;
163 static u32 dev_table_size; /* size of the device table */
164 static u32 alias_table_size; /* size of the alias table */
165 static u32 rlookup_table_size; /* size if the rlookup table */
167 static inline void update_last_devid(u16 devid)
169 if (devid > amd_iommu_last_bdf)
170 amd_iommu_last_bdf = devid;
173 /****************************************************************************
175 * AMD IOMMU MMIO register space handling functions
177 * These functions are used to program the IOMMU device registers in
178 * MMIO space required for that driver.
180 ****************************************************************************/
183 * This function set the exclusion range in the IOMMU. DMA accesses to the
184 * exclusion range are passed through untranslated
186 static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
188 u64 start = iommu->exclusion_start & PAGE_MASK;
189 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
192 if (!iommu->exclusion_start)
195 entry = start | MMIO_EXCL_ENABLE_MASK;
196 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
197 &entry, sizeof(entry));
200 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
201 &entry, sizeof(entry));
204 /* Programs the physical address of the device table into the IOMMU hardware */
205 static void __init iommu_set_device_table(struct amd_iommu *iommu)
209 BUG_ON(iommu->mmio_base == NULL);
211 entry = virt_to_phys(amd_iommu_dev_table);
212 entry |= (dev_table_size >> 12) - 1;
213 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
214 &entry, sizeof(entry));
217 /* Generic functions to enable/disable certain features of the IOMMU. */
218 static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
222 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
224 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
227 static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
231 ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
233 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
236 /* Function to enable the hardware */
237 void __init iommu_enable(struct amd_iommu *iommu)
239 printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at ");
240 print_devid(iommu->devid, 0);
241 printk(" cap 0x%hx\n", iommu->cap_ptr);
243 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
247 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
248 * the system has one.
250 static u8 * __init iommu_map_mmio_space(u64 address)
254 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
257 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
261 release_mem_region(address, MMIO_REGION_LENGTH);
266 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
268 if (iommu->mmio_base)
269 iounmap(iommu->mmio_base);
270 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
273 /****************************************************************************
275 * The functions below belong to the first pass of AMD IOMMU ACPI table
276 * parsing. In this pass we try to find out the highest device id this
277 * code has to handle. Upon this information the size of the shared data
278 * structures is determined later.
280 ****************************************************************************/
283 * This function reads the last device id the IOMMU has to handle from the PCI
284 * capability header for this IOMMU
286 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
290 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
291 update_last_devid(DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
297 * After reading the highest device id from the IOMMU PCI capability header
298 * this function looks if there is a higher device id defined in the ACPI table
300 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
302 u8 *p = (void *)h, *end = (void *)h;
303 struct ivhd_entry *dev;
308 find_last_devid_on_pci(PCI_BUS(h->devid),
314 dev = (struct ivhd_entry *)p;
316 case IVHD_DEV_SELECT:
317 case IVHD_DEV_RANGE_END:
319 case IVHD_DEV_EXT_SELECT:
320 /* all the above subfield types refer to device ids */
321 update_last_devid(dev->devid);
326 p += 0x04 << (*p >> 6);
335 * Iterate over all IVHD entries in the ACPI table and find the highest device
336 * id which we need to handle. This is the first of three functions which parse
337 * the ACPI table. So we check the checksum here.
339 static int __init find_last_devid_acpi(struct acpi_table_header *table)
342 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
343 struct ivhd_header *h;
346 * Validate checksum here so we don't need to do it when
347 * we actually parse the table
349 for (i = 0; i < table->length; ++i)
352 /* ACPI table corrupt */
355 p += IVRS_HEADER_LENGTH;
357 end += table->length;
359 h = (struct ivhd_header *)p;
362 find_last_devid_from_ivhd(h);
374 /****************************************************************************
376 * The following functions belong the the code path which parses the ACPI table
377 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
378 * data structures, initialize the device/alias/rlookup table and also
379 * basically initialize the hardware.
381 ****************************************************************************/
384 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
385 * write commands to that buffer later and the IOMMU will execute them
388 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
390 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL,
391 get_order(CMD_BUFFER_SIZE));
397 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
399 memset(cmd_buf, 0, CMD_BUFFER_SIZE);
401 entry = (u64)virt_to_phys(cmd_buf);
402 entry |= MMIO_CMD_SIZE_512;
403 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
404 &entry, sizeof(entry));
406 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
411 static void __init free_command_buffer(struct amd_iommu *iommu)
414 free_pages((unsigned long)iommu->cmd_buf,
415 get_order(CMD_BUFFER_SIZE));
418 /* sets a specific bit in the device table entry. */
419 static void set_dev_entry_bit(u16 devid, u8 bit)
421 int i = (bit >> 5) & 0x07;
422 int _bit = bit & 0x1f;
424 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
428 * This function takes the device specific flags read from the ACPI
429 * table and sets up the device table entry with that information
431 static void __init set_dev_entry_from_acpi(u16 devid, u32 flags, u32 ext_flags)
433 if (flags & ACPI_DEVFLAG_INITPASS)
434 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
435 if (flags & ACPI_DEVFLAG_EXTINT)
436 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
437 if (flags & ACPI_DEVFLAG_NMI)
438 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
439 if (flags & ACPI_DEVFLAG_SYSMGT1)
440 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
441 if (flags & ACPI_DEVFLAG_SYSMGT2)
442 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
443 if (flags & ACPI_DEVFLAG_LINT0)
444 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
445 if (flags & ACPI_DEVFLAG_LINT1)
446 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
449 /* Writes the specific IOMMU for a device into the rlookup table */
450 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
452 amd_iommu_rlookup_table[devid] = iommu;
456 * Reads the device exclusion range from ACPI and initialize IOMMU with
459 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
461 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
463 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
468 * We only can configure exclusion ranges per IOMMU, not
469 * per device. But we can enable the exclusion range per
470 * device. This is done here
472 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
473 iommu->exclusion_start = m->range_start;
474 iommu->exclusion_length = m->range_length;
479 * This function reads some important data from the IOMMU PCI space and
480 * initializes the driver data structure with it. It reads the hardware
481 * capabilities and the first/last device entries
483 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
485 int bus = PCI_BUS(iommu->devid);
486 int dev = PCI_SLOT(iommu->devid);
487 int fn = PCI_FUNC(iommu->devid);
488 int cap_ptr = iommu->cap_ptr;
491 iommu->cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_CAP_HDR_OFFSET);
493 range = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
494 iommu->first_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_FD(range));
495 iommu->last_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_LD(range));
499 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
500 * initializes the hardware and our data structures with it.
502 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
503 struct ivhd_header *h)
506 u8 *end = p, flags = 0;
507 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
510 struct ivhd_entry *e;
513 * First set the recommended feature enable bits from ACPI
514 * into the IOMMU control registers
516 h->flags & IVHD_FLAG_HT_TUN_EN ?
517 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
518 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
520 h->flags & IVHD_FLAG_PASSPW_EN ?
521 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
522 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
524 h->flags & IVHD_FLAG_RESPASSPW_EN ?
525 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
526 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
528 h->flags & IVHD_FLAG_ISOC_EN ?
529 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
530 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
533 * make IOMMU memory accesses cache coherent
535 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
538 * Done. Now parse the device entries
540 p += sizeof(struct ivhd_header);
544 e = (struct ivhd_entry *)p;
547 for (dev_i = iommu->first_device;
548 dev_i <= iommu->last_device; ++dev_i)
549 set_dev_entry_from_acpi(dev_i, e->flags, 0);
551 case IVHD_DEV_SELECT:
553 set_dev_entry_from_acpi(devid, e->flags, 0);
555 case IVHD_DEV_SELECT_RANGE_START:
556 devid_start = e->devid;
563 devid_to = e->ext >> 8;
564 set_dev_entry_from_acpi(devid, e->flags, 0);
565 amd_iommu_alias_table[devid] = devid_to;
567 case IVHD_DEV_ALIAS_RANGE:
568 devid_start = e->devid;
570 devid_to = e->ext >> 8;
574 case IVHD_DEV_EXT_SELECT:
576 set_dev_entry_from_acpi(devid, e->flags, e->ext);
578 case IVHD_DEV_EXT_SELECT_RANGE:
579 devid_start = e->devid;
584 case IVHD_DEV_RANGE_END:
586 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
588 amd_iommu_alias_table[dev_i] = devid_to;
589 set_dev_entry_from_acpi(
590 amd_iommu_alias_table[dev_i],
598 p += 0x04 << (e->type >> 6);
602 /* Initializes the device->iommu mapping for the driver */
603 static int __init init_iommu_devices(struct amd_iommu *iommu)
607 for (i = iommu->first_device; i <= iommu->last_device; ++i)
608 set_iommu_for_device(iommu, i);
613 static void __init free_iommu_one(struct amd_iommu *iommu)
615 free_command_buffer(iommu);
616 iommu_unmap_mmio_space(iommu);
619 static void __init free_iommu_all(void)
621 struct amd_iommu *iommu, *next;
623 list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) {
624 list_del(&iommu->list);
625 free_iommu_one(iommu);
631 * This function clues the initialization function for one IOMMU
632 * together and also allocates the command buffer and programs the
633 * hardware. It does NOT enable the IOMMU. This is done afterwards.
635 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
637 spin_lock_init(&iommu->lock);
638 list_add_tail(&iommu->list, &amd_iommu_list);
641 * Copy data from ACPI table entry to the iommu struct
643 iommu->devid = h->devid;
644 iommu->cap_ptr = h->cap_ptr;
645 iommu->mmio_phys = h->mmio_phys;
646 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
647 if (!iommu->mmio_base)
650 iommu_set_device_table(iommu);
651 iommu->cmd_buf = alloc_command_buffer(iommu);
655 init_iommu_from_pci(iommu);
656 init_iommu_from_acpi(iommu, h);
657 init_iommu_devices(iommu);
663 * Iterates over all IOMMU entries in the ACPI table, allocates the
664 * IOMMU structure and initializes it with init_iommu_one()
666 static int __init init_iommu_all(struct acpi_table_header *table)
668 u8 *p = (u8 *)table, *end = (u8 *)table;
669 struct ivhd_header *h;
670 struct amd_iommu *iommu;
673 INIT_LIST_HEAD(&amd_iommu_list);
675 end += table->length;
676 p += IVRS_HEADER_LENGTH;
679 h = (struct ivhd_header *)p;
682 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
685 ret = init_iommu_one(iommu, h);
700 /****************************************************************************
702 * The next functions belong to the third pass of parsing the ACPI
703 * table. In this last pass the memory mapping requirements are
704 * gathered (like exclusion and unity mapping reanges).
706 ****************************************************************************/
708 static void __init free_unity_maps(void)
710 struct unity_map_entry *entry, *next;
712 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
713 list_del(&entry->list);
718 /* called when we find an exclusion range definition in ACPI */
719 static int __init init_exclusion_range(struct ivmd_header *m)
725 set_device_exclusion_range(m->devid, m);
727 case ACPI_IVMD_TYPE_ALL:
728 for (i = 0; i < amd_iommu_last_bdf; ++i)
729 set_device_exclusion_range(i, m);
731 case ACPI_IVMD_TYPE_RANGE:
732 for (i = m->devid; i <= m->aux; ++i)
733 set_device_exclusion_range(i, m);
742 /* called for unity map ACPI definition */
743 static int __init init_unity_map_range(struct ivmd_header *m)
745 struct unity_map_entry *e = 0;
747 e = kzalloc(sizeof(*e), GFP_KERNEL);
754 e->devid_start = e->devid_end = m->devid;
756 case ACPI_IVMD_TYPE_ALL:
758 e->devid_end = amd_iommu_last_bdf;
760 case ACPI_IVMD_TYPE_RANGE:
761 e->devid_start = m->devid;
762 e->devid_end = m->aux;
765 e->address_start = PAGE_ALIGN(m->range_start);
766 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
767 e->prot = m->flags >> 1;
769 list_add_tail(&e->list, &amd_iommu_unity_map);
774 /* iterates over all memory definitions we find in the ACPI table */
775 static int __init init_memory_definitions(struct acpi_table_header *table)
777 u8 *p = (u8 *)table, *end = (u8 *)table;
778 struct ivmd_header *m;
780 INIT_LIST_HEAD(&amd_iommu_unity_map);
782 end += table->length;
783 p += IVRS_HEADER_LENGTH;
786 m = (struct ivmd_header *)p;
787 if (m->flags & IVMD_FLAG_EXCL_RANGE)
788 init_exclusion_range(m);
789 else if (m->flags & IVMD_FLAG_UNITY_MAP)
790 init_unity_map_range(m);
799 * This function finally enables all IOMMUs found in the system after
800 * they have been initialized
802 static void __init enable_iommus(void)
804 struct amd_iommu *iommu;
806 list_for_each_entry(iommu, &amd_iommu_list, list) {
807 iommu_set_exclusion_range(iommu);
813 * Suspend/Resume support
814 * disable suspend until real resume implemented
817 static int amd_iommu_resume(struct sys_device *dev)
822 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
827 static struct sysdev_class amd_iommu_sysdev_class = {
829 .suspend = amd_iommu_suspend,
830 .resume = amd_iommu_resume,
833 static struct sys_device device_amd_iommu = {
835 .cls = &amd_iommu_sysdev_class,
839 * This is the core init function for AMD IOMMU hardware in the system.
840 * This function is called from the generic x86 DMA layer initialization
843 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
846 * 1 pass) Find the highest PCI device id the driver has to handle.
847 * Upon this information the size of the data structures is
848 * determined that needs to be allocated.
850 * 2 pass) Initialize the data structures just allocated with the
851 * information in the ACPI table about available AMD IOMMUs
852 * in the system. It also maps the PCI devices in the
853 * system to specific IOMMUs
855 * 3 pass) After the basic data structures are allocated and
856 * initialized we update them with information about memory
857 * remapping requirements parsed out of the ACPI table in
860 * After that the hardware is initialized and ready to go. In the last
861 * step we do some Linux specific things like registering the driver in
862 * the dma_ops interface and initializing the suspend/resume support
863 * functions. Finally it prints some information about AMD IOMMUs and
864 * the driver state and enables the hardware.
866 int __init amd_iommu_init(void)
872 printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
876 if (!amd_iommu_detected)
880 * First parse ACPI tables to find the largest Bus/Dev/Func
881 * we need to handle. Upon this information the shared data
882 * structures for the IOMMUs in the system will be allocated
884 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
887 dev_table_size = TBL_SIZE(DEV_TABLE_ENTRY_SIZE);
888 alias_table_size = TBL_SIZE(ALIAS_TABLE_ENTRY_SIZE);
889 rlookup_table_size = TBL_SIZE(RLOOKUP_TABLE_ENTRY_SIZE);
893 /* Device table - directly used by all IOMMUs */
894 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL,
895 get_order(dev_table_size));
896 if (amd_iommu_dev_table == NULL)
900 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
901 * IOMMU see for that device
903 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
904 get_order(alias_table_size));
905 if (amd_iommu_alias_table == NULL)
908 /* IOMMU rlookup table - find the IOMMU for a specific device */
909 amd_iommu_rlookup_table = (void *)__get_free_pages(GFP_KERNEL,
910 get_order(rlookup_table_size));
911 if (amd_iommu_rlookup_table == NULL)
915 * Protection Domain table - maps devices to protection domains
916 * This table has the same size as the rlookup_table
918 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL,
919 get_order(rlookup_table_size));
920 if (amd_iommu_pd_table == NULL)
923 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(GFP_KERNEL,
924 get_order(MAX_DOMAIN_ID/8));
925 if (amd_iommu_pd_alloc_bitmap == NULL)
929 * memory is allocated now; initialize the device table with all zeroes
930 * and let all alias entries point to itself
932 memset(amd_iommu_dev_table, 0, dev_table_size);
933 for (i = 0; i < amd_iommu_last_bdf; ++i)
934 amd_iommu_alias_table[i] = i;
936 memset(amd_iommu_pd_table, 0, rlookup_table_size);
937 memset(amd_iommu_pd_alloc_bitmap, 0, MAX_DOMAIN_ID / 8);
940 * never allocate domain 0 because its used as the non-allocated and
941 * error value placeholder
943 amd_iommu_pd_alloc_bitmap[0] = 1;
946 * now the data structures are allocated and basically initialized
947 * start the real acpi table scan
950 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
953 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
956 ret = amd_iommu_init_dma_ops();
960 ret = sysdev_class_register(&amd_iommu_sysdev_class);
964 ret = sysdev_register(&device_amd_iommu);
970 printk(KERN_INFO "AMD IOMMU: aperture size is %d MB\n",
971 (1 << (amd_iommu_aperture_order-20)));
973 printk(KERN_INFO "AMD IOMMU: device isolation ");
974 if (amd_iommu_isolate)
977 printk("disabled\n");
983 if (amd_iommu_pd_alloc_bitmap)
984 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap, 1);
986 if (amd_iommu_pd_table)
987 free_pages((unsigned long)amd_iommu_pd_table,
988 get_order(rlookup_table_size));
990 if (amd_iommu_rlookup_table)
991 free_pages((unsigned long)amd_iommu_rlookup_table,
992 get_order(rlookup_table_size));
994 if (amd_iommu_alias_table)
995 free_pages((unsigned long)amd_iommu_alias_table,
996 get_order(alias_table_size));
998 if (amd_iommu_dev_table)
999 free_pages((unsigned long)amd_iommu_dev_table,
1000 get_order(dev_table_size));
1009 /****************************************************************************
1011 * Early detect code. This code runs at IOMMU detection time in the DMA
1012 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1015 ****************************************************************************/
1016 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1021 void __init amd_iommu_detect(void)
1023 if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture))
1026 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1028 amd_iommu_detected = 1;
1029 #ifdef CONFIG_GART_IOMMU
1030 gart_iommu_aperture_disabled = 1;
1031 gart_iommu_aperture = 0;
1036 /****************************************************************************
1038 * Parsing functions for the AMD IOMMU specific kernel command line
1041 ****************************************************************************/
1043 static int __init parse_amd_iommu_options(char *str)
1045 for (; *str; ++str) {
1046 if (strcmp(str, "isolate") == 0)
1047 amd_iommu_isolate = 1;
1053 static int __init parse_amd_iommu_size_options(char *str)
1055 for (; *str; ++str) {
1056 if (strcmp(str, "32M") == 0)
1057 amd_iommu_aperture_order = 25;
1058 if (strcmp(str, "64M") == 0)
1059 amd_iommu_aperture_order = 26;
1060 if (strcmp(str, "128M") == 0)
1061 amd_iommu_aperture_order = 27;
1062 if (strcmp(str, "256M") == 0)
1063 amd_iommu_aperture_order = 28;
1064 if (strcmp(str, "512M") == 0)
1065 amd_iommu_aperture_order = 29;
1066 if (strcmp(str, "1G") == 0)
1067 amd_iommu_aperture_order = 30;
1073 __setup("amd_iommu=", parse_amd_iommu_options);
1074 __setup("amd_iommu_size=", parse_amd_iommu_size_options);