2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
49 #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
50 # error SPURIOUS_APIC_VECTOR definition error
53 unsigned long mp_lapic_addr;
56 * Knob to control our willingness to enable the local APIC.
60 static int force_enable_local_apic;
63 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
64 static int disable_apic_timer __cpuinitdata;
65 /* Local APIC timer works in C2 */
66 int local_apic_timer_c2_ok;
67 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
69 int first_system_vector = 0xfe;
71 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
74 * Debug level, exported for io_apic.c
76 unsigned int apic_verbosity;
80 /* Have we found an MP table */
83 static struct resource lapic_resource = {
85 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
88 static unsigned int calibration_result;
90 static int lapic_next_event(unsigned long delta,
91 struct clock_event_device *evt);
92 static void lapic_timer_setup(enum clock_event_mode mode,
93 struct clock_event_device *evt);
94 static void lapic_timer_broadcast(cpumask_t mask);
95 static void apic_pm_activate(void);
98 * The local apic timer can be used for any function which is CPU local.
100 static struct clock_event_device lapic_clockevent = {
102 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
103 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
105 .set_mode = lapic_timer_setup,
106 .set_next_event = lapic_next_event,
107 .broadcast = lapic_timer_broadcast,
111 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
113 /* Local APIC was disabled by the BIOS and enabled by the kernel */
114 static int enabled_via_apicbase;
116 static unsigned long apic_phys;
119 * Get the LAPIC version
121 static inline int lapic_get_version(void)
123 return GET_APIC_VERSION(apic_read(APIC_LVR));
127 * Check, if the APIC is integrated or a separate chip
129 static inline int lapic_is_integrated(void)
131 return APIC_INTEGRATED(lapic_get_version());
135 * Check, whether this is a modern or a first generation APIC
137 static int modern_apic(void)
139 /* AMD systems use old APIC versions, so check the CPU */
140 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
141 boot_cpu_data.x86 >= 0xf)
143 return lapic_get_version() >= 0x14;
147 * Paravirt kernels also might be using these below ops. So we still
148 * use generic apic_read()/apic_write(), which might be pointing to different
149 * ops in PARAVIRT case.
151 void xapic_wait_icr_idle(void)
153 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
157 u32 safe_xapic_wait_icr_idle(void)
164 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
168 } while (timeout++ < 1000);
173 void xapic_icr_write(u32 low, u32 id)
175 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
176 apic_write(APIC_ICR, low);
179 u64 xapic_icr_read(void)
183 icr2 = apic_read(APIC_ICR2);
184 icr1 = apic_read(APIC_ICR);
186 return icr1 | ((u64)icr2 << 32);
189 static struct apic_ops xapic_ops = {
190 .read = native_apic_mem_read,
191 .write = native_apic_mem_write,
192 .icr_read = xapic_icr_read,
193 .icr_write = xapic_icr_write,
194 .wait_icr_idle = xapic_wait_icr_idle,
195 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
198 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
199 EXPORT_SYMBOL_GPL(apic_ops);
202 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
204 void __cpuinit enable_NMI_through_LVT0(void)
208 /* unmask and set to NMI */
211 /* Level triggered for 82489DX (32bit mode) */
212 if (!lapic_is_integrated())
213 v |= APIC_LVT_LEVEL_TRIGGER;
215 apic_write(APIC_LVT0, v);
219 * get_physical_broadcast - Get number of physical broadcast IDs
221 int get_physical_broadcast(void)
223 return modern_apic() ? 0xff : 0xf;
227 * lapic_get_maxlvt - get the maximum number of local vector table entries
229 int lapic_get_maxlvt(void)
233 v = apic_read(APIC_LVR);
235 * - we always have APIC integrated on 64bit mode
236 * - 82489DXs do not report # of LVT entries
238 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
245 /* Clock divisor is set to 16 */
246 #define APIC_DIVISOR 16
249 * This function sets up the local APIC timer, with a timeout of
250 * 'clocks' APIC bus clock. During calibration we actually call
251 * this function twice on the boot CPU, once with a bogus timeout
252 * value, second time for real. The other (noncalibrating) CPUs
253 * call this function only once, with the real, calibrated value.
255 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
257 unsigned int lvtt_value, tmp_value;
259 lvtt_value = LOCAL_TIMER_VECTOR;
261 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
262 if (!lapic_is_integrated())
263 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
266 lvtt_value |= APIC_LVT_MASKED;
268 apic_write(APIC_LVTT, lvtt_value);
273 tmp_value = apic_read(APIC_TDCR);
274 apic_write(APIC_TDCR,
275 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
279 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
283 * Program the next event, relative to now
285 static int lapic_next_event(unsigned long delta,
286 struct clock_event_device *evt)
288 apic_write(APIC_TMICT, delta);
293 * Setup the lapic timer in periodic or oneshot mode
295 static void lapic_timer_setup(enum clock_event_mode mode,
296 struct clock_event_device *evt)
301 /* Lapic used for broadcast ? */
302 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
305 local_irq_save(flags);
308 case CLOCK_EVT_MODE_PERIODIC:
309 case CLOCK_EVT_MODE_ONESHOT:
310 __setup_APIC_LVTT(calibration_result,
311 mode != CLOCK_EVT_MODE_PERIODIC, 1);
313 case CLOCK_EVT_MODE_UNUSED:
314 case CLOCK_EVT_MODE_SHUTDOWN:
315 v = apic_read(APIC_LVTT);
316 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
317 apic_write(APIC_LVTT, v);
319 case CLOCK_EVT_MODE_RESUME:
320 /* Nothing to do here */
324 local_irq_restore(flags);
328 * Local APIC timer broadcast function
330 static void lapic_timer_broadcast(cpumask_t mask)
333 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
338 * Setup the local APIC timer for this CPU. Copy the initilized values
339 * of the boot CPU and register the clock event in the framework.
341 static void __devinit setup_APIC_timer(void)
343 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
345 memcpy(levt, &lapic_clockevent, sizeof(*levt));
346 levt->cpumask = cpumask_of_cpu(smp_processor_id());
348 clockevents_register_device(levt);
352 * In this functions we calibrate APIC bus clocks to the external timer.
354 * We want to do the calibration only once since we want to have local timer
355 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
358 * This was previously done by reading the PIT/HPET and waiting for a wrap
359 * around to find out, that a tick has elapsed. I have a box, where the PIT
360 * readout is broken, so it never gets out of the wait loop again. This was
361 * also reported by others.
363 * Monitoring the jiffies value is inaccurate and the clockevents
364 * infrastructure allows us to do a simple substitution of the interrupt
367 * The calibration routine also uses the pm_timer when possible, as the PIT
368 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
369 * back to normal later in the boot process).
372 #define LAPIC_CAL_LOOPS (HZ/10)
374 static __initdata int lapic_cal_loops = -1;
375 static __initdata long lapic_cal_t1, lapic_cal_t2;
376 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
377 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
378 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
381 * Temporary interrupt handler.
383 static void __init lapic_cal_handler(struct clock_event_device *dev)
385 unsigned long long tsc = 0;
386 long tapic = apic_read(APIC_TMCCT);
387 unsigned long pm = acpi_pm_read_early();
392 switch (lapic_cal_loops++) {
394 lapic_cal_t1 = tapic;
395 lapic_cal_tsc1 = tsc;
397 lapic_cal_j1 = jiffies;
400 case LAPIC_CAL_LOOPS:
401 lapic_cal_t2 = tapic;
402 lapic_cal_tsc2 = tsc;
403 if (pm < lapic_cal_pm1)
404 pm += ACPI_PM_OVRRUN;
406 lapic_cal_j2 = jiffies;
411 static int __init calibrate_APIC_clock(void)
413 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
414 const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
415 const long pm_thresh = pm_100ms/100;
416 void (*real_handler)(struct clock_event_device *dev);
417 unsigned long deltaj;
419 int pm_referenced = 0;
423 /* Replace the global interrupt handler */
424 real_handler = global_clock_event->event_handler;
425 global_clock_event->event_handler = lapic_cal_handler;
428 * Setup the APIC counter to 1e9. There is no way the lapic
429 * can underflow in the 100ms detection time frame
431 __setup_APIC_LVTT(1000000000, 0, 0);
433 /* Let the interrupts run */
436 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
441 /* Restore the real event handler */
442 global_clock_event->event_handler = real_handler;
444 /* Build delta t1-t2 as apic timer counts down */
445 delta = lapic_cal_t1 - lapic_cal_t2;
446 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
448 /* Check, if the PM timer is available */
449 deltapm = lapic_cal_pm2 - lapic_cal_pm1;
450 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
456 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
458 if (deltapm > (pm_100ms - pm_thresh) &&
459 deltapm < (pm_100ms + pm_thresh)) {
460 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
462 res = (((u64) deltapm) * mult) >> 22;
463 do_div(res, 1000000);
464 printk(KERN_WARNING "APIC calibration not consistent "
465 "with PM Timer: %ldms instead of 100ms\n",
467 /* Correct the lapic counter value */
468 res = (((u64) delta) * pm_100ms);
469 do_div(res, deltapm);
470 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
471 "%lu (%ld)\n", (unsigned long) res, delta);
477 /* Calculate the scaled math multiplication factor */
478 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
479 lapic_clockevent.shift);
480 lapic_clockevent.max_delta_ns =
481 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
482 lapic_clockevent.min_delta_ns =
483 clockevent_delta2ns(0xF, &lapic_clockevent);
485 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
487 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
488 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
489 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
493 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
494 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
496 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
497 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
500 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
502 calibration_result / (1000000 / HZ),
503 calibration_result % (1000000 / HZ));
506 * Do a sanity check on the APIC calibration result
508 if (calibration_result < (1000000 / HZ)) {
511 "APIC frequency too slow, disabling apic timer\n");
515 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
517 /* We trust the pm timer based calibration */
518 if (!pm_referenced) {
519 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
522 * Setup the apic timer manually
524 levt->event_handler = lapic_cal_handler;
525 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
526 lapic_cal_loops = -1;
528 /* Let the interrupts run */
531 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
536 /* Stop the lapic timer */
537 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
542 deltaj = lapic_cal_j2 - lapic_cal_j1;
543 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
545 /* Check, if the jiffies result is consistent */
546 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
547 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
549 levt->features |= CLOCK_EVT_FEAT_DUMMY;
553 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
555 "APIC timer disabled due to verification failure.\n");
563 * Setup the boot APIC
565 * Calibrate and verify the result.
567 void __init setup_boot_APIC_clock(void)
570 * The local apic timer can be disabled via the kernel
571 * commandline or from the CPU detection code. Register the lapic
572 * timer as a dummy clock event source on SMP systems, so the
573 * broadcast mechanism is used. On UP systems simply ignore it.
575 if (disable_apic_timer) {
576 /* No broadcast on UP ! */
577 if (num_possible_cpus() > 1) {
578 lapic_clockevent.mult = 1;
584 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
585 "calibrating APIC timer ...\n");
587 if (calibrate_APIC_clock()) {
588 /* No broadcast on UP ! */
589 if (num_possible_cpus() > 1)
595 * If nmi_watchdog is set to IO_APIC, we need the
596 * PIT/HPET going. Otherwise register lapic as a dummy
599 if (nmi_watchdog != NMI_IO_APIC)
600 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
602 printk(KERN_WARNING "APIC timer registered as dummy,"
603 " due to nmi_watchdog=%d!\n", nmi_watchdog);
605 /* Setup the lapic or request the broadcast */
609 void __devinit setup_secondary_APIC_clock(void)
615 * The guts of the apic timer interrupt
617 static void local_apic_timer_interrupt(void)
619 int cpu = smp_processor_id();
620 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
623 * Normally we should not be here till LAPIC has been initialized but
624 * in some cases like kdump, its possible that there is a pending LAPIC
625 * timer interrupt from previous kernel's context and is delivered in
626 * new kernel the moment interrupts are enabled.
628 * Interrupts are enabled early and LAPIC is setup much later, hence
629 * its possible that when we get here evt->event_handler is NULL.
630 * Check for event_handler being NULL and discard the interrupt as
633 if (!evt->event_handler) {
635 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
637 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
642 * the NMI deadlock-detector uses this.
644 per_cpu(irq_stat, cpu).apic_timer_irqs++;
646 evt->event_handler(evt);
650 * Local APIC timer interrupt. This is the most natural way for doing
651 * local interrupts, but local timer interrupts can be emulated by
652 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
654 * [ if a single-CPU system runs an SMP kernel then we call the local
655 * interrupt as well. Thus we cannot inline the local irq ... ]
657 void smp_apic_timer_interrupt(struct pt_regs *regs)
659 struct pt_regs *old_regs = set_irq_regs(regs);
662 * NOTE! We'd better ACK the irq immediately,
663 * because timer handling can be slow.
667 * update_process_times() expects us to have done irq_enter().
668 * Besides, if we don't timer interrupts ignore the global
669 * interrupt lock, which is the WrongThing (tm) to do.
672 local_apic_timer_interrupt();
675 set_irq_regs(old_regs);
678 int setup_profiling_timer(unsigned int multiplier)
684 * Setup extended LVT, AMD specific (K8, family 10h)
686 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
687 * MCE interrupts are supported. Thus MCE offset must be set to 0.
690 #define APIC_EILVT_LVTOFF_MCE 0
691 #define APIC_EILVT_LVTOFF_IBS 1
693 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
695 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
696 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
700 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
702 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
703 return APIC_EILVT_LVTOFF_MCE;
706 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
708 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
709 return APIC_EILVT_LVTOFF_IBS;
713 * Local APIC start and shutdown
717 * clear_local_APIC - shutdown the local APIC
719 * This is called, when a CPU is disabled and before rebooting, so the state of
720 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
721 * leftovers during boot.
723 void clear_local_APIC(void)
728 /* APIC hasn't been mapped yet */
732 maxlvt = lapic_get_maxlvt();
734 * Masking an LVT entry can trigger a local APIC error
735 * if the vector is zero. Mask LVTERR first to prevent this.
738 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
739 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
742 * Careful: we have to set masks only first to deassert
743 * any level-triggered sources.
745 v = apic_read(APIC_LVTT);
746 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
747 v = apic_read(APIC_LVT0);
748 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
749 v = apic_read(APIC_LVT1);
750 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
752 v = apic_read(APIC_LVTPC);
753 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
756 /* lets not touch this if we didn't frob it */
757 #ifdef CONFIG_X86_MCE_P4THERMAL
759 v = apic_read(APIC_LVTTHMR);
760 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
764 * Clean APIC state for other OSs:
766 apic_write(APIC_LVTT, APIC_LVT_MASKED);
767 apic_write(APIC_LVT0, APIC_LVT_MASKED);
768 apic_write(APIC_LVT1, APIC_LVT_MASKED);
770 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
772 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
774 #ifdef CONFIG_X86_MCE_P4THERMAL
776 apic_write(APIC_LVTTHMR, APIC_LVT_MASKED);
778 /* Integrated APIC (!82489DX) ? */
779 if (lapic_is_integrated()) {
781 /* Clear ESR due to Pentium errata 3AP and 11AP */
782 apic_write(APIC_ESR, 0);
788 * disable_local_APIC - clear and disable the local APIC
790 void disable_local_APIC(void)
797 * Disable APIC (implies clearing of registers
800 value = apic_read(APIC_SPIV);
801 value &= ~APIC_SPIV_APIC_ENABLED;
802 apic_write(APIC_SPIV, value);
805 * When LAPIC was disabled by the BIOS and enabled by the kernel,
806 * restore the disabled state.
808 if (enabled_via_apicbase) {
811 rdmsr(MSR_IA32_APICBASE, l, h);
812 l &= ~MSR_IA32_APICBASE_ENABLE;
813 wrmsr(MSR_IA32_APICBASE, l, h);
818 * If Linux enabled the LAPIC against the BIOS default disable it down before
819 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
820 * not power-off. Additionally clear all LVT entries before disable_local_APIC
821 * for the case where Linux didn't enable the LAPIC.
823 void lapic_shutdown(void)
830 local_irq_save(flags);
832 if (enabled_via_apicbase)
833 disable_local_APIC();
837 local_irq_restore(flags);
841 * This is to verify that we're looking at a real local APIC.
842 * Check these against your board if the CPUs aren't getting
843 * started for no apparent reason.
845 int __init verify_local_APIC(void)
847 unsigned int reg0, reg1;
850 * The version register is read-only in a real APIC.
852 reg0 = apic_read(APIC_LVR);
853 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
854 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
855 reg1 = apic_read(APIC_LVR);
856 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
859 * The two version reads above should print the same
860 * numbers. If the second one is different, then we
861 * poke at a non-APIC.
867 * Check if the version looks reasonably.
869 reg1 = GET_APIC_VERSION(reg0);
870 if (reg1 == 0x00 || reg1 == 0xff)
872 reg1 = lapic_get_maxlvt();
873 if (reg1 < 0x02 || reg1 == 0xff)
877 * The ID register is read/write in a real APIC.
879 reg0 = apic_read(APIC_ID);
880 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
881 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
882 reg1 = apic_read(APIC_ID);
883 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
884 apic_write(APIC_ID, reg0);
885 if (reg1 != (reg0 ^ APIC_ID_MASK))
889 * The next two are just to see if we have sane values.
890 * They're only really relevant if we're in Virtual Wire
891 * compatibility mode, but most boxes are anymore.
893 reg0 = apic_read(APIC_LVT0);
894 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
895 reg1 = apic_read(APIC_LVT1);
896 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
902 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
904 void __init sync_Arb_IDs(void)
907 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
910 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
915 apic_wait_icr_idle();
917 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
919 APIC_DEST_ALLINC | APIC_INT_LEVELTRIG | APIC_DM_INIT);
923 * An initial setup of the virtual wire mode.
925 void __init init_bsp_APIC(void)
930 * Don't do the setup now if we have a SMP BIOS as the
931 * through-I/O-APIC virtual wire mode might be active.
933 if (smp_found_config || !cpu_has_apic)
937 * Do not trust the local APIC being empty at bootup.
944 value = apic_read(APIC_SPIV);
945 value &= ~APIC_VECTOR_MASK;
946 value |= APIC_SPIV_APIC_ENABLED;
948 /* This bit is reserved on P4/Xeon and should be cleared */
949 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
950 (boot_cpu_data.x86 == 15))
951 value &= ~APIC_SPIV_FOCUS_DISABLED;
953 value |= APIC_SPIV_FOCUS_DISABLED;
954 value |= SPURIOUS_APIC_VECTOR;
955 apic_write(APIC_SPIV, value);
958 * Set up the virtual wire mode.
960 apic_write(APIC_LVT0, APIC_DM_EXTINT);
962 if (!lapic_is_integrated()) /* 82489DX */
963 value |= APIC_LVT_LEVEL_TRIGGER;
964 apic_write(APIC_LVT1, value);
967 static void __cpuinit lapic_setup_esr(void)
969 unsigned long oldvalue, value, maxlvt;
970 if (lapic_is_integrated() && !esr_disable) {
972 maxlvt = lapic_get_maxlvt();
973 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
974 apic_write(APIC_ESR, 0);
975 oldvalue = apic_read(APIC_ESR);
977 /* enables sending errors */
978 value = ERROR_APIC_VECTOR;
979 apic_write(APIC_LVTERR, value);
981 * spec says clear errors after enabling vector.
984 apic_write(APIC_ESR, 0);
985 value = apic_read(APIC_ESR);
986 if (value != oldvalue)
987 apic_printk(APIC_VERBOSE, "ESR value before enabling "
988 "vector: 0x%08lx after: 0x%08lx\n",
993 * Something untraceable is creating bad interrupts on
994 * secondary quads ... for the moment, just leave the
995 * ESR disabled - we can't do anything useful with the
996 * errors anyway - mbligh
998 printk(KERN_INFO "Leaving ESR disabled.\n");
1000 printk(KERN_INFO "No ESR for 82489DX.\n");
1006 * setup_local_APIC - setup the local APIC
1008 void __cpuinit setup_local_APIC(void)
1010 unsigned long value, integrated;
1013 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1015 apic_write(APIC_ESR, 0);
1016 apic_write(APIC_ESR, 0);
1017 apic_write(APIC_ESR, 0);
1018 apic_write(APIC_ESR, 0);
1021 integrated = lapic_is_integrated();
1024 * Double-check whether this APIC is really registered.
1026 if (!apic_id_registered())
1030 * Intel recommends to set DFR, LDR and TPR before enabling
1031 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1032 * document number 292116). So here it goes...
1037 * Set Task Priority to 'accept all'. We never change this
1040 value = apic_read(APIC_TASKPRI);
1041 value &= ~APIC_TPRI_MASK;
1042 apic_write(APIC_TASKPRI, value);
1045 * After a crash, we no longer service the interrupts and a pending
1046 * interrupt from previous kernel might still have ISR bit set.
1048 * Most probably by now CPU has serviced that pending interrupt and
1049 * it might not have done the ack_APIC_irq() because it thought,
1050 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1051 * does not clear the ISR bit and cpu thinks it has already serivced
1052 * the interrupt. Hence a vector might get locked. It was noticed
1053 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1055 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1056 value = apic_read(APIC_ISR + i*0x10);
1057 for (j = 31; j >= 0; j--) {
1064 * Now that we are all set up, enable the APIC
1066 value = apic_read(APIC_SPIV);
1067 value &= ~APIC_VECTOR_MASK;
1071 value |= APIC_SPIV_APIC_ENABLED;
1074 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1075 * certain networking cards. If high frequency interrupts are
1076 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1077 * entry is masked/unmasked at a high rate as well then sooner or
1078 * later IOAPIC line gets 'stuck', no more interrupts are received
1079 * from the device. If focus CPU is disabled then the hang goes
1082 * [ This bug can be reproduced easily with a level-triggered
1083 * PCI Ne2000 networking cards and PII/PIII processors, dual
1087 * Actually disabling the focus CPU check just makes the hang less
1088 * frequent as it makes the interrupt distributon model be more
1089 * like LRU than MRU (the short-term load is more even across CPUs).
1090 * See also the comment in end_level_ioapic_irq(). --macro
1093 /* Enable focus processor (bit==0) */
1094 value &= ~APIC_SPIV_FOCUS_DISABLED;
1097 * Set spurious IRQ vector
1099 value |= SPURIOUS_APIC_VECTOR;
1100 apic_write(APIC_SPIV, value);
1103 * Set up LVT0, LVT1:
1105 * set up through-local-APIC on the BP's LINT0. This is not
1106 * strictly necessary in pure symmetric-IO mode, but sometimes
1107 * we delegate interrupts to the 8259A.
1110 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1112 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1113 if (!smp_processor_id() && (pic_mode || !value)) {
1114 value = APIC_DM_EXTINT;
1115 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1116 smp_processor_id());
1118 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1119 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1120 smp_processor_id());
1122 apic_write(APIC_LVT0, value);
1125 * only the BP should see the LINT1 NMI signal, obviously.
1127 if (!smp_processor_id())
1128 value = APIC_DM_NMI;
1130 value = APIC_DM_NMI | APIC_LVT_MASKED;
1131 if (!integrated) /* 82489DX */
1132 value |= APIC_LVT_LEVEL_TRIGGER;
1133 apic_write(APIC_LVT1, value);
1136 void __cpuinit end_local_APIC_setup(void)
1138 unsigned long value;
1141 /* Disable the local apic timer */
1142 value = apic_read(APIC_LVTT);
1143 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1144 apic_write(APIC_LVTT, value);
1146 setup_apic_nmi_watchdog(NULL);
1151 * Detect and initialize APIC
1153 static int __init detect_init_APIC(void)
1157 /* Disabled by kernel option? */
1161 switch (boot_cpu_data.x86_vendor) {
1162 case X86_VENDOR_AMD:
1163 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1164 (boot_cpu_data.x86 == 15))
1167 case X86_VENDOR_INTEL:
1168 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1169 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1176 if (!cpu_has_apic) {
1178 * Over-ride BIOS and try to enable the local APIC only if
1179 * "lapic" specified.
1181 if (!force_enable_local_apic) {
1182 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1183 "you can enable it with \"lapic\"\n");
1187 * Some BIOSes disable the local APIC in the APIC_BASE
1188 * MSR. This can only be done in software for Intel P6 or later
1189 * and AMD K7 (Model > 1) or later.
1191 rdmsr(MSR_IA32_APICBASE, l, h);
1192 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1194 "Local APIC disabled by BIOS -- reenabling.\n");
1195 l &= ~MSR_IA32_APICBASE_BASE;
1196 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1197 wrmsr(MSR_IA32_APICBASE, l, h);
1198 enabled_via_apicbase = 1;
1202 * The APIC feature bit should now be enabled
1205 features = cpuid_edx(1);
1206 if (!(features & (1 << X86_FEATURE_APIC))) {
1207 printk(KERN_WARNING "Could not enable APIC!\n");
1210 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1211 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1213 /* The BIOS may have set up the APIC at some other address */
1214 rdmsr(MSR_IA32_APICBASE, l, h);
1215 if (l & MSR_IA32_APICBASE_ENABLE)
1216 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1218 printk(KERN_INFO "Found and enabled local APIC!\n");
1225 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1230 * init_apic_mappings - initialize APIC mappings
1232 void __init init_apic_mappings(void)
1235 * If no local APIC can be found then set up a fake all
1236 * zeroes page to simulate the local APIC and another
1237 * one for the IO-APIC.
1239 if (!smp_found_config && detect_init_APIC()) {
1240 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1241 apic_phys = __pa(apic_phys);
1243 apic_phys = mp_lapic_addr;
1245 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1246 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
1250 * Fetch the APIC ID of the BSP in case we have a
1251 * default configuration (or the MP table is broken).
1253 if (boot_cpu_physical_apicid == -1U)
1254 boot_cpu_physical_apicid = read_apic_id();
1259 * This initializes the IO-APIC and APIC hardware if this is
1263 int apic_version[MAX_APICS];
1265 int __init APIC_init_uniprocessor(void)
1267 if (!smp_found_config && !cpu_has_apic)
1271 * Complain if the BIOS pretends there is one.
1273 if (!cpu_has_apic &&
1274 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1275 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1276 boot_cpu_physical_apicid);
1277 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1281 verify_local_APIC();
1286 * Hack: In case of kdump, after a crash, kernel might be booting
1287 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1288 * might be zero if read from MP tables. Get it from LAPIC.
1290 #ifdef CONFIG_CRASH_DUMP
1291 boot_cpu_physical_apicid = read_apic_id();
1293 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1297 #ifdef CONFIG_X86_IO_APIC
1298 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1300 localise_nmi_watchdog();
1301 end_local_APIC_setup();
1302 #ifdef CONFIG_X86_IO_APIC
1303 if (smp_found_config)
1304 if (!skip_ioapic_setup && nr_ioapics)
1313 * Local APIC interrupts
1317 * This interrupt should _never_ happen with our APIC/SMP architecture
1319 void smp_spurious_interrupt(struct pt_regs *regs)
1325 * Check if this really is a spurious interrupt and ACK it
1326 * if it is a vectored one. Just in case...
1327 * Spurious interrupts should not be ACKed.
1329 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1330 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1333 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1334 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1335 "should never happen.\n", smp_processor_id());
1336 __get_cpu_var(irq_stat).irq_spurious_count++;
1341 * This interrupt should never happen with our APIC/SMP architecture
1343 void smp_error_interrupt(struct pt_regs *regs)
1345 unsigned long v, v1;
1348 /* First tickle the hardware, only then report what went on. -- REW */
1349 v = apic_read(APIC_ESR);
1350 apic_write(APIC_ESR, 0);
1351 v1 = apic_read(APIC_ESR);
1353 atomic_inc(&irq_err_count);
1355 /* Here is what the APIC error bits mean:
1358 2: Send accept error
1359 3: Receive accept error
1361 5: Send illegal vector
1362 6: Received illegal vector
1363 7: Illegal register address
1365 printk(KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1366 smp_processor_id(), v , v1);
1371 * connect_bsp_APIC - attach the APIC to the interrupt system
1373 void __init connect_bsp_APIC(void)
1377 * Do not trust the local APIC being empty at bootup.
1381 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1382 * local APIC to INT and NMI lines.
1384 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1385 "enabling APIC mode.\n");
1393 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1394 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1396 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1399 void disconnect_bsp_APIC(int virt_wire_setup)
1403 * Put the board back into PIC mode (has an effect only on
1404 * certain older boards). Note that APIC interrupts, including
1405 * IPIs, won't work beyond this point! The only exception are
1408 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1409 "entering PIC mode.\n");
1413 /* Go back to Virtual Wire compatibility mode */
1414 unsigned long value;
1416 /* For the spurious interrupt use vector F, and enable it */
1417 value = apic_read(APIC_SPIV);
1418 value &= ~APIC_VECTOR_MASK;
1419 value |= APIC_SPIV_APIC_ENABLED;
1421 apic_write(APIC_SPIV, value);
1423 if (!virt_wire_setup) {
1425 * For LVT0 make it edge triggered, active high,
1426 * external and enabled
1428 value = apic_read(APIC_LVT0);
1429 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1430 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1431 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1432 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1433 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1434 apic_write(APIC_LVT0, value);
1437 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1441 * For LVT1 make it edge triggered, active high, nmi and
1444 value = apic_read(APIC_LVT1);
1446 APIC_MODE_MASK | APIC_SEND_PENDING |
1447 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1448 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1449 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1450 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1451 apic_write(APIC_LVT1, value);
1455 unsigned int __cpuinitdata maxcpus = NR_CPUS;
1457 void __cpuinit generic_processor_info(int apicid, int version)
1461 physid_mask_t phys_cpu;
1466 if (version == 0x0) {
1467 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1468 "fixing up to 0x10. (tell your hw vendor)\n",
1472 apic_version[apicid] = version;
1474 phys_cpu = apicid_to_cpu_present(apicid);
1475 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
1477 if (num_processors >= NR_CPUS) {
1478 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1479 " Processor ignored.\n", NR_CPUS);
1483 if (num_processors >= maxcpus) {
1484 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
1485 " Processor ignored.\n", maxcpus);
1490 cpus_complement(tmp_map, cpu_present_map);
1491 cpu = first_cpu(tmp_map);
1493 if (apicid == boot_cpu_physical_apicid)
1495 * x86_bios_cpu_apicid is required to have processors listed
1496 * in same order as logical cpu numbers. Hence the first
1497 * entry is BSP, and so on.
1501 if (apicid > max_physical_apicid)
1502 max_physical_apicid = apicid;
1505 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1506 * but we need to work other dependencies like SMP_SUSPEND etc
1507 * before this can be done without some confusion.
1508 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1509 * - Ashok Raj <ashok.raj@intel.com>
1511 if (max_physical_apicid >= 8) {
1512 switch (boot_cpu_data.x86_vendor) {
1513 case X86_VENDOR_INTEL:
1514 if (!APIC_XAPIC(version)) {
1518 /* If P4 and above fall through */
1519 case X86_VENDOR_AMD:
1524 /* are we being called early in kernel startup? */
1525 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1526 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1527 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1529 cpu_to_apicid[cpu] = apicid;
1530 bios_cpu_apicid[cpu] = apicid;
1532 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1533 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1536 cpu_set(cpu, cpu_possible_map);
1537 cpu_set(cpu, cpu_present_map);
1547 /* r/w apic fields */
1548 unsigned int apic_id;
1549 unsigned int apic_taskpri;
1550 unsigned int apic_ldr;
1551 unsigned int apic_dfr;
1552 unsigned int apic_spiv;
1553 unsigned int apic_lvtt;
1554 unsigned int apic_lvtpc;
1555 unsigned int apic_lvt0;
1556 unsigned int apic_lvt1;
1557 unsigned int apic_lvterr;
1558 unsigned int apic_tmict;
1559 unsigned int apic_tdcr;
1560 unsigned int apic_thmr;
1563 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1565 unsigned long flags;
1568 if (!apic_pm_state.active)
1571 maxlvt = lapic_get_maxlvt();
1573 apic_pm_state.apic_id = apic_read(APIC_ID);
1574 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1575 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1576 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1577 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1578 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1580 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1581 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1582 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1583 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1584 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1585 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1586 #ifdef CONFIG_X86_MCE_P4THERMAL
1588 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1591 local_irq_save(flags);
1592 disable_local_APIC();
1593 local_irq_restore(flags);
1597 static int lapic_resume(struct sys_device *dev)
1600 unsigned long flags;
1603 if (!apic_pm_state.active)
1606 maxlvt = lapic_get_maxlvt();
1608 local_irq_save(flags);
1611 * Make sure the APICBASE points to the right address
1613 * FIXME! This will be wrong if we ever support suspend on
1614 * SMP! We'll need to do this as part of the CPU restore!
1616 rdmsr(MSR_IA32_APICBASE, l, h);
1617 l &= ~MSR_IA32_APICBASE_BASE;
1618 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1619 wrmsr(MSR_IA32_APICBASE, l, h);
1621 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1622 apic_write(APIC_ID, apic_pm_state.apic_id);
1623 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1624 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1625 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1626 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1627 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1628 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1629 #ifdef CONFIG_X86_MCE_P4THERMAL
1631 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1634 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1635 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1636 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1637 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1638 apic_write(APIC_ESR, 0);
1639 apic_read(APIC_ESR);
1640 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1641 apic_write(APIC_ESR, 0);
1642 apic_read(APIC_ESR);
1643 local_irq_restore(flags);
1648 * This device has no shutdown method - fully functioning local APICs
1649 * are needed on every CPU up until machine_halt/restart/poweroff.
1652 static struct sysdev_class lapic_sysclass = {
1654 .resume = lapic_resume,
1655 .suspend = lapic_suspend,
1658 static struct sys_device device_lapic = {
1660 .cls = &lapic_sysclass,
1663 static void __devinit apic_pm_activate(void)
1665 apic_pm_state.active = 1;
1668 static int __init init_lapic_sysfs(void)
1674 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1676 error = sysdev_class_register(&lapic_sysclass);
1678 error = sysdev_register(&device_lapic);
1681 device_initcall(init_lapic_sysfs);
1683 #else /* CONFIG_PM */
1685 static void apic_pm_activate(void) { }
1687 #endif /* CONFIG_PM */
1690 * APIC command line parameters
1692 static int __init parse_lapic(char *arg)
1694 force_enable_local_apic = 1;
1697 early_param("lapic", parse_lapic);
1699 static int __init parse_nolapic(char *arg)
1702 setup_clear_cpu_cap(X86_FEATURE_APIC);
1705 early_param("nolapic", parse_nolapic);
1707 static int __init parse_disable_apic_timer(char *arg)
1709 disable_apic_timer = 1;
1712 early_param("noapictimer", parse_disable_apic_timer);
1714 static int __init parse_nolapic_timer(char *arg)
1716 disable_apic_timer = 1;
1719 early_param("nolapic_timer", parse_nolapic_timer);
1721 static int __init parse_lapic_timer_c2_ok(char *arg)
1723 local_apic_timer_c2_ok = 1;
1726 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1728 static int __init apic_set_verbosity(char *arg)
1733 if (strcmp(arg, "debug") == 0)
1734 apic_verbosity = APIC_DEBUG;
1735 else if (strcmp(arg, "verbose") == 0)
1736 apic_verbosity = APIC_VERBOSE;
1740 early_param("apic", apic_set_verbosity);
1742 static int __init lapic_insert_resource(void)
1747 /* Put local APIC into the resource map. */
1748 lapic_resource.start = apic_phys;
1749 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1750 insert_resource(&iomem_resource, &lapic_resource);
1756 * need call insert after e820_reserve_resources()
1757 * that is using request_resource
1759 late_initcall(lapic_insert_resource);