2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/pgalloc.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
43 #include <asm/i8259.h>
46 #include <mach_apic.h>
48 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
49 static int disable_apic_timer __cpuinitdata;
50 static int apic_calibrate_pmtmr __initdata;
55 /* x2apic enabled before OS handover */
56 int x2apic_preenabled;
58 /* Local APIC timer works in C2 */
59 int local_apic_timer_c2_ok;
60 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
63 * Debug level, exported for io_apic.c
65 unsigned int apic_verbosity;
67 /* Have we found an MP table */
70 static struct resource lapic_resource = {
72 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
75 static unsigned int calibration_result;
77 static int lapic_next_event(unsigned long delta,
78 struct clock_event_device *evt);
79 static void lapic_timer_setup(enum clock_event_mode mode,
80 struct clock_event_device *evt);
81 static void lapic_timer_broadcast(cpumask_t mask);
82 static void apic_pm_activate(void);
85 * The local apic timer can be used for any function which is CPU local.
87 static struct clock_event_device lapic_clockevent = {
89 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
90 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
92 .set_mode = lapic_timer_setup,
93 .set_next_event = lapic_next_event,
94 .broadcast = lapic_timer_broadcast,
98 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
100 static unsigned long apic_phys;
102 unsigned long mp_lapic_addr;
104 unsigned int __cpuinitdata maxcpus = NR_CPUS;
106 * Get the LAPIC version
108 static inline int lapic_get_version(void)
110 return GET_APIC_VERSION(apic_read(APIC_LVR));
114 * Check, if the APIC is integrated or a seperate chip
116 static inline int lapic_is_integrated(void)
122 * Check, whether this is a modern or a first generation APIC
124 static int modern_apic(void)
126 /* AMD systems use old APIC versions, so check the CPU */
127 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
128 boot_cpu_data.x86 >= 0xf)
130 return lapic_get_version() >= 0x14;
134 * Paravirt kernels also might be using these below ops. So we still
135 * use generic apic_read()/apic_write(), which might be pointing to different
136 * ops in PARAVIRT case.
138 void xapic_wait_icr_idle(void)
140 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
144 u32 safe_xapic_wait_icr_idle(void)
151 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
155 } while (timeout++ < 1000);
160 void xapic_icr_write(u32 low, u32 id)
162 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
163 apic_write(APIC_ICR, low);
166 u64 xapic_icr_read(void)
170 icr2 = apic_read(APIC_ICR2);
171 icr1 = apic_read(APIC_ICR);
173 return (icr1 | ((u64)icr2 << 32));
176 static struct apic_ops xapic_ops = {
177 .read = native_apic_mem_read,
178 .write = native_apic_mem_write,
179 .icr_read = xapic_icr_read,
180 .icr_write = xapic_icr_write,
181 .wait_icr_idle = xapic_wait_icr_idle,
182 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
185 struct apic_ops __read_mostly *apic_ops = &xapic_ops;
186 EXPORT_SYMBOL_GPL(apic_ops);
188 static void x2apic_wait_icr_idle(void)
190 /* no need to wait for icr idle in x2apic */
194 static u32 safe_x2apic_wait_icr_idle(void)
196 /* no need to wait for icr idle in x2apic */
200 void x2apic_icr_write(u32 low, u32 id)
202 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
205 u64 x2apic_icr_read(void)
209 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
213 static struct apic_ops x2apic_ops = {
214 .read = native_apic_msr_read,
215 .write = native_apic_msr_write,
216 .icr_read = x2apic_icr_read,
217 .icr_write = x2apic_icr_write,
218 .wait_icr_idle = x2apic_wait_icr_idle,
219 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
223 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
225 void __cpuinit enable_NMI_through_LVT0(void)
229 /* unmask and set to NMI */
232 /* Level triggered for 82489DX (32bit mode) */
233 if (!lapic_is_integrated())
234 v |= APIC_LVT_LEVEL_TRIGGER;
236 apic_write(APIC_LVT0, v);
240 * lapic_get_maxlvt - get the maximum number of local vector table entries
242 int lapic_get_maxlvt(void)
246 v = apic_read(APIC_LVR);
248 * - we always have APIC integrated on 64bit mode
249 * - 82489DXs do not report # of LVT entries
251 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
258 /* Clock divisor is set to 1 */
259 #define APIC_DIVISOR 1
262 * This function sets up the local APIC timer, with a timeout of
263 * 'clocks' APIC bus clock. During calibration we actually call
264 * this function twice on the boot CPU, once with a bogus timeout
265 * value, second time for real. The other (noncalibrating) CPUs
266 * call this function only once, with the real, calibrated value.
268 * We do reads before writes even if unnecessary, to get around the
269 * P5 APIC double write bug.
271 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
273 unsigned int lvtt_value, tmp_value;
275 lvtt_value = LOCAL_TIMER_VECTOR;
277 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
278 if (!lapic_is_integrated())
279 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
282 lvtt_value |= APIC_LVT_MASKED;
284 apic_write(APIC_LVTT, lvtt_value);
289 tmp_value = apic_read(APIC_TDCR);
290 apic_write(APIC_TDCR, (tmp_value
291 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
295 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
299 * Setup extended LVT, AMD specific (K8, family 10h)
301 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
302 * MCE interrupts are supported. Thus MCE offset must be set to 0.
305 #define APIC_EILVT_LVTOFF_MCE 0
306 #define APIC_EILVT_LVTOFF_IBS 1
308 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
310 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
311 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
316 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
318 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
319 return APIC_EILVT_LVTOFF_MCE;
322 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
324 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
325 return APIC_EILVT_LVTOFF_IBS;
329 * Program the next event, relative to now
331 static int lapic_next_event(unsigned long delta,
332 struct clock_event_device *evt)
334 apic_write(APIC_TMICT, delta);
339 * Setup the lapic timer in periodic or oneshot mode
341 static void lapic_timer_setup(enum clock_event_mode mode,
342 struct clock_event_device *evt)
347 /* Lapic used as dummy for broadcast ? */
348 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
351 local_irq_save(flags);
354 case CLOCK_EVT_MODE_PERIODIC:
355 case CLOCK_EVT_MODE_ONESHOT:
356 __setup_APIC_LVTT(calibration_result,
357 mode != CLOCK_EVT_MODE_PERIODIC, 1);
359 case CLOCK_EVT_MODE_UNUSED:
360 case CLOCK_EVT_MODE_SHUTDOWN:
361 v = apic_read(APIC_LVTT);
362 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
363 apic_write(APIC_LVTT, v);
365 case CLOCK_EVT_MODE_RESUME:
366 /* Nothing to do here */
370 local_irq_restore(flags);
374 * Local APIC timer broadcast function
376 static void lapic_timer_broadcast(cpumask_t mask)
379 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
384 * Setup the local APIC timer for this CPU. Copy the initilized values
385 * of the boot CPU and register the clock event in the framework.
387 static void setup_APIC_timer(void)
389 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
391 memcpy(levt, &lapic_clockevent, sizeof(*levt));
392 levt->cpumask = cpumask_of_cpu(smp_processor_id());
394 clockevents_register_device(levt);
398 * In this function we calibrate APIC bus clocks to the external
399 * timer. Unfortunately we cannot use jiffies and the timer irq
400 * to calibrate, since some later bootup code depends on getting
401 * the first irq? Ugh.
403 * We want to do the calibration only once since we
404 * want to have local timer irqs syncron. CPUs connected
405 * by the same APIC bus have the very same bus frequency.
406 * And we want to have irqs off anyways, no accidental
410 #define TICK_COUNT 100000000
412 static int __init calibrate_APIC_clock(void)
414 unsigned apic, apic_start;
415 unsigned long tsc, tsc_start;
421 * Put whatever arbitrary (but long enough) timeout
422 * value into the APIC clock, we just want to get the
423 * counter running for calibration.
425 * No interrupt enable !
427 __setup_APIC_LVTT(250000000, 0, 0);
429 apic_start = apic_read(APIC_TMCCT);
430 #ifdef CONFIG_X86_PM_TIMER
431 if (apic_calibrate_pmtmr && pmtmr_ioport) {
432 pmtimer_wait(5000); /* 5ms wait */
433 apic = apic_read(APIC_TMCCT);
434 result = (apic_start - apic) * 1000L / 5;
441 apic = apic_read(APIC_TMCCT);
443 } while ((tsc - tsc_start) < TICK_COUNT &&
444 (apic_start - apic) < TICK_COUNT);
446 result = (apic_start - apic) * 1000L * tsc_khz /
452 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
454 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
455 result / 1000 / 1000, result / 1000 % 1000);
457 /* Calculate the scaled math multiplication factor */
458 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
459 lapic_clockevent.shift);
460 lapic_clockevent.max_delta_ns =
461 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
462 lapic_clockevent.min_delta_ns =
463 clockevent_delta2ns(0xF, &lapic_clockevent);
465 calibration_result = (result * APIC_DIVISOR) / HZ;
468 * Do a sanity check on the APIC calibration result
470 if (calibration_result < (1000000 / HZ)) {
472 "APIC frequency too slow, disabling apic timer\n");
480 * Setup the boot APIC
482 * Calibrate and verify the result.
484 void __init setup_boot_APIC_clock(void)
487 * The local apic timer can be disabled via the kernel
488 * commandline or from the CPU detection code. Register the lapic
489 * timer as a dummy clock event source on SMP systems, so the
490 * broadcast mechanism is used. On UP systems simply ignore it.
492 if (disable_apic_timer) {
493 printk(KERN_INFO "Disabling APIC timer\n");
494 /* No broadcast on UP ! */
495 if (num_possible_cpus() > 1) {
496 lapic_clockevent.mult = 1;
502 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
503 "calibrating APIC timer ...\n");
505 if (calibrate_APIC_clock()) {
506 /* No broadcast on UP ! */
507 if (num_possible_cpus() > 1)
513 * If nmi_watchdog is set to IO_APIC, we need the
514 * PIT/HPET going. Otherwise register lapic as a dummy
517 if (nmi_watchdog != NMI_IO_APIC)
518 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
520 printk(KERN_WARNING "APIC timer registered as dummy,"
521 " due to nmi_watchdog=%d!\n", nmi_watchdog);
523 /* Setup the lapic or request the broadcast */
527 void __cpuinit setup_secondary_APIC_clock(void)
533 * The guts of the apic timer interrupt
535 static void local_apic_timer_interrupt(void)
537 int cpu = smp_processor_id();
538 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
541 * Normally we should not be here till LAPIC has been initialized but
542 * in some cases like kdump, its possible that there is a pending LAPIC
543 * timer interrupt from previous kernel's context and is delivered in
544 * new kernel the moment interrupts are enabled.
546 * Interrupts are enabled early and LAPIC is setup much later, hence
547 * its possible that when we get here evt->event_handler is NULL.
548 * Check for event_handler being NULL and discard the interrupt as
551 if (!evt->event_handler) {
553 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
555 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
560 * the NMI deadlock-detector uses this.
562 add_pda(apic_timer_irqs, 1);
564 evt->event_handler(evt);
568 * Local APIC timer interrupt. This is the most natural way for doing
569 * local interrupts, but local timer interrupts can be emulated by
570 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
572 * [ if a single-CPU system runs an SMP kernel then we call the local
573 * interrupt as well. Thus we cannot inline the local irq ... ]
575 void smp_apic_timer_interrupt(struct pt_regs *regs)
577 struct pt_regs *old_regs = set_irq_regs(regs);
580 * NOTE! We'd better ACK the irq immediately,
581 * because timer handling can be slow.
585 * update_process_times() expects us to have done irq_enter().
586 * Besides, if we don't timer interrupts ignore the global
587 * interrupt lock, which is the WrongThing (tm) to do.
591 local_apic_timer_interrupt();
594 set_irq_regs(old_regs);
597 int setup_profiling_timer(unsigned int multiplier)
604 * Local APIC start and shutdown
608 * clear_local_APIC - shutdown the local APIC
610 * This is called, when a CPU is disabled and before rebooting, so the state of
611 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
612 * leftovers during boot.
614 void clear_local_APIC(void)
619 /* APIC hasn't been mapped yet */
623 maxlvt = lapic_get_maxlvt();
625 * Masking an LVT entry can trigger a local APIC error
626 * if the vector is zero. Mask LVTERR first to prevent this.
629 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
630 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
633 * Careful: we have to set masks only first to deassert
634 * any level-triggered sources.
636 v = apic_read(APIC_LVTT);
637 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
638 v = apic_read(APIC_LVT0);
639 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
640 v = apic_read(APIC_LVT1);
641 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
643 v = apic_read(APIC_LVTPC);
644 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
647 /* lets not touch this if we didn't frob it */
648 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
650 v = apic_read(APIC_LVTTHMR);
651 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
655 * Clean APIC state for other OSs:
657 apic_write(APIC_LVTT, APIC_LVT_MASKED);
658 apic_write(APIC_LVT0, APIC_LVT_MASKED);
659 apic_write(APIC_LVT1, APIC_LVT_MASKED);
661 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
663 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
665 /* Integrated APIC (!82489DX) ? */
666 if (lapic_is_integrated()) {
668 /* Clear ESR due to Pentium errata 3AP and 11AP */
669 apic_write(APIC_ESR, 0);
675 * disable_local_APIC - clear and disable the local APIC
677 void disable_local_APIC(void)
684 * Disable APIC (implies clearing of registers
687 value = apic_read(APIC_SPIV);
688 value &= ~APIC_SPIV_APIC_ENABLED;
689 apic_write(APIC_SPIV, value);
692 void lapic_shutdown(void)
699 local_irq_save(flags);
701 disable_local_APIC();
703 local_irq_restore(flags);
707 * This is to verify that we're looking at a real local APIC.
708 * Check these against your board if the CPUs aren't getting
709 * started for no apparent reason.
711 int __init verify_local_APIC(void)
713 unsigned int reg0, reg1;
716 * The version register is read-only in a real APIC.
718 reg0 = apic_read(APIC_LVR);
719 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
720 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
721 reg1 = apic_read(APIC_LVR);
722 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
725 * The two version reads above should print the same
726 * numbers. If the second one is different, then we
727 * poke at a non-APIC.
733 * Check if the version looks reasonably.
735 reg1 = GET_APIC_VERSION(reg0);
736 if (reg1 == 0x00 || reg1 == 0xff)
738 reg1 = lapic_get_maxlvt();
739 if (reg1 < 0x02 || reg1 == 0xff)
743 * The ID register is read/write in a real APIC.
745 reg0 = apic_read(APIC_ID);
746 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
747 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
748 reg1 = apic_read(APIC_ID);
749 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
750 apic_write(APIC_ID, reg0);
751 if (reg1 != (reg0 ^ APIC_ID_MASK))
755 * The next two are just to see if we have sane values.
756 * They're only really relevant if we're in Virtual Wire
757 * compatibility mode, but most boxes are anymore.
759 reg0 = apic_read(APIC_LVT0);
760 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
761 reg1 = apic_read(APIC_LVT1);
762 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
768 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
770 void __init sync_Arb_IDs(void)
773 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
776 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
782 apic_wait_icr_idle();
784 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
785 apic_write(APIC_ICR, APIC_DEST_ALLINC |
786 APIC_INT_LEVELTRIG | APIC_DM_INIT);
790 * An initial setup of the virtual wire mode.
792 void __init init_bsp_APIC(void)
797 * Don't do the setup now if we have a SMP BIOS as the
798 * through-I/O-APIC virtual wire mode might be active.
800 if (smp_found_config || !cpu_has_apic)
804 * Do not trust the local APIC being empty at bootup.
811 value = apic_read(APIC_SPIV);
812 value &= ~APIC_VECTOR_MASK;
813 value |= APIC_SPIV_APIC_ENABLED;
816 /* This bit is reserved on P4/Xeon and should be cleared */
817 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
818 (boot_cpu_data.x86 == 15))
819 value &= ~APIC_SPIV_FOCUS_DISABLED;
822 value |= APIC_SPIV_FOCUS_DISABLED;
823 value |= SPURIOUS_APIC_VECTOR;
824 apic_write(APIC_SPIV, value);
827 * Set up the virtual wire mode.
829 apic_write(APIC_LVT0, APIC_DM_EXTINT);
831 if (!lapic_is_integrated()) /* 82489DX */
832 value |= APIC_LVT_LEVEL_TRIGGER;
833 apic_write(APIC_LVT1, value);
837 * setup_local_APIC - setup the local APIC
839 void __cpuinit setup_local_APIC(void)
845 value = apic_read(APIC_LVR);
847 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
850 * Double-check whether this APIC is really registered.
851 * This is meaningless in clustered apic mode, so we skip it.
853 if (!apic_id_registered())
857 * Intel recommends to set DFR, LDR and TPR before enabling
858 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
859 * document number 292116). So here it goes...
864 * Set Task Priority to 'accept all'. We never change this
867 value = apic_read(APIC_TASKPRI);
868 value &= ~APIC_TPRI_MASK;
869 apic_write(APIC_TASKPRI, value);
872 * After a crash, we no longer service the interrupts and a pending
873 * interrupt from previous kernel might still have ISR bit set.
875 * Most probably by now CPU has serviced that pending interrupt and
876 * it might not have done the ack_APIC_irq() because it thought,
877 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
878 * does not clear the ISR bit and cpu thinks it has already serivced
879 * the interrupt. Hence a vector might get locked. It was noticed
880 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
882 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
883 value = apic_read(APIC_ISR + i*0x10);
884 for (j = 31; j >= 0; j--) {
891 * Now that we are all set up, enable the APIC
893 value = apic_read(APIC_SPIV);
894 value &= ~APIC_VECTOR_MASK;
898 value |= APIC_SPIV_APIC_ENABLED;
900 /* We always use processor focus */
903 * Set spurious IRQ vector
905 value |= SPURIOUS_APIC_VECTOR;
906 apic_write(APIC_SPIV, value);
911 * set up through-local-APIC on the BP's LINT0. This is not
912 * strictly necessary in pure symmetric-IO mode, but sometimes
913 * we delegate interrupts to the 8259A.
916 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
918 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
919 if (!smp_processor_id() && !value) {
920 value = APIC_DM_EXTINT;
921 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
924 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
925 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
928 apic_write(APIC_LVT0, value);
931 * only the BP should see the LINT1 NMI signal, obviously.
933 if (!smp_processor_id())
936 value = APIC_DM_NMI | APIC_LVT_MASKED;
937 apic_write(APIC_LVT1, value);
941 static void __cpuinit lapic_setup_esr(void)
943 unsigned maxlvt = lapic_get_maxlvt();
945 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
947 * spec says clear errors after enabling vector.
950 apic_write(APIC_ESR, 0);
953 void __cpuinit end_local_APIC_setup(void)
956 setup_apic_nmi_watchdog(NULL);
960 void check_x2apic(void)
964 rdmsr(MSR_IA32_APICBASE, msr, msr2);
966 if (msr & X2APIC_ENABLE) {
967 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
968 x2apic_preenabled = x2apic = 1;
969 apic_ops = &x2apic_ops;
973 void enable_x2apic(void)
977 rdmsr(MSR_IA32_APICBASE, msr, msr2);
978 if (!(msr & X2APIC_ENABLE)) {
979 printk("Enabling x2apic\n");
980 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
984 void enable_IR_x2apic(void)
986 #ifdef CONFIG_INTR_REMAP
993 if (!x2apic_preenabled && disable_x2apic) {
995 "Skipped enabling x2apic and Interrupt-remapping "
996 "because of nox2apic\n");
1000 if (x2apic_preenabled && disable_x2apic)
1001 panic("Bios already enabled x2apic, can't enforce nox2apic");
1003 if (!x2apic_preenabled && skip_ioapic_setup) {
1005 "Skipped enabling x2apic and Interrupt-remapping "
1006 "because of skipping io-apic setup\n");
1010 ret = dmar_table_init();
1013 "dmar_table_init() failed with %d:\n", ret);
1015 if (x2apic_preenabled)
1016 panic("x2apic enabled by bios. But IR enabling failed");
1019 "Not enabling x2apic,Intr-remapping\n");
1023 local_irq_save(flags);
1025 save_mask_IO_APIC_setup();
1027 ret = enable_intr_remapping(1);
1029 if (ret && x2apic_preenabled) {
1030 local_irq_restore(flags);
1031 panic("x2apic enabled by bios. But IR enabling failed");
1039 apic_ops = &x2apic_ops;
1045 * IR enabling failed
1047 restore_IO_APIC_setup();
1049 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1052 local_irq_restore(flags);
1055 if (!x2apic_preenabled)
1057 "Enabled x2apic and interrupt-remapping\n");
1060 "Enabled Interrupt-remapping\n");
1063 "Failed to enable Interrupt-remapping and x2apic\n");
1065 if (!cpu_has_x2apic)
1068 if (x2apic_preenabled)
1069 panic("x2apic enabled prior OS handover,"
1070 " enable CONFIG_INTR_REMAP");
1072 printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1080 * Detect and enable local APICs on non-SMP boards.
1081 * Original code written by Keir Fraser.
1082 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1083 * not correctly set up (usually the APIC timer won't work etc.)
1085 static int __init detect_init_APIC(void)
1087 if (!cpu_has_apic) {
1088 printk(KERN_INFO "No local APIC present\n");
1092 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1093 boot_cpu_physical_apicid = 0;
1097 void __init early_init_lapic_mapping(void)
1099 unsigned long phys_addr;
1102 * If no local APIC can be found then go out
1103 * : it means there is no mpatable and MADT
1105 if (!smp_found_config)
1108 phys_addr = mp_lapic_addr;
1110 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1111 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1112 APIC_BASE, phys_addr);
1115 * Fetch the APIC ID of the BSP in case we have a
1116 * default configuration (or the MP table is broken).
1118 boot_cpu_physical_apicid = read_apic_id();
1122 * init_apic_mappings - initialize APIC mappings
1124 void __init init_apic_mappings(void)
1127 boot_cpu_physical_apicid = read_apic_id();
1132 * If no local APIC can be found then set up a fake all
1133 * zeroes page to simulate the local APIC and another
1134 * one for the IO-APIC.
1136 if (!smp_found_config && detect_init_APIC()) {
1137 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1138 apic_phys = __pa(apic_phys);
1140 apic_phys = mp_lapic_addr;
1142 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1143 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1144 APIC_BASE, apic_phys);
1147 * Fetch the APIC ID of the BSP in case we have a
1148 * default configuration (or the MP table is broken).
1150 boot_cpu_physical_apicid = read_apic_id();
1154 * This initializes the IO-APIC and APIC hardware if this is
1157 int __init APIC_init_uniprocessor(void)
1160 printk(KERN_INFO "Apic disabled\n");
1163 if (!cpu_has_apic) {
1165 printk(KERN_INFO "Apic disabled by BIOS\n");
1170 setup_apic_routing();
1172 verify_local_APIC();
1176 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1177 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1182 * Now enable IO-APICs, actually call clear_IO_APIC
1183 * We need clear_IO_APIC before enabling vector on BP
1185 if (!skip_ioapic_setup && nr_ioapics)
1188 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1189 localise_nmi_watchdog();
1190 end_local_APIC_setup();
1192 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1196 setup_boot_APIC_clock();
1197 check_nmi_watchdog();
1202 * Local APIC interrupts
1206 * This interrupt should _never_ happen with our APIC/SMP architecture
1208 asmlinkage void smp_spurious_interrupt(void)
1214 * Check if this really is a spurious interrupt and ACK it
1215 * if it is a vectored one. Just in case...
1216 * Spurious interrupts should not be ACKed.
1218 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1219 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1222 add_pda(irq_spurious_count, 1);
1227 * This interrupt should never happen with our APIC/SMP architecture
1229 asmlinkage void smp_error_interrupt(void)
1235 /* First tickle the hardware, only then report what went on. -- REW */
1236 v = apic_read(APIC_ESR);
1237 apic_write(APIC_ESR, 0);
1238 v1 = apic_read(APIC_ESR);
1240 atomic_inc(&irq_err_count);
1242 /* Here is what the APIC error bits mean:
1245 2: Send accept error
1246 3: Receive accept error
1248 5: Send illegal vector
1249 6: Received illegal vector
1250 7: Illegal register address
1252 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1253 smp_processor_id(), v , v1);
1258 * * connect_bsp_APIC - attach the APIC to the interrupt system
1260 void __init connect_bsp_APIC(void)
1266 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1267 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1269 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1272 void disconnect_bsp_APIC(int virt_wire_setup)
1274 /* Go back to Virtual Wire compatibility mode */
1275 unsigned long value;
1277 /* For the spurious interrupt use vector F, and enable it */
1278 value = apic_read(APIC_SPIV);
1279 value &= ~APIC_VECTOR_MASK;
1280 value |= APIC_SPIV_APIC_ENABLED;
1282 apic_write(APIC_SPIV, value);
1284 if (!virt_wire_setup) {
1286 * For LVT0 make it edge triggered, active high,
1287 * external and enabled
1289 value = apic_read(APIC_LVT0);
1290 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1291 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1292 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1293 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1294 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1295 apic_write(APIC_LVT0, value);
1298 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1301 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1302 value = apic_read(APIC_LVT1);
1303 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1304 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1305 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1306 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1307 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1308 apic_write(APIC_LVT1, value);
1311 void __cpuinit generic_processor_info(int apicid, int version)
1316 if (num_processors >= NR_CPUS) {
1317 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1318 " Processor ignored.\n", NR_CPUS);
1322 if (num_processors >= maxcpus) {
1323 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
1324 " Processor ignored.\n", maxcpus);
1329 cpus_complement(tmp_map, cpu_present_map);
1330 cpu = first_cpu(tmp_map);
1332 physid_set(apicid, phys_cpu_present_map);
1333 if (apicid == boot_cpu_physical_apicid) {
1335 * x86_bios_cpu_apicid is required to have processors listed
1336 * in same order as logical cpu numbers. Hence the first
1337 * entry is BSP, and so on.
1341 if (apicid > max_physical_apicid)
1342 max_physical_apicid = apicid;
1344 /* are we being called early in kernel startup? */
1345 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1346 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1347 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1349 cpu_to_apicid[cpu] = apicid;
1350 bios_cpu_apicid[cpu] = apicid;
1352 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1353 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1356 cpu_set(cpu, cpu_possible_map);
1357 cpu_set(cpu, cpu_present_map);
1360 int hard_smp_processor_id(void)
1362 return read_apic_id();
1372 * 'active' is true if the local APIC was enabled by us and
1373 * not the BIOS; this signifies that we are also responsible
1374 * for disabling it before entering apm/acpi suspend
1377 /* r/w apic fields */
1378 unsigned int apic_id;
1379 unsigned int apic_taskpri;
1380 unsigned int apic_ldr;
1381 unsigned int apic_dfr;
1382 unsigned int apic_spiv;
1383 unsigned int apic_lvtt;
1384 unsigned int apic_lvtpc;
1385 unsigned int apic_lvt0;
1386 unsigned int apic_lvt1;
1387 unsigned int apic_lvterr;
1388 unsigned int apic_tmict;
1389 unsigned int apic_tdcr;
1390 unsigned int apic_thmr;
1393 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1395 unsigned long flags;
1398 if (!apic_pm_state.active)
1401 maxlvt = lapic_get_maxlvt();
1403 apic_pm_state.apic_id = apic_read(APIC_ID);
1404 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1405 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1406 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1407 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1408 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1410 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1411 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1412 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1413 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1414 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1415 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1416 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1418 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1421 local_irq_save(flags);
1422 disable_local_APIC();
1423 local_irq_restore(flags);
1427 static int lapic_resume(struct sys_device *dev)
1430 unsigned long flags;
1433 if (!apic_pm_state.active)
1436 maxlvt = lapic_get_maxlvt();
1438 local_irq_save(flags);
1440 #ifdef CONFIG_X86_64
1446 * Make sure the APICBASE points to the right address
1448 * FIXME! This will be wrong if we ever support suspend on
1449 * SMP! We'll need to do this as part of the CPU restore!
1451 rdmsr(MSR_IA32_APICBASE, l, h);
1452 l &= ~MSR_IA32_APICBASE_BASE;
1453 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1454 wrmsr(MSR_IA32_APICBASE, l, h);
1456 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1457 apic_write(APIC_ID, apic_pm_state.apic_id);
1458 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1459 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1460 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1461 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1462 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1463 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1464 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1466 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1469 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1470 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1471 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1472 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1473 apic_write(APIC_ESR, 0);
1474 apic_read(APIC_ESR);
1475 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1476 apic_write(APIC_ESR, 0);
1477 apic_read(APIC_ESR);
1479 local_irq_restore(flags);
1485 * This device has no shutdown method - fully functioning local APICs
1486 * are needed on every CPU up until machine_halt/restart/poweroff.
1489 static struct sysdev_class lapic_sysclass = {
1491 .resume = lapic_resume,
1492 .suspend = lapic_suspend,
1495 static struct sys_device device_lapic = {
1497 .cls = &lapic_sysclass,
1500 static void __cpuinit apic_pm_activate(void)
1502 apic_pm_state.active = 1;
1505 static int __init init_lapic_sysfs(void)
1511 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1513 error = sysdev_class_register(&lapic_sysclass);
1515 error = sysdev_register(&device_lapic);
1518 device_initcall(init_lapic_sysfs);
1520 #else /* CONFIG_PM */
1522 static void apic_pm_activate(void) { }
1524 #endif /* CONFIG_PM */
1527 * apic_is_clustered_box() -- Check if we can expect good TSC
1529 * Thus far, the major user of this is IBM's Summit2 series:
1531 * Clustered boxes may have unsynced TSC problems if they are
1532 * multi-chassis. Use available data to take a good guess.
1533 * If in doubt, go HPET.
1535 __cpuinit int apic_is_clustered_box(void)
1537 int i, clusters, zeros;
1539 u16 *bios_cpu_apicid;
1540 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1543 * there is not this kind of box with AMD CPU yet.
1544 * Some AMD box with quadcore cpu and 8 sockets apicid
1545 * will be [4, 0x23] or [8, 0x27] could be thought to
1546 * vsmp box still need checking...
1548 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1551 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1552 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1554 for (i = 0; i < NR_CPUS; i++) {
1555 /* are we being called early in kernel startup? */
1556 if (bios_cpu_apicid) {
1557 id = bios_cpu_apicid[i];
1559 else if (i < nr_cpu_ids) {
1561 id = per_cpu(x86_bios_cpu_apicid, i);
1568 if (id != BAD_APICID)
1569 __set_bit(APIC_CLUSTERID(id), clustermap);
1572 /* Problem: Partially populated chassis may not have CPUs in some of
1573 * the APIC clusters they have been allocated. Only present CPUs have
1574 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1575 * Since clusters are allocated sequentially, count zeros only if
1576 * they are bounded by ones.
1580 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1581 if (test_bit(i, clustermap)) {
1582 clusters += 1 + zeros;
1588 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1589 * not guaranteed to be synced between boards
1591 if (is_vsmp_box() && clusters > 1)
1595 * If clusters > 2, then should be multi-chassis.
1596 * May have to revisit this when multi-core + hyperthreaded CPUs come
1597 * out, but AFAIK this will work even for them.
1599 return (clusters > 2);
1602 static __init int setup_nox2apic(char *str)
1605 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_X2APIC);
1608 early_param("nox2apic", setup_nox2apic);
1612 * APIC command line parameters
1614 static int __init apic_set_verbosity(char *str)
1617 skip_ioapic_setup = 0;
1621 if (strcmp("debug", str) == 0)
1622 apic_verbosity = APIC_DEBUG;
1623 else if (strcmp("verbose", str) == 0)
1624 apic_verbosity = APIC_VERBOSE;
1626 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1627 " use apic=verbose or apic=debug\n", str);
1633 early_param("apic", apic_set_verbosity);
1635 static __init int setup_disableapic(char *str)
1638 setup_clear_cpu_cap(X86_FEATURE_APIC);
1641 early_param("disableapic", setup_disableapic);
1643 /* same as disableapic, for compatibility */
1644 static __init int setup_nolapic(char *str)
1646 return setup_disableapic(str);
1648 early_param("nolapic", setup_nolapic);
1650 static int __init parse_lapic_timer_c2_ok(char *arg)
1652 local_apic_timer_c2_ok = 1;
1655 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1657 static int __init parse_disable_apic_timer(char *arg)
1659 disable_apic_timer = 1;
1662 early_param("noapictimer", parse_disable_apic_timer);
1664 static int __init parse_nolapic_timer(char *arg)
1666 disable_apic_timer = 1;
1669 early_param("nolapic_timer", parse_nolapic_timer);
1671 static __init int setup_apicpmtimer(char *s)
1673 apic_calibrate_pmtmr = 1;
1677 __setup("apicpmtimer", setup_apicpmtimer);
1679 static int __init lapic_insert_resource(void)
1684 /* Put local APIC into the resource map. */
1685 lapic_resource.start = apic_phys;
1686 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1687 insert_resource(&iomem_resource, &lapic_resource);
1693 * need call insert after e820_reserve_resources()
1694 * that is using request_resource
1696 late_initcall(lapic_insert_resource);