2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/module.h>
27 #include <linux/ioport.h>
29 #include <asm/atomic.h>
32 #include <asm/mpspec.h>
33 #include <asm/pgalloc.h>
34 #include <asm/mach_apic.h>
37 #include <asm/proto.h>
38 #include <asm/timex.h>
43 int apic_runs_main_timer;
44 int apic_calibrate_pmtmr __initdata;
46 int disable_apic_timer __initdata;
48 /* Local APIC timer works in C2? */
49 int local_apic_timer_c2_ok;
50 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
52 static struct resource *ioapic_resources;
53 static struct resource lapic_resource = {
55 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
59 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
60 * IPIs in place of local APIC timers
62 static cpumask_t timer_interrupt_broadcast_ipi_mask;
64 /* Using APIC to generate smp_local_timer_interrupt? */
65 int using_apic_timer __read_mostly = 0;
67 static void apic_pm_activate(void);
69 void apic_wait_icr_idle(void)
71 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
75 unsigned int safe_apic_wait_icr_idle(void)
77 unsigned int send_status;
82 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
86 } while (timeout++ < 1000);
91 void enable_NMI_through_LVT0 (void * dummy)
95 /* unmask and set to NMI */
97 apic_write(APIC_LVT0, v);
102 unsigned int v, maxlvt;
104 v = apic_read(APIC_LVR);
105 maxlvt = GET_APIC_MAXLVT(v);
110 * 'what should we do if we get a hw irq event on an illegal vector'.
111 * each architecture has to answer this themselves.
113 void ack_bad_irq(unsigned int irq)
115 printk("unexpected IRQ trap at vector %02x\n", irq);
117 * Currently unexpected vectors happen only on SMP and APIC.
118 * We _must_ ack these because every local APIC has only N
119 * irq slots per priority level, and a 'hanging, unacked' IRQ
120 * holds up an irq slot - in excessive cases (when multiple
121 * unexpected vectors occur) that might lock up the APIC
123 * But don't ack when the APIC is disabled. -AK
129 void clear_local_APIC(void)
134 maxlvt = get_maxlvt();
137 * Masking an LVT entry can trigger a local APIC error
138 * if the vector is zero. Mask LVTERR first to prevent this.
141 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
142 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
145 * Careful: we have to set masks only first to deassert
146 * any level-triggered sources.
148 v = apic_read(APIC_LVTT);
149 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
150 v = apic_read(APIC_LVT0);
151 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
152 v = apic_read(APIC_LVT1);
153 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
155 v = apic_read(APIC_LVTPC);
156 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
160 * Clean APIC state for other OSs:
162 apic_write(APIC_LVTT, APIC_LVT_MASKED);
163 apic_write(APIC_LVT0, APIC_LVT_MASKED);
164 apic_write(APIC_LVT1, APIC_LVT_MASKED);
166 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
168 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
169 apic_write(APIC_ESR, 0);
173 void disconnect_bsp_APIC(int virt_wire_setup)
175 /* Go back to Virtual Wire compatibility mode */
178 /* For the spurious interrupt use vector F, and enable it */
179 value = apic_read(APIC_SPIV);
180 value &= ~APIC_VECTOR_MASK;
181 value |= APIC_SPIV_APIC_ENABLED;
183 apic_write(APIC_SPIV, value);
185 if (!virt_wire_setup) {
186 /* For LVT0 make it edge triggered, active high, external and enabled */
187 value = apic_read(APIC_LVT0);
188 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
189 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
190 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
191 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
192 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
193 apic_write(APIC_LVT0, value);
196 apic_write(APIC_LVT0, APIC_LVT_MASKED);
199 /* For LVT1 make it edge triggered, active high, nmi and enabled */
200 value = apic_read(APIC_LVT1);
201 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
202 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
203 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
204 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
205 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
206 apic_write(APIC_LVT1, value);
209 void disable_local_APIC(void)
216 * Disable APIC (implies clearing of registers
219 value = apic_read(APIC_SPIV);
220 value &= ~APIC_SPIV_APIC_ENABLED;
221 apic_write(APIC_SPIV, value);
225 * This is to verify that we're looking at a real local APIC.
226 * Check these against your board if the CPUs aren't getting
227 * started for no apparent reason.
229 int __init verify_local_APIC(void)
231 unsigned int reg0, reg1;
234 * The version register is read-only in a real APIC.
236 reg0 = apic_read(APIC_LVR);
237 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
238 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
239 reg1 = apic_read(APIC_LVR);
240 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
243 * The two version reads above should print the same
244 * numbers. If the second one is different, then we
245 * poke at a non-APIC.
251 * Check if the version looks reasonably.
253 reg1 = GET_APIC_VERSION(reg0);
254 if (reg1 == 0x00 || reg1 == 0xff)
257 if (reg1 < 0x02 || reg1 == 0xff)
261 * The ID register is read/write in a real APIC.
263 reg0 = apic_read(APIC_ID);
264 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
265 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
266 reg1 = apic_read(APIC_ID);
267 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
268 apic_write(APIC_ID, reg0);
269 if (reg1 != (reg0 ^ APIC_ID_MASK))
273 * The next two are just to see if we have sane values.
274 * They're only really relevant if we're in Virtual Wire
275 * compatibility mode, but most boxes are anymore.
277 reg0 = apic_read(APIC_LVT0);
278 apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
279 reg1 = apic_read(APIC_LVT1);
280 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
285 void __init sync_Arb_IDs(void)
287 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
288 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
289 if (ver >= 0x14) /* P4 or higher */
295 apic_wait_icr_idle();
297 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
298 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
303 * An initial setup of the virtual wire mode.
305 void __init init_bsp_APIC(void)
310 * Don't do the setup now if we have a SMP BIOS as the
311 * through-I/O-APIC virtual wire mode might be active.
313 if (smp_found_config || !cpu_has_apic)
316 value = apic_read(APIC_LVR);
319 * Do not trust the local APIC being empty at bootup.
326 value = apic_read(APIC_SPIV);
327 value &= ~APIC_VECTOR_MASK;
328 value |= APIC_SPIV_APIC_ENABLED;
329 value |= APIC_SPIV_FOCUS_DISABLED;
330 value |= SPURIOUS_APIC_VECTOR;
331 apic_write(APIC_SPIV, value);
334 * Set up the virtual wire mode.
336 apic_write(APIC_LVT0, APIC_DM_EXTINT);
338 apic_write(APIC_LVT1, value);
341 void __cpuinit setup_local_APIC (void)
343 unsigned int value, maxlvt;
346 value = apic_read(APIC_LVR);
348 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
351 * Double-check whether this APIC is really registered.
352 * This is meaningless in clustered apic mode, so we skip it.
354 if (!apic_id_registered())
358 * Intel recommends to set DFR, LDR and TPR before enabling
359 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
360 * document number 292116). So here it goes...
365 * Set Task Priority to 'accept all'. We never change this
368 value = apic_read(APIC_TASKPRI);
369 value &= ~APIC_TPRI_MASK;
370 apic_write(APIC_TASKPRI, value);
373 * After a crash, we no longer service the interrupts and a pending
374 * interrupt from previous kernel might still have ISR bit set.
376 * Most probably by now CPU has serviced that pending interrupt and
377 * it might not have done the ack_APIC_irq() because it thought,
378 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
379 * does not clear the ISR bit and cpu thinks it has already serivced
380 * the interrupt. Hence a vector might get locked. It was noticed
381 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
383 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
384 value = apic_read(APIC_ISR + i*0x10);
385 for (j = 31; j >= 0; j--) {
392 * Now that we are all set up, enable the APIC
394 value = apic_read(APIC_SPIV);
395 value &= ~APIC_VECTOR_MASK;
399 value |= APIC_SPIV_APIC_ENABLED;
401 /* We always use processor focus */
404 * Set spurious IRQ vector
406 value |= SPURIOUS_APIC_VECTOR;
407 apic_write(APIC_SPIV, value);
412 * set up through-local-APIC on the BP's LINT0. This is not
413 * strictly necessary in pure symmetric-IO mode, but sometimes
414 * we delegate interrupts to the 8259A.
417 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
419 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
420 if (!smp_processor_id() && !value) {
421 value = APIC_DM_EXTINT;
422 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
424 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
425 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
427 apic_write(APIC_LVT0, value);
430 * only the BP should see the LINT1 NMI signal, obviously.
432 if (!smp_processor_id())
435 value = APIC_DM_NMI | APIC_LVT_MASKED;
436 apic_write(APIC_LVT1, value);
440 maxlvt = get_maxlvt();
441 oldvalue = apic_read(APIC_ESR);
442 value = ERROR_APIC_VECTOR; // enables sending errors
443 apic_write(APIC_LVTERR, value);
445 * spec says clear errors after enabling vector.
448 apic_write(APIC_ESR, 0);
449 value = apic_read(APIC_ESR);
450 if (value != oldvalue)
451 apic_printk(APIC_VERBOSE,
452 "ESR value after enabling vector: %08x, after %08x\n",
456 nmi_watchdog_default();
457 setup_apic_nmi_watchdog(NULL);
464 /* 'active' is true if the local APIC was enabled by us and
465 not the BIOS; this signifies that we are also responsible
466 for disabling it before entering apm/acpi suspend */
468 /* r/w apic fields */
469 unsigned int apic_id;
470 unsigned int apic_taskpri;
471 unsigned int apic_ldr;
472 unsigned int apic_dfr;
473 unsigned int apic_spiv;
474 unsigned int apic_lvtt;
475 unsigned int apic_lvtpc;
476 unsigned int apic_lvt0;
477 unsigned int apic_lvt1;
478 unsigned int apic_lvterr;
479 unsigned int apic_tmict;
480 unsigned int apic_tdcr;
481 unsigned int apic_thmr;
484 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
489 if (!apic_pm_state.active)
492 maxlvt = get_maxlvt();
494 apic_pm_state.apic_id = apic_read(APIC_ID);
495 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
496 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
497 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
498 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
499 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
501 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
502 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
503 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
504 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
505 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
506 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
507 #ifdef CONFIG_X86_MCE_INTEL
509 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
511 local_irq_save(flags);
512 disable_local_APIC();
513 local_irq_restore(flags);
517 static int lapic_resume(struct sys_device *dev)
523 if (!apic_pm_state.active)
526 maxlvt = get_maxlvt();
528 local_irq_save(flags);
529 rdmsr(MSR_IA32_APICBASE, l, h);
530 l &= ~MSR_IA32_APICBASE_BASE;
531 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
532 wrmsr(MSR_IA32_APICBASE, l, h);
533 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
534 apic_write(APIC_ID, apic_pm_state.apic_id);
535 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
536 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
537 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
538 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
539 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
540 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
541 #ifdef CONFIG_X86_MCE_INTEL
543 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
546 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
547 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
548 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
549 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
550 apic_write(APIC_ESR, 0);
552 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
553 apic_write(APIC_ESR, 0);
555 local_irq_restore(flags);
559 static struct sysdev_class lapic_sysclass = {
560 set_kset_name("lapic"),
561 .resume = lapic_resume,
562 .suspend = lapic_suspend,
565 static struct sys_device device_lapic = {
567 .cls = &lapic_sysclass,
570 static void __cpuinit apic_pm_activate(void)
572 apic_pm_state.active = 1;
575 static int __init init_lapic_sysfs(void)
580 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
581 error = sysdev_class_register(&lapic_sysclass);
583 error = sysdev_register(&device_lapic);
586 device_initcall(init_lapic_sysfs);
588 #else /* CONFIG_PM */
590 static void apic_pm_activate(void) { }
592 #endif /* CONFIG_PM */
594 static int __init apic_set_verbosity(char *str)
597 skip_ioapic_setup = 0;
601 if (strcmp("debug", str) == 0)
602 apic_verbosity = APIC_DEBUG;
603 else if (strcmp("verbose", str) == 0)
604 apic_verbosity = APIC_VERBOSE;
606 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
607 " use apic=verbose or apic=debug\n", str);
613 early_param("apic", apic_set_verbosity);
616 * Detect and enable local APICs on non-SMP boards.
617 * Original code written by Keir Fraser.
618 * On AMD64 we trust the BIOS - if it says no APIC it is likely
619 * not correctly set up (usually the APIC timer won't work etc.)
622 static int __init detect_init_APIC (void)
625 printk(KERN_INFO "No local APIC present\n");
629 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
634 #ifdef CONFIG_X86_IO_APIC
635 static struct resource * __init ioapic_setup_resources(void)
637 #define IOAPIC_RESOURCE_NAME_SIZE 11
639 struct resource *res;
646 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
649 mem = alloc_bootmem(n);
654 mem += sizeof(struct resource) * nr_ioapics;
656 for (i = 0; i < nr_ioapics; i++) {
658 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
659 sprintf(mem, "IOAPIC %u", i);
660 mem += IOAPIC_RESOURCE_NAME_SIZE;
664 ioapic_resources = res;
669 static int __init ioapic_insert_resources(void)
672 struct resource *r = ioapic_resources;
675 printk("IO APIC resources could be not be allocated.\n");
679 for (i = 0; i < nr_ioapics; i++) {
680 insert_resource(&iomem_resource, r);
687 /* Insert the IO APIC resources after PCI initialization has occured to handle
688 * IO APICS that are mapped in on a BAR in PCI space. */
689 late_initcall(ioapic_insert_resources);
692 void __init init_apic_mappings(void)
694 unsigned long apic_phys;
697 * If no local APIC can be found then set up a fake all
698 * zeroes page to simulate the local APIC and another
699 * one for the IO-APIC.
701 if (!smp_found_config && detect_init_APIC()) {
702 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
703 apic_phys = __pa(apic_phys);
705 apic_phys = mp_lapic_addr;
707 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
708 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
709 APIC_BASE, apic_phys);
711 /* Put local APIC into the resource map. */
712 lapic_resource.start = apic_phys;
713 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
714 insert_resource(&iomem_resource, &lapic_resource);
717 * Fetch the APIC ID of the BSP in case we have a
718 * default configuration (or the MP table is broken).
720 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
723 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
725 struct resource *ioapic_res;
727 ioapic_res = ioapic_setup_resources();
728 for (i = 0; i < nr_ioapics; i++) {
729 if (smp_found_config) {
730 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
732 ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
733 ioapic_phys = __pa(ioapic_phys);
735 set_fixmap_nocache(idx, ioapic_phys);
736 apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n",
737 __fix_to_virt(idx), ioapic_phys);
740 if (ioapic_res != NULL) {
741 ioapic_res->start = ioapic_phys;
742 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
750 * This function sets up the local APIC timer, with a timeout of
751 * 'clocks' APIC bus clock. During calibration we actually call
752 * this function twice on the boot CPU, once with a bogus timeout
753 * value, second time for real. The other (noncalibrating) CPUs
754 * call this function only once, with the real, calibrated value.
756 * We do reads before writes even if unnecessary, to get around the
757 * P5 APIC double write bug.
760 #define APIC_DIVISOR 16
762 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
764 unsigned int lvtt_value, tmp_value;
766 lvtt_value = LOCAL_TIMER_VECTOR;
768 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
770 lvtt_value |= APIC_LVT_MASKED;
772 apic_write(APIC_LVTT, lvtt_value);
777 tmp_value = apic_read(APIC_TDCR);
778 apic_write(APIC_TDCR, (tmp_value
779 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
783 apic_write(APIC_TMICT, clocks/APIC_DIVISOR);
786 static void setup_APIC_timer(unsigned int clocks)
791 local_irq_save(flags);
793 /* wait for irq slice */
794 if (hpet_address && hpet_use_timer) {
795 u32 trigger = hpet_readl(HPET_T0_CMP);
796 while (hpet_readl(HPET_T0_CMP) == trigger)
802 c2 |= inb_p(0x40) << 8;
807 c2 |= inb_p(0x40) << 8;
808 } while (c2 - c1 < 300);
811 irqen = ! cpu_isset(smp_processor_id(),
812 timer_interrupt_broadcast_ipi_mask);
813 __setup_APIC_LVTT(clocks, 0, irqen);
814 /* Turn off PIT interrupt if we use APIC timer as main timer.
815 Only works with the PM timer right now
816 TBD fix it for HPET too. */
817 if ((pmtmr_ioport != 0) &&
818 smp_processor_id() == boot_cpu_id &&
819 apic_runs_main_timer == 1 &&
820 !cpu_isset(boot_cpu_id, timer_interrupt_broadcast_ipi_mask)) {
821 stop_timer_interrupt();
822 apic_runs_main_timer++;
824 local_irq_restore(flags);
828 * In this function we calibrate APIC bus clocks to the external
829 * timer. Unfortunately we cannot use jiffies and the timer irq
830 * to calibrate, since some later bootup code depends on getting
831 * the first irq? Ugh.
833 * We want to do the calibration only once since we
834 * want to have local timer irqs syncron. CPUs connected
835 * by the same APIC bus have the very same bus frequency.
836 * And we want to have irqs off anyways, no accidental
840 #define TICK_COUNT 100000000
842 static int __init calibrate_APIC_clock(void)
844 unsigned apic, apic_start;
845 unsigned long tsc, tsc_start;
848 * Put whatever arbitrary (but long enough) timeout
849 * value into the APIC clock, we just want to get the
850 * counter running for calibration.
852 * No interrupt enable !
854 __setup_APIC_LVTT(4000000000, 0, 0);
856 apic_start = apic_read(APIC_TMCCT);
857 #ifdef CONFIG_X86_PM_TIMER
858 if (apic_calibrate_pmtmr && pmtmr_ioport) {
859 pmtimer_wait(5000); /* 5ms wait */
860 apic = apic_read(APIC_TMCCT);
861 result = (apic_start - apic) * 1000L / 5;
868 apic = apic_read(APIC_TMCCT);
870 } while ((tsc - tsc_start) < TICK_COUNT &&
871 (apic_start - apic) < TICK_COUNT);
873 result = (apic_start - apic) * 1000L * tsc_khz /
876 printk("result %d\n", result);
879 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
880 result / 1000 / 1000, result / 1000 % 1000);
882 return result * APIC_DIVISOR / HZ;
885 static unsigned int calibration_result;
887 void __init setup_boot_APIC_clock (void)
889 if (disable_apic_timer) {
890 printk(KERN_INFO "Disabling APIC timer\n");
894 printk(KERN_INFO "Using local APIC timer interrupts.\n");
895 using_apic_timer = 1;
899 calibration_result = calibrate_APIC_clock();
901 * Now set up the timer for real.
903 setup_APIC_timer(calibration_result);
908 void __cpuinit setup_secondary_APIC_clock(void)
910 local_irq_disable(); /* FIXME: Do we need this? --RR */
911 setup_APIC_timer(calibration_result);
915 void disable_APIC_timer(void)
917 if (using_apic_timer) {
920 v = apic_read(APIC_LVTT);
922 * When an illegal vector value (0-15) is written to an LVT
923 * entry and delivery mode is Fixed, the APIC may signal an
924 * illegal vector error, with out regard to whether the mask
925 * bit is set or whether an interrupt is actually seen on input.
927 * Boot sequence might call this function when the LVTT has
928 * '0' vector value. So make sure vector field is set to
931 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
932 apic_write(APIC_LVTT, v);
936 void enable_APIC_timer(void)
938 int cpu = smp_processor_id();
940 if (using_apic_timer &&
941 !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) {
944 v = apic_read(APIC_LVTT);
945 apic_write(APIC_LVTT, v & ~APIC_LVT_MASKED);
949 void switch_APIC_timer_to_ipi(void *cpumask)
951 cpumask_t mask = *(cpumask_t *)cpumask;
952 int cpu = smp_processor_id();
954 if (cpu_isset(cpu, mask) &&
955 !cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) {
956 disable_APIC_timer();
957 cpu_set(cpu, timer_interrupt_broadcast_ipi_mask);
960 EXPORT_SYMBOL(switch_APIC_timer_to_ipi);
962 void smp_send_timer_broadcast_ipi(void)
964 int cpu = smp_processor_id();
967 cpus_and(mask, cpu_online_map, timer_interrupt_broadcast_ipi_mask);
969 if (cpu_isset(cpu, mask)) {
970 cpu_clear(cpu, mask);
971 add_pda(apic_timer_irqs, 1);
972 smp_local_timer_interrupt();
975 if (!cpus_empty(mask)) {
976 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
980 void switch_ipi_to_APIC_timer(void *cpumask)
982 cpumask_t mask = *(cpumask_t *)cpumask;
983 int cpu = smp_processor_id();
985 if (cpu_isset(cpu, mask) &&
986 cpu_isset(cpu, timer_interrupt_broadcast_ipi_mask)) {
987 cpu_clear(cpu, timer_interrupt_broadcast_ipi_mask);
991 EXPORT_SYMBOL(switch_ipi_to_APIC_timer);
993 int setup_profiling_timer(unsigned int multiplier)
998 void setup_APIC_extended_lvt(unsigned char lvt_off, unsigned char vector,
999 unsigned char msg_type, unsigned char mask)
1001 unsigned long reg = (lvt_off << 4) + K8_APIC_EXT_LVT_BASE;
1002 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
1009 * Local timer interrupt handler. It does both profiling and
1010 * process statistics/rescheduling.
1012 * We do profiling in every local tick, statistics/rescheduling
1013 * happen only every 'profiling multiplier' ticks. The default
1014 * multiplier is 1 and it can be changed by writing the new multiplier
1015 * value into /proc/profile.
1018 void smp_local_timer_interrupt(void)
1020 profile_tick(CPU_PROFILING);
1022 update_process_times(user_mode(get_irq_regs()));
1024 if (apic_runs_main_timer > 1 && smp_processor_id() == boot_cpu_id)
1025 main_timer_handler();
1027 * We take the 'long' return path, and there every subsystem
1028 * grabs the appropriate locks (kernel lock/ irq lock).
1030 * We might want to decouple profiling from the 'long path',
1031 * and do the profiling totally in assembly.
1033 * Currently this isn't too much of an issue (performance wise),
1034 * we can take more than 100K local irqs per second on a 100 MHz P5.
1039 * Local APIC timer interrupt. This is the most natural way for doing
1040 * local interrupts, but local timer interrupts can be emulated by
1041 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1043 * [ if a single-CPU system runs an SMP kernel then we call the local
1044 * interrupt as well. Thus we cannot inline the local irq ... ]
1046 void smp_apic_timer_interrupt(struct pt_regs *regs)
1048 struct pt_regs *old_regs = set_irq_regs(regs);
1051 * the NMI deadlock-detector uses this.
1053 add_pda(apic_timer_irqs, 1);
1056 * NOTE! We'd better ACK the irq immediately,
1057 * because timer handling can be slow.
1061 * update_process_times() expects us to have done irq_enter().
1062 * Besides, if we don't timer interrupts ignore the global
1063 * interrupt lock, which is the WrongThing (tm) to do.
1067 smp_local_timer_interrupt();
1069 set_irq_regs(old_regs);
1073 * apic_is_clustered_box() -- Check if we can expect good TSC
1075 * Thus far, the major user of this is IBM's Summit2 series:
1077 * Clustered boxes may have unsynced TSC problems if they are
1078 * multi-chassis. Use available data to take a good guess.
1079 * If in doubt, go HPET.
1081 __cpuinit int apic_is_clustered_box(void)
1083 int i, clusters, zeros;
1085 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1087 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1089 for (i = 0; i < NR_CPUS; i++) {
1090 id = bios_cpu_apicid[i];
1091 if (id != BAD_APICID)
1092 __set_bit(APIC_CLUSTERID(id), clustermap);
1095 /* Problem: Partially populated chassis may not have CPUs in some of
1096 * the APIC clusters they have been allocated. Only present CPUs have
1097 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
1098 * clusters are allocated sequentially, count zeros only if they are
1103 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1104 if (test_bit(i, clustermap)) {
1105 clusters += 1 + zeros;
1112 * If clusters > 2, then should be multi-chassis.
1113 * May have to revisit this when multi-core + hyperthreaded CPUs come
1114 * out, but AFAIK this will work even for them.
1116 return (clusters > 2);
1120 * This interrupt should _never_ happen with our APIC/SMP architecture
1122 asmlinkage void smp_spurious_interrupt(void)
1128 * Check if this really is a spurious interrupt and ACK it
1129 * if it is a vectored one. Just in case...
1130 * Spurious interrupts should not be ACKed.
1132 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1133 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1140 * This interrupt should never happen with our APIC/SMP architecture
1143 asmlinkage void smp_error_interrupt(void)
1149 /* First tickle the hardware, only then report what went on. -- REW */
1150 v = apic_read(APIC_ESR);
1151 apic_write(APIC_ESR, 0);
1152 v1 = apic_read(APIC_ESR);
1154 atomic_inc(&irq_err_count);
1156 /* Here is what the APIC error bits mean:
1159 2: Send accept error
1160 3: Receive accept error
1162 5: Send illegal vector
1163 6: Received illegal vector
1164 7: Illegal register address
1166 printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1167 smp_processor_id(), v , v1);
1174 * This initializes the IO-APIC and APIC hardware if this is
1177 int __init APIC_init_uniprocessor (void)
1180 printk(KERN_INFO "Apic disabled\n");
1183 if (!cpu_has_apic) {
1185 printk(KERN_INFO "Apic disabled by BIOS\n");
1189 verify_local_APIC();
1191 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_id);
1192 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_id));
1196 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1200 setup_boot_APIC_clock();
1201 check_nmi_watchdog();
1205 static __init int setup_disableapic(char *str)
1208 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1211 early_param("disableapic", setup_disableapic);
1213 /* same as disableapic, for compatibility */
1214 static __init int setup_nolapic(char *str)
1216 return setup_disableapic(str);
1218 early_param("nolapic", setup_nolapic);
1220 static int __init parse_lapic_timer_c2_ok(char *arg)
1222 local_apic_timer_c2_ok = 1;
1225 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1227 static __init int setup_noapictimer(char *str)
1229 if (str[0] != ' ' && str[0] != 0)
1231 disable_apic_timer = 1;
1235 static __init int setup_apicmaintimer(char *str)
1237 apic_runs_main_timer = 1;
1241 __setup("apicmaintimer", setup_apicmaintimer);
1243 static __init int setup_noapicmaintimer(char *str)
1245 apic_runs_main_timer = -1;
1248 __setup("noapicmaintimer", setup_noapicmaintimer);
1250 static __init int setup_apicpmtimer(char *s)
1252 apic_calibrate_pmtmr = 1;
1254 return setup_apicmaintimer(NULL);
1256 __setup("apicpmtimer", setup_apicpmtimer);
1258 __setup("noapictimer", setup_noapictimer);