1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/bootmem.h>
8 #include <asm/processor.h>
12 #include <asm/mmu_context.h>
17 #ifdef CONFIG_X86_LOCAL_APIC
18 #include <asm/mpspec.h>
20 #include <mach_apic.h>
25 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
26 [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
27 [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
28 [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
29 [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
31 * Segments used for calling PnP BIOS have byte granularity.
32 * They code segments and data segments have fixed 64k limits,
33 * the transfer segment sizes are set at run time.
36 [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
38 [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
40 [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
42 [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
44 [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
46 * The APM segments have byte granularity and their bases
47 * are set at run time. All have 64k limits.
50 [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
52 [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
54 [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
56 [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
57 [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
59 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
61 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
63 static int cachesize_override __cpuinitdata = -1;
64 static int disable_x86_serial_nr __cpuinitdata = 1;
66 struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
68 static void __cpuinit default_init(struct cpuinfo_x86 *c)
70 /* Not much we can do here... */
71 /* Check if at least it has cpuid */
72 if (c->cpuid_level == -1) {
73 /* No cpuid. It must be an ancient CPU */
75 strcpy(c->x86_model_id, "486");
77 strcpy(c->x86_model_id, "386");
81 static struct cpu_dev __cpuinitdata default_cpu = {
82 .c_init = default_init,
83 .c_vendor = "Unknown",
85 static struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
87 static int __init cachesize_setup(char *str)
89 get_option(&str, &cachesize_override);
92 __setup("cachesize=", cachesize_setup);
94 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
99 if (cpuid_eax(0x80000000) < 0x80000004)
102 v = (unsigned int *) c->x86_model_id;
103 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
104 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
105 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
106 c->x86_model_id[48] = 0;
108 /* Intel chips right-justify this string for some dumb reason;
109 undo that brain damage */
110 p = q = &c->x86_model_id[0];
116 while (q <= &c->x86_model_id[48])
117 *q++ = '\0'; /* Zero-pad the rest */
124 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
126 unsigned int n, dummy, ecx, edx, l2size;
128 n = cpuid_eax(0x80000000);
130 if (n >= 0x80000005) {
131 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
132 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
133 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
134 c->x86_cache_size = (ecx>>24)+(edx>>24);
137 if (n < 0x80000006) /* Some chips just has a large L1. */
140 ecx = cpuid_ecx(0x80000006);
143 /* do processor-specific cache resizing */
144 if (this_cpu->c_size_cache)
145 l2size = this_cpu->c_size_cache(c, l2size);
147 /* Allow user to override all this if necessary. */
148 if (cachesize_override != -1)
149 l2size = cachesize_override;
152 return; /* Again, no L2 cache is possible */
154 c->x86_cache_size = l2size;
156 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
161 * Naming convention should be: <Name> [(<Codename>)]
162 * This table only is used unless init_<vendor>() below doesn't set it;
163 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
167 /* Look up CPU names by table lookup. */
168 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
170 struct cpu_model_info *info;
172 if (c->x86_model >= 16)
173 return NULL; /* Range check */
178 info = this_cpu->c_models;
180 while (info && info->family) {
181 if (info->family == c->x86)
182 return info->model_names[c->x86_model];
185 return NULL; /* Not found */
189 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
191 char *v = c->x86_vendor_id;
195 for (i = 0; i < X86_VENDOR_NUM; i++) {
197 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
198 (cpu_devs[i]->c_ident[1] &&
199 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
202 this_cpu = cpu_devs[i];
209 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
210 printk(KERN_ERR "CPU: Your system may be unstable.\n");
212 c->x86_vendor = X86_VENDOR_UNKNOWN;
213 this_cpu = &default_cpu;
217 static int __init x86_fxsr_setup(char *s)
219 setup_clear_cpu_cap(X86_FEATURE_FXSR);
220 setup_clear_cpu_cap(X86_FEATURE_XMM);
223 __setup("nofxsr", x86_fxsr_setup);
226 static int __init x86_sep_setup(char *s)
228 setup_clear_cpu_cap(X86_FEATURE_SEP);
231 __setup("nosep", x86_sep_setup);
234 /* Standard macro to see if a specific flag is changeable */
235 static inline int flag_is_changeable_p(u32 flag)
249 : "=&r" (f1), "=&r" (f2)
252 return ((f1^f2) & flag) != 0;
256 /* Probe for the CPUID instruction */
257 static int __cpuinit have_cpuid_p(void)
259 return flag_is_changeable_p(X86_EFLAGS_ID);
262 void __init cpu_detect(struct cpuinfo_x86 *c)
264 /* Get vendor name */
265 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
266 (unsigned int *)&c->x86_vendor_id[0],
267 (unsigned int *)&c->x86_vendor_id[8],
268 (unsigned int *)&c->x86_vendor_id[4]);
271 if (c->cpuid_level >= 0x00000001) {
272 u32 junk, tfms, cap0, misc;
273 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
274 c->x86 = (tfms >> 8) & 15;
275 c->x86_model = (tfms >> 4) & 15;
277 c->x86 += (tfms >> 20) & 0xff;
279 c->x86_model += ((tfms >> 16) & 0xF) << 4;
280 c->x86_mask = tfms & 15;
281 if (cap0 & (1<<19)) {
282 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
283 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
287 static void __cpuinit early_get_cap(struct cpuinfo_x86 *c)
292 memset(&c->x86_capability, 0, sizeof c->x86_capability);
293 if (have_cpuid_p()) {
294 /* Intel-defined flags: level 0x00000001 */
295 if (c->cpuid_level >= 0x00000001) {
296 u32 capability, excap;
297 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
298 c->x86_capability[0] = capability;
299 c->x86_capability[4] = excap;
302 /* AMD-defined flags: level 0x80000001 */
303 xlvl = cpuid_eax(0x80000000);
304 if ((xlvl & 0xffff0000) == 0x80000000) {
305 if (xlvl >= 0x80000001) {
306 c->x86_capability[1] = cpuid_edx(0x80000001);
307 c->x86_capability[6] = cpuid_ecx(0x80000001);
316 * Do minimum CPU detection early.
317 * Fields really needed: vendor, cpuid_level, family, model, mask,
319 * The others are not touched to avoid unwanted side effects.
321 * WARNING: this function is only called on the BP. Don't add code here
322 * that is supposed to run on all CPUs.
324 static void __init early_cpu_detect(void)
326 struct cpuinfo_x86 *c = &boot_cpu_data;
328 c->x86_cache_alignment = 32;
329 c->x86_clflush_size = 32;
336 get_cpu_vendor(c, 1);
340 if (c->x86_vendor != X86_VENDOR_UNKNOWN &&
341 cpu_devs[c->x86_vendor]->c_early_init)
342 cpu_devs[c->x86_vendor]->c_early_init(c);
346 * The NOPL instruction is supposed to exist on all CPUs with
347 * family >= 6; unfortunately, that's not true in practice because
348 * of early VIA chips and (more importantly) broken virtualizers that
349 * are not easy to detect. In the latter case it doesn't even *fail*
350 * reliably, so probing for it doesn't even work. Disable it completely
351 * unless we can find a reliable way to detect all the broken cases.
353 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
355 clear_cpu_cap(c, X86_FEATURE_NOPL);
358 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
363 if (have_cpuid_p()) {
364 /* Get vendor name */
365 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
366 (unsigned int *)&c->x86_vendor_id[0],
367 (unsigned int *)&c->x86_vendor_id[8],
368 (unsigned int *)&c->x86_vendor_id[4]);
370 get_cpu_vendor(c, 0);
371 /* Initialize the standard set of capabilities */
372 /* Note that the vendor-specific code below might override */
373 /* Intel-defined flags: level 0x00000001 */
374 if (c->cpuid_level >= 0x00000001) {
375 u32 capability, excap;
376 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
377 c->x86_capability[0] = capability;
378 c->x86_capability[4] = excap;
379 c->x86 = (tfms >> 8) & 15;
380 c->x86_model = (tfms >> 4) & 15;
382 c->x86 += (tfms >> 20) & 0xff;
384 c->x86_model += ((tfms >> 16) & 0xF) << 4;
385 c->x86_mask = tfms & 15;
386 c->initial_apicid = (ebx >> 24) & 0xFF;
388 c->apicid = phys_pkg_id(c->initial_apicid, 0);
389 c->phys_proc_id = c->initial_apicid;
391 c->apicid = c->initial_apicid;
393 if (test_cpu_cap(c, X86_FEATURE_CLFLSH))
394 c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
396 /* Have CPUID level 0 only - unheard of */
400 /* AMD-defined flags: level 0x80000001 */
401 xlvl = cpuid_eax(0x80000000);
402 if ((xlvl & 0xffff0000) == 0x80000000) {
403 if (xlvl >= 0x80000001) {
404 c->x86_capability[1] = cpuid_edx(0x80000001);
405 c->x86_capability[6] = cpuid_ecx(0x80000001);
407 if (xlvl >= 0x80000004)
408 get_model_name(c); /* Default name */
411 init_scattered_cpuid_features(c);
416 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
418 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
419 /* Disable processor serial number */
420 unsigned long lo, hi;
421 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
423 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
424 printk(KERN_NOTICE "CPU serial number disabled.\n");
425 clear_cpu_cap(c, X86_FEATURE_PN);
427 /* Disabling the serial number may affect the cpuid level */
428 c->cpuid_level = cpuid_eax(0);
432 static int __init x86_serial_nr_setup(char *s)
434 disable_x86_serial_nr = 0;
437 __setup("serialnumber", x86_serial_nr_setup);
442 * This does the hard work of actually picking apart the CPU stuff...
444 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
448 c->loops_per_jiffy = loops_per_jiffy;
449 c->x86_cache_size = -1;
450 c->x86_vendor = X86_VENDOR_UNKNOWN;
451 c->cpuid_level = -1; /* CPUID not detected */
452 c->x86_model = c->x86_mask = 0; /* So far unknown... */
453 c->x86_vendor_id[0] = '\0'; /* Unset */
454 c->x86_model_id[0] = '\0'; /* Unset */
455 c->x86_max_cores = 1;
456 c->x86_clflush_size = 32;
457 memset(&c->x86_capability, 0, sizeof c->x86_capability);
459 if (!have_cpuid_p()) {
461 * First of all, decide if this is a 486 or higher
462 * It's a 486 if we can modify the AC flag
464 if (flag_is_changeable_p(X86_EFLAGS_AC))
472 if (this_cpu->c_identify)
473 this_cpu->c_identify(c);
476 * Vendor-specific initialization. In this section we
477 * canonicalize the feature flags, meaning if there are
478 * features a certain CPU supports which CPUID doesn't
479 * tell us, CPUID claiming incorrect flags, or other bugs,
480 * we handle them here.
482 * At the end of this section, c->x86_capability better
483 * indicate the features this CPU genuinely supports!
485 if (this_cpu->c_init)
488 /* Disable the PN if appropriate */
489 squash_the_stupid_serial_number(c);
492 * The vendor-specific functions might have changed features. Now
493 * we do "generic changes."
496 /* If the model name is still unset, do table lookup. */
497 if (!c->x86_model_id[0]) {
499 p = table_lookup_model(c);
501 strcpy(c->x86_model_id, p);
504 sprintf(c->x86_model_id, "%02x/%02x",
505 c->x86, c->x86_model);
509 * On SMP, boot_cpu_data holds the common feature set between
510 * all CPUs; so make sure that we indicate which features are
511 * common between the CPUs. The first time this routine gets
512 * executed, c == &boot_cpu_data.
514 if (c != &boot_cpu_data) {
515 /* AND the already accumulated flags with these */
516 for (i = 0 ; i < NCAPINTS ; i++)
517 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
520 /* Clear all flags overriden by options */
521 for (i = 0; i < NCAPINTS; i++)
522 c->x86_capability[i] &= ~cleared_cpu_caps[i];
524 /* Init Machine Check Exception if available. */
527 select_idle_routine(c);
530 void __init identify_boot_cpu(void)
532 identify_cpu(&boot_cpu_data);
537 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
539 BUG_ON(c == &boot_cpu_data);
546 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
548 u32 eax, ebx, ecx, edx;
549 int index_msb, core_bits;
551 cpuid(1, &eax, &ebx, &ecx, &edx);
553 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
556 smp_num_siblings = (ebx & 0xff0000) >> 16;
558 if (smp_num_siblings == 1) {
559 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
560 } else if (smp_num_siblings > 1) {
562 if (smp_num_siblings > NR_CPUS) {
563 printk(KERN_WARNING "CPU: Unsupported number of the "
564 "siblings %d", smp_num_siblings);
565 smp_num_siblings = 1;
569 index_msb = get_count_order(smp_num_siblings);
570 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
572 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
575 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
577 index_msb = get_count_order(smp_num_siblings) ;
579 core_bits = get_count_order(c->x86_max_cores);
581 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
582 ((1 << core_bits) - 1);
584 if (c->x86_max_cores > 1)
585 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
591 static __init int setup_noclflush(char *arg)
593 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
596 __setup("noclflush", setup_noclflush);
598 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
602 if (c->x86_vendor < X86_VENDOR_NUM)
603 vendor = this_cpu->c_vendor;
604 else if (c->cpuid_level >= 0)
605 vendor = c->x86_vendor_id;
607 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
608 printk("%s ", vendor);
610 if (!c->x86_model_id[0])
611 printk("%d86", c->x86);
613 printk("%s", c->x86_model_id);
615 if (c->x86_mask || c->cpuid_level >= 0)
616 printk(" stepping %02x\n", c->x86_mask);
621 static __init int setup_disablecpuid(char *arg)
624 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
625 setup_clear_cpu_cap(bit);
630 __setup("clearcpuid=", setup_disablecpuid);
632 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
634 void __init early_cpu_init(void)
636 struct cpu_vendor_dev *cvdev;
638 for (cvdev = __x86cpuvendor_start ;
639 cvdev < __x86cpuvendor_end ;
641 cpu_devs[cvdev->vendor] = cvdev->cpu_dev;
644 validate_pat_support(&boot_cpu_data);
647 /* Make sure %fs is initialized properly in idle threads */
648 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
650 memset(regs, 0, sizeof(struct pt_regs));
651 regs->fs = __KERNEL_PERCPU;
655 /* Current gdt points %fs at the "master" per-cpu area: after this,
656 * it's on the real one. */
657 void switch_to_new_gdt(void)
659 struct desc_ptr gdt_descr;
661 gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
662 gdt_descr.size = GDT_SIZE - 1;
663 load_gdt(&gdt_descr);
664 asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
668 * cpu_init() initializes state that is per-CPU. Some data is already
669 * initialized (naturally) in the bootstrap process, such as the GDT
670 * and IDT. We reload them nevertheless, this function acts as a
671 * 'CPU state barrier', nothing should get across.
673 void __cpuinit cpu_init(void)
675 int cpu = smp_processor_id();
676 struct task_struct *curr = current;
677 struct tss_struct *t = &per_cpu(init_tss, cpu);
678 struct thread_struct *thread = &curr->thread;
680 if (cpu_test_and_set(cpu, cpu_initialized)) {
681 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
682 for (;;) local_irq_enable();
685 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
687 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
688 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
690 load_idt(&idt_descr);
694 * Set up and load the per-CPU TSS and LDT
696 atomic_inc(&init_mm.mm_count);
697 curr->active_mm = &init_mm;
700 enter_lazy_tlb(&init_mm, curr);
703 set_tss_desc(cpu, t);
705 load_LDT(&init_mm.context);
707 #ifdef CONFIG_DOUBLEFAULT
708 /* Set up doublefault TSS pointer in the GDT */
709 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
713 asm volatile ("mov %0, %%gs" : : "r" (0));
715 /* Clear all 6 debug registers: */
724 * Force FPU initialization:
726 current_thread_info()->status = 0;
728 mxcsr_feature_mask_init();