arch/x86/kernel/genapic_flat_64.c

   1 /*
   2  * Copyright 2004 James Cleverdon, IBM.
   3  * Subject to the GNU Public License, v.2
   4  *
   5  * Flat APIC subarch code.
   6  *
   7  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
   8  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
   9  * James Cleverdon.
  10  */
  11 #include <linux/errno.h>
  12 #include <linux/threads.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/string.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ctype.h>
  17 #include <linux/init.h>
  18 #include <linux/hardirq.h>
  19 #include <asm/smp.h>
  20 #include <asm/ipi.h>
  21 #include <asm/genapic.h>
  22 #include <mach_apicdef.h>
  23
  24 static cpumask_t flat_target_cpus(void)
  25 {
  26         return cpu_online_map;
  27 }
  28
  29 static cpumask_t flat_vector_allocation_domain(int cpu)
  30 {
  31         /* Careful. Some cpus do not strictly honor the set of cpus
  32          * specified in the interrupt destination when using lowest
  33          * priority interrupt delivery mode.
  34          *
  35          * In particular there was a hyperthreading cpu observed to
  36          * deliver interrupts to the wrong hyperthread when only one
  37          * hyperthread was specified in the interrupt desitination.
  38          */
  39         cpumask_t domain = { { [0] = APIC_ALL_CPUS, } };
  40         return domain;
  41 }
  42
  43 /*
  44  * Set up the logical destination ID.
  45  *
  46  * Intel recommends to set DFR, LDR and TPR before enabling
  47  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
  48  * document number 292116).  So here it goes...
  49  */
  50 static void flat_init_apic_ldr(void)
  51 {
  52         unsigned long val;
  53         unsigned long num, id;
  54
  55         num = smp_processor_id();
  56         id = 1UL << num;
  57         apic_write(APIC_DFR, APIC_DFR_FLAT);
  58         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  59         val |= SET_APIC_LOGICAL_ID(id);
  60         apic_write(APIC_LDR, val);
  61 }
  62
  63 static void flat_send_IPI_mask(cpumask_t cpumask, int vector)
  64 {
  65         unsigned long mask = cpus_addr(cpumask)[0];
  66         unsigned long flags;
  67
  68         local_irq_save(flags);
  69         __send_IPI_dest_field(mask, vector, APIC_DEST_LOGICAL);
  70         local_irq_restore(flags);
  71 }
  72
  73 static void flat_send_IPI_allbutself(int vector)
  74 {
  75 #ifdef  CONFIG_HOTPLUG_CPU
  76         int hotplug = 1;
  77 #else
  78         int hotplug = 0;
  79 #endif
  80         if (hotplug || vector == NMI_VECTOR) {
  81                 cpumask_t allbutme = cpu_online_map;
  82
  83                 cpu_clear(smp_processor_id(), allbutme);
  84
  85                 if (!cpus_empty(allbutme))
  86                         flat_send_IPI_mask(allbutme, vector);
  87         } else if (num_online_cpus() > 1) {
  88                 __send_IPI_shortcut(APIC_DEST_ALLBUT, vector,APIC_DEST_LOGICAL);
  89         }
  90 }
  91
  92 static void flat_send_IPI_all(int vector)
  93 {
  94         if (vector == NMI_VECTOR)
  95                 flat_send_IPI_mask(cpu_online_map, vector);
  96         else
  97                 __send_IPI_shortcut(APIC_DEST_ALLINC, vector, APIC_DEST_LOGICAL);
  98 }
  99
 100 static unsigned int get_apic_id(unsigned long x)
 101 {
 102         unsigned int id;
 103
 104         id = (((x)>>24) & 0xFFu);
 105         return id;
 106 }
 107
 108 static unsigned long set_apic_id(unsigned int id)
 109 {
 110         unsigned long x;
 111
 112         x = ((id & 0xFFu)<<24);
 113         return x;
 114 }
 115
 116 static unsigned int read_xapic_id(void)
 117 {
 118         unsigned int id;
 119
 120         id = get_apic_id(apic_read(APIC_ID));
 121         return id;
 122 }
 123
 124 static int flat_apic_id_registered(void)
 125 {
 126         return physid_isset(read_xapic_id(), phys_cpu_present_map);
 127 }
 128
 129 static unsigned int flat_cpu_mask_to_apicid(cpumask_t cpumask)
 130 {
 131         return cpus_addr(cpumask)[0] & APIC_ALL_CPUS;
 132 }
 133
 134 static unsigned int phys_pkg_id(int index_msb)
 135 {
 136         return hard_smp_processor_id() >> index_msb;
 137 }
 138
 139 struct genapic apic_flat =  {
 140         .name = "flat",
 141         .int_delivery_mode = dest_LowestPrio,
 142         .int_dest_mode = (APIC_DEST_LOGICAL != 0),
 143         .target_cpus = flat_target_cpus,
 144         .vector_allocation_domain = flat_vector_allocation_domain,
 145         .apic_id_registered = flat_apic_id_registered,
 146         .init_apic_ldr = flat_init_apic_ldr,
 147         .send_IPI_all = flat_send_IPI_all,
 148         .send_IPI_allbutself = flat_send_IPI_allbutself,
 149         .send_IPI_mask = flat_send_IPI_mask,
 150         .send_IPI_self = apic_send_IPI_self,
 151         .cpu_mask_to_apicid = flat_cpu_mask_to_apicid,
 152         .phys_pkg_id = phys_pkg_id,
 153         .get_apic_id = get_apic_id,
 154         .set_apic_id = set_apic_id,
 155         .apic_id_mask = (0xFFu<<24),
 156 };
 157
 158 /*
 159  * Physflat mode is used when there are more than 8 CPUs on a AMD system.
 160  * We cannot use logical delivery in this case because the mask
 161  * overflows, so use physical mode.
 162  */
 163
 164 static cpumask_t physflat_target_cpus(void)
 165 {
 166         return cpu_online_map;
 167 }
 168
 169 static cpumask_t physflat_vector_allocation_domain(int cpu)
 170 {
 171         return cpumask_of_cpu(cpu);
 172 }
 173
 174 static void physflat_send_IPI_mask(cpumask_t cpumask, int vector)
 175 {
 176         send_IPI_mask_sequence(cpumask, vector);
 177 }
 178
 179 static void physflat_send_IPI_allbutself(int vector)
 180 {
 181         cpumask_t allbutme = cpu_online_map;
 182
 183         cpu_clear(smp_processor_id(), allbutme);
 184         physflat_send_IPI_mask(allbutme, vector);
 185 }
 186
 187 static void physflat_send_IPI_all(int vector)
 188 {
 189         physflat_send_IPI_mask(cpu_online_map, vector);
 190 }
 191
 192 static unsigned int physflat_cpu_mask_to_apicid(cpumask_t cpumask)
 193 {
 194         int cpu;
 195
 196         /*
 197          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 198          * May as well be the first.
 199          */
 200         cpu = first_cpu(cpumask);
 201         if ((unsigned)cpu < NR_CPUS)
 202                 return per_cpu(x86_cpu_to_apicid, cpu);
 203         else
 204                 return BAD_APICID;
 205 }
 206
 207 struct genapic apic_physflat =  {
 208         .name = "physical flat",
 209         .int_delivery_mode = dest_Fixed,
 210         .int_dest_mode = (APIC_DEST_PHYSICAL != 0),
 211         .target_cpus = physflat_target_cpus,
 212         .vector_allocation_domain = physflat_vector_allocation_domain,
 213         .apic_id_registered = flat_apic_id_registered,
 214         .init_apic_ldr = flat_init_apic_ldr,/*not needed, but shouldn't hurt*/
 215         .send_IPI_all = physflat_send_IPI_all,
 216         .send_IPI_allbutself = physflat_send_IPI_allbutself,
 217         .send_IPI_mask = physflat_send_IPI_mask,
 218         .send_IPI_self = apic_send_IPI_self,
 219         .cpu_mask_to_apicid = physflat_cpu_mask_to_apicid,
 220         .phys_pkg_id = phys_pkg_id,
 221         .get_apic_id = get_apic_id,
 222         .set_apic_id = set_apic_id,
 223         .apic_id_mask = (0xFFu<<24),
 224 };