2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/bootmem.h>
20 #include <linux/kernel_stat.h>
21 #include <linux/mc146818rtc.h>
22 #include <linux/acpi.h>
23 #include <linux/module.h>
27 #include <asm/mpspec.h>
28 #include <asm/pgalloc.h>
29 #include <asm/io_apic.h>
30 #include <asm/proto.h>
32 #include <asm/bios_ebda.h>
34 #include <mach_apic.h>
36 /* Have we found an MP table */
38 unsigned int __cpuinitdata maxcpus = NR_CPUS;
41 * Various Linux-internal data structures created from the
44 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
45 int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 };
47 static int mp_current_pci_id = 0;
48 /* I/O APIC entries */
49 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
51 /* # of MP IRQ source entries */
52 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
54 /* MP IRQ source entries */
59 /* Processor that is doing the boot up */
60 unsigned int boot_cpu_physical_apicid = -1U;
61 EXPORT_SYMBOL(boot_cpu_physical_apicid);
63 /* Internal processor count */
64 unsigned int num_processors;
66 unsigned disabled_cpus __cpuinitdata;
69 u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata
70 = {[0 ... NR_CPUS - 1] = BAD_APICID };
71 void *x86_bios_cpu_apicid_early_ptr;
73 DEFINE_PER_CPU(u16, x86_bios_cpu_apicid) = BAD_APICID;
74 EXPORT_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
77 * Intel MP BIOS table parsing routines:
81 * Checksum an MP configuration block.
84 static int __init mpf_checksum(unsigned char *mp, int len)
94 void __cpuinit generic_processor_info(int apicid, int version)
99 if (num_processors >= NR_CPUS) {
100 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
101 " Processor ignored.\n", NR_CPUS);
105 if (num_processors >= maxcpus) {
106 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
107 " Processor ignored.\n", maxcpus);
112 cpus_complement(tmp_map, cpu_present_map);
113 cpu = first_cpu(tmp_map);
115 physid_set(apicid, phys_cpu_present_map);
116 if (apicid == boot_cpu_physical_apicid) {
118 * x86_bios_cpu_apicid is required to have processors listed
119 * in same order as logical cpu numbers. Hence the first
120 * entry is BSP, and so on.
124 /* are we being called early in kernel startup? */
125 if (x86_cpu_to_apicid_early_ptr) {
126 u16 *cpu_to_apicid = x86_cpu_to_apicid_early_ptr;
127 u16 *bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
129 cpu_to_apicid[cpu] = apicid;
130 bios_cpu_apicid[cpu] = apicid;
132 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
133 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
136 cpu_set(cpu, cpu_possible_map);
137 cpu_set(cpu, cpu_present_map);
140 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
142 char *bootup_cpu = "";
144 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
148 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
149 bootup_cpu = " (Bootup-CPU)";
150 boot_cpu_physical_apicid = m->mpc_apicid;
153 printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);
154 generic_processor_info(m->mpc_apicid, 0);
157 static void __init MP_bus_info(struct mpc_config_bus *m)
161 memcpy(str, m->mpc_bustype, 6);
163 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
165 if (strncmp(str, "ISA", 3) == 0) {
166 set_bit(m->mpc_busid, mp_bus_not_pci);
167 } else if (strncmp(str, "PCI", 3) == 0) {
168 clear_bit(m->mpc_busid, mp_bus_not_pci);
169 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
172 printk(KERN_ERR "Unknown bustype %s\n", str);
176 static int bad_ioapic(unsigned long address)
178 if (nr_ioapics >= MAX_IO_APICS) {
179 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
180 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
181 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
184 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
185 " found in table, skipping!\n");
191 static void __init MP_ioapic_info(struct mpc_config_ioapic *m)
193 if (!(m->mpc_flags & MPC_APIC_USABLE))
196 printk(KERN_INFO "I/O APIC #%d at 0x%X.\n", m->mpc_apicid,
199 if (bad_ioapic(m->mpc_apicaddr))
202 mp_ioapics[nr_ioapics] = *m;
206 static void __init MP_intsrc_info(struct mpc_config_intsrc *m)
208 mp_irqs[mp_irq_entries] = *m;
209 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
210 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
211 m->mpc_irqtype, m->mpc_irqflag & 3,
212 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
213 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
214 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
215 panic("Max # of irq sources exceeded!!\n");
218 static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m)
220 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
221 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
222 m->mpc_irqtype, m->mpc_irqflag & 3,
223 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid,
224 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
230 static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
233 int count = sizeof(*mpc);
234 unsigned char *mpt = ((unsigned char *)mpc) + count;
236 if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) {
237 printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n",
238 mpc->mpc_signature[0],
239 mpc->mpc_signature[1],
240 mpc->mpc_signature[2], mpc->mpc_signature[3]);
243 if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) {
244 printk(KERN_ERR "MPTABLE: checksum error!\n");
247 if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) {
248 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
252 if (!mpc->mpc_lapic) {
253 printk(KERN_ERR "MPTABLE: null local APIC address!\n");
256 memcpy(str, mpc->mpc_oem, 8);
258 printk(KERN_INFO "MPTABLE: OEM ID: %s ", str);
260 memcpy(str, mpc->mpc_productid, 12);
262 printk(KERN_INFO "MPTABLE: Product ID: %s ", str);
264 printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic);
266 /* save the local APIC address, it might be non-default */
268 mp_lapic_addr = mpc->mpc_lapic;
274 * Now process the configuration blocks.
276 while (count < mpc->mpc_length) {
280 struct mpc_config_processor *m =
281 (struct mpc_config_processor *)mpt;
283 MP_processor_info(m);
290 struct mpc_config_bus *m =
291 (struct mpc_config_bus *)mpt;
299 struct mpc_config_ioapic *m =
300 (struct mpc_config_ioapic *)mpt;
308 struct mpc_config_intsrc *m =
309 (struct mpc_config_intsrc *)mpt;
318 struct mpc_config_lintsrc *m =
319 (struct mpc_config_lintsrc *)mpt;
327 setup_apic_routing();
329 printk(KERN_ERR "MPTABLE: no processors registered!\n");
330 return num_processors;
333 static int __init ELCR_trigger(unsigned int irq)
337 port = 0x4d0 + (irq >> 3);
338 return (inb(port) >> (irq & 7)) & 1;
341 static void __init construct_default_ioirq_mptable(int mpc_default_type)
343 struct mpc_config_intsrc intsrc;
345 int ELCR_fallback = 0;
347 intsrc.mpc_type = MP_INTSRC;
348 intsrc.mpc_irqflag = 0; /* conforming */
349 intsrc.mpc_srcbus = 0;
350 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
352 intsrc.mpc_irqtype = mp_INT;
355 * If true, we have an ISA/PCI system with no IRQ entries
356 * in the MP table. To prevent the PCI interrupts from being set up
357 * incorrectly, we try to use the ELCR. The sanity check to see if
358 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
359 * never be level sensitive, so we simply see if the ELCR agrees.
360 * If it does, we assume it's valid.
362 if (mpc_default_type == 5) {
363 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... "
364 "falling back to ELCR\n");
366 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) ||
368 printk(KERN_ERR "ELCR contains invalid data... "
372 "Using ELCR to identify PCI interrupts\n");
377 for (i = 0; i < 16; i++) {
378 switch (mpc_default_type) {
380 if (i == 0 || i == 13)
381 continue; /* IRQ0 & IRQ13 not connected */
385 continue; /* IRQ2 is never connected */
390 * If the ELCR indicates a level-sensitive interrupt, we
391 * copy that information over to the MP table in the
392 * irqflag field (level sensitive, active high polarity).
395 intsrc.mpc_irqflag = 13;
397 intsrc.mpc_irqflag = 0;
400 intsrc.mpc_srcbusirq = i;
401 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
402 MP_intsrc_info(&intsrc);
405 intsrc.mpc_irqtype = mp_ExtINT;
406 intsrc.mpc_srcbusirq = 0;
407 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
408 MP_intsrc_info(&intsrc);
411 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
413 struct mpc_config_processor processor;
414 struct mpc_config_bus bus;
415 struct mpc_config_ioapic ioapic;
416 struct mpc_config_lintsrc lintsrc;
417 int linttypes[2] = { mp_ExtINT, mp_NMI };
421 * local APIC has default address
423 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
426 * 2 CPUs, numbered 0 & 1.
428 processor.mpc_type = MP_PROCESSOR;
429 processor.mpc_apicver = 0;
430 processor.mpc_cpuflag = CPU_ENABLED;
431 processor.mpc_cpufeature = 0;
432 processor.mpc_featureflag = 0;
433 processor.mpc_reserved[0] = 0;
434 processor.mpc_reserved[1] = 0;
435 for (i = 0; i < 2; i++) {
436 processor.mpc_apicid = i;
437 MP_processor_info(&processor);
440 bus.mpc_type = MP_BUS;
442 switch (mpc_default_type) {
444 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
449 memcpy(bus.mpc_bustype, "ISA ", 6);
453 if (mpc_default_type > 4) {
455 memcpy(bus.mpc_bustype, "PCI ", 6);
459 ioapic.mpc_type = MP_IOAPIC;
460 ioapic.mpc_apicid = 2;
461 ioapic.mpc_apicver = 0;
462 ioapic.mpc_flags = MPC_APIC_USABLE;
463 ioapic.mpc_apicaddr = 0xFEC00000;
464 MP_ioapic_info(&ioapic);
467 * We set up most of the low 16 IO-APIC pins according to MPS rules.
469 construct_default_ioirq_mptable(mpc_default_type);
471 lintsrc.mpc_type = MP_LINTSRC;
472 lintsrc.mpc_irqflag = 0; /* conforming */
473 lintsrc.mpc_srcbusid = 0;
474 lintsrc.mpc_srcbusirq = 0;
475 lintsrc.mpc_destapic = MP_APIC_ALL;
476 for (i = 0; i < 2; i++) {
477 lintsrc.mpc_irqtype = linttypes[i];
478 lintsrc.mpc_destapiclint = i;
479 MP_lintsrc_info(&lintsrc);
483 static struct intel_mp_floating *mpf_found;
486 * Scan the memory blocks for an SMP configuration block.
488 static void __init __get_smp_config(unsigned early)
490 struct intel_mp_floating *mpf = mpf_found;
492 if (acpi_lapic && early)
495 * ACPI supports both logical (e.g. Hyper-Threading) and physical
496 * processors, where MPS only supports physical.
498 if (acpi_lapic && acpi_ioapic) {
499 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration "
502 } else if (acpi_lapic)
503 printk(KERN_INFO "Using ACPI for processor (LAPIC) "
504 "configuration information\n");
506 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n",
507 mpf->mpf_specification);
510 * Now see if we need to read further.
512 if (mpf->mpf_feature1 != 0) {
515 * local APIC has default address
517 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
521 printk(KERN_INFO "Default MP configuration #%d\n",
523 construct_default_ISA_mptable(mpf->mpf_feature1);
525 } else if (mpf->mpf_physptr) {
528 * Read the physical hardware table. Anything here will
529 * override the defaults.
531 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) {
532 smp_found_config = 0;
534 "BIOS bug, MP table errors detected!...\n");
535 printk(KERN_ERR "... disabling SMP support. "
536 "(tell your hw vendor)\n");
543 * If there are no explicit MP IRQ entries, then we are
544 * broken. We set up most of the low 16 IO-APIC pins to
545 * ISA defaults and hope it will work.
547 if (!mp_irq_entries) {
548 struct mpc_config_bus bus;
550 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, "
551 "using default mptable. "
552 "(tell your hw vendor)\n");
554 bus.mpc_type = MP_BUS;
556 memcpy(bus.mpc_bustype, "ISA ", 6);
559 construct_default_ioirq_mptable(0);
566 printk(KERN_INFO "Processors: %d\n", num_processors);
568 * Only use the first configuration found.
572 void __init early_get_smp_config(void)
577 void __init get_smp_config(void)
582 static int __init smp_scan_config(unsigned long base, unsigned long length,
585 extern void __bad_mpf_size(void);
586 unsigned int *bp = phys_to_virt(base);
587 struct intel_mp_floating *mpf;
589 Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length);
590 if (sizeof(*mpf) != 16)
594 mpf = (struct intel_mp_floating *)bp;
595 if ((*bp == SMP_MAGIC_IDENT) &&
596 (mpf->mpf_length == 1) &&
597 !mpf_checksum((unsigned char *)bp, 16) &&
598 ((mpf->mpf_specification == 1)
599 || (mpf->mpf_specification == 4))) {
601 smp_found_config = 1;
607 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
608 if (mpf->mpf_physptr)
609 reserve_bootmem_generic(mpf->mpf_physptr,
619 static void __init __find_smp_config(unsigned reserve)
621 unsigned int address;
624 * FIXME: Linux assumes you have 640K of base ram..
625 * this continues the error...
627 * 1) Scan the bottom 1K for a signature
628 * 2) Scan the top 1K of base RAM
629 * 3) Scan the 64K of bios
631 if (smp_scan_config(0x0, 0x400, reserve) ||
632 smp_scan_config(639 * 0x400, 0x400, reserve) ||
633 smp_scan_config(0xF0000, 0x10000, reserve))
636 * If it is an SMP machine we should know now.
638 * there is a real-mode segmented pointer pointing to the
639 * 4K EBDA area at 0x40E, calculate and scan it here.
641 * NOTE! There are Linux loaders that will corrupt the EBDA
642 * area, and as such this kind of SMP config may be less
643 * trustworthy, simply because the SMP table may have been
644 * stomped on during early boot. These loaders are buggy and
647 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
650 address = get_bios_ebda();
652 smp_scan_config(address, 0x400, reserve);
655 void __init early_find_smp_config(void)
657 __find_smp_config(0);
660 void __init find_smp_config(void)
662 __find_smp_config(1);
665 /* --------------------------------------------------------------------------
666 ACPI-based MP Configuration
667 -------------------------------------------------------------------------- */
671 void __init mp_register_lapic_address(u64 address)
673 mp_lapic_addr = (unsigned long)address;
674 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
675 if (boot_cpu_physical_apicid == -1U)
676 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
679 void __cpuinit mp_register_lapic(u8 id, u8 enabled)
686 generic_processor_info(id, 0);
690 #define MP_MAX_IOAPIC_PIN 127
692 static struct mp_ioapic_routing {
696 u32 pin_programmed[4];
697 } mp_ioapic_routing[MAX_IO_APICS];
699 static int mp_find_ioapic(int gsi)
703 /* Find the IOAPIC that manages this GSI. */
704 for (i = 0; i < nr_ioapics; i++) {
705 if ((gsi >= mp_ioapic_routing[i].gsi_base)
706 && (gsi <= mp_ioapic_routing[i].gsi_end))
710 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
714 static u8 uniq_ioapic_id(u8 id)
717 DECLARE_BITMAP(used, 256);
718 bitmap_zero(used, 256);
719 for (i = 0; i < nr_ioapics; i++) {
720 struct mpc_config_ioapic *ia = &mp_ioapics[i];
721 __set_bit(ia->mpc_apicid, used);
723 if (!test_bit(id, used))
725 return find_first_zero_bit(used, 256);
728 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
732 if (bad_ioapic(address))
737 mp_ioapics[idx].mpc_type = MP_IOAPIC;
738 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
739 mp_ioapics[idx].mpc_apicaddr = address;
741 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
742 mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
743 mp_ioapics[idx].mpc_apicver = 0;
746 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
747 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
749 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
750 mp_ioapic_routing[idx].gsi_base = gsi_base;
751 mp_ioapic_routing[idx].gsi_end = gsi_base +
752 io_apic_get_redir_entries(idx);
754 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, "
755 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
756 mp_ioapics[idx].mpc_apicaddr,
757 mp_ioapic_routing[idx].gsi_base,
758 mp_ioapic_routing[idx].gsi_end);
763 void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
765 struct mpc_config_intsrc intsrc;
770 * Convert 'gsi' to 'ioapic.pin'.
772 ioapic = mp_find_ioapic(gsi);
775 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
778 * TBD: This check is for faulty timer entries, where the override
779 * erroneously sets the trigger to level, resulting in a HUGE
780 * increase of timer interrupts!
782 if ((bus_irq == 0) && (trigger == 3))
785 intsrc.mpc_type = MP_INTSRC;
786 intsrc.mpc_irqtype = mp_INT;
787 intsrc.mpc_irqflag = (trigger << 2) | polarity;
788 intsrc.mpc_srcbus = MP_ISA_BUS;
789 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
790 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
791 intsrc.mpc_dstirq = pin; /* INTIN# */
793 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
794 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
795 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
796 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
798 mp_irqs[mp_irq_entries] = intsrc;
799 if (++mp_irq_entries == MAX_IRQ_SOURCES)
800 panic("Max # of irq sources exceeded!\n");
803 void __init mp_config_acpi_legacy_irqs(void)
805 struct mpc_config_intsrc intsrc;
810 * Fabricate the legacy ISA bus (bus #31).
812 set_bit(MP_ISA_BUS, mp_bus_not_pci);
815 * Locate the IOAPIC that manages the ISA IRQs (0-15).
817 ioapic = mp_find_ioapic(0);
821 intsrc.mpc_type = MP_INTSRC;
822 intsrc.mpc_irqflag = 0; /* Conforming */
823 intsrc.mpc_srcbus = MP_ISA_BUS;
824 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
827 * Use the default configuration for the IRQs 0-15. Unless
828 * overridden by (MADT) interrupt source override entries.
830 for (i = 0; i < 16; i++) {
833 for (idx = 0; idx < mp_irq_entries; idx++) {
834 struct mpc_config_intsrc *irq = mp_irqs + idx;
836 /* Do we already have a mapping for this ISA IRQ? */
837 if (irq->mpc_srcbus == MP_ISA_BUS
838 && irq->mpc_srcbusirq == i)
841 /* Do we already have a mapping for this IOAPIC pin */
842 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
843 (irq->mpc_dstirq == i))
847 if (idx != mp_irq_entries) {
848 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
849 continue; /* IRQ already used */
852 intsrc.mpc_irqtype = mp_INT;
853 intsrc.mpc_srcbusirq = i; /* Identity mapped */
854 intsrc.mpc_dstirq = i;
856 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
857 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
858 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
859 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
862 mp_irqs[mp_irq_entries] = intsrc;
863 if (++mp_irq_entries == MAX_IRQ_SOURCES)
864 panic("Max # of irq sources exceeded!\n");
868 int mp_register_gsi(u32 gsi, int triggering, int polarity)
874 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
877 /* Don't set up the ACPI SCI because it's already set up */
878 if (acpi_gbl_FADT.sci_interrupt == gsi)
881 ioapic = mp_find_ioapic(gsi);
883 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
887 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
890 * Avoid pin reprogramming. PRTs typically include entries
891 * with redundant pin->gsi mappings (but unique PCI devices);
892 * we only program the IOAPIC on the first.
894 bit = ioapic_pin % 32;
895 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
897 printk(KERN_ERR "Invalid reference to IOAPIC pin "
898 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
902 if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
903 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
904 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
908 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit);
910 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
911 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
912 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
915 #endif /* CONFIG_ACPI */