2 * Dynamic DMA mapping support for AMD Hammer.
4 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
5 * This allows to use PCI devices that only support 32bit addresses on systems
8 * See Documentation/DMA-mapping.txt for the interface specification.
10 * Copyright 2002 Andi Kleen, SuSE Labs.
11 * Subject to the GNU General Public License v2 only.
14 #include <linux/types.h>
15 #include <linux/ctype.h>
16 #include <linux/agp_backend.h>
17 #include <linux/init.h>
19 #include <linux/string.h>
20 #include <linux/spinlock.h>
21 #include <linux/pci.h>
22 #include <linux/module.h>
23 #include <linux/topology.h>
24 #include <linux/interrupt.h>
25 #include <linux/bitops.h>
26 #include <linux/kdebug.h>
27 #include <linux/scatterlist.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/sysdev.h>
30 #include <asm/atomic.h>
33 #include <asm/pgtable.h>
34 #include <asm/proto.h>
35 #include <asm/iommu.h>
37 #include <asm/cacheflush.h>
38 #include <asm/swiotlb.h>
42 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
43 static unsigned long iommu_size; /* size of remapping area bytes */
44 static unsigned long iommu_pages; /* .. and in pages */
46 static u32 *iommu_gatt_base; /* Remapping table */
49 * If this is disabled the IOMMU will use an optimized flushing strategy
50 * of only flushing when an mapping is reused. With it true the GART is
51 * flushed for every mapping. Problem is that doing the lazy flush seems
52 * to trigger bugs with some popular PCI cards, in particular 3ware (but
53 * has been also also seen with Qlogic at least).
55 int iommu_fullflush = 1;
57 /* Allocation bitmap for the remapping area: */
58 static DEFINE_SPINLOCK(iommu_bitmap_lock);
59 /* Guarded by iommu_bitmap_lock: */
60 static unsigned long *iommu_gart_bitmap;
62 static u32 gart_unmapped_entry;
65 #define GPTE_COHERENT 2
66 #define GPTE_ENCODE(x) \
67 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
68 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
70 #define EMERGENCY_PAGES 32 /* = 128KB */
73 #define AGPEXTERN extern
78 /* backdoor interface to AGP driver */
79 AGPEXTERN int agp_memory_reserved;
80 AGPEXTERN __u32 *agp_gatt_table;
82 static unsigned long next_bit; /* protected by iommu_bitmap_lock */
83 static int need_flush; /* global flush state. set for each gart wrap */
85 static unsigned long alloc_iommu(struct device *dev, int size,
86 unsigned long align_mask)
88 unsigned long offset, flags;
89 unsigned long boundary_size;
90 unsigned long base_index;
92 base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
93 PAGE_SIZE) >> PAGE_SHIFT;
94 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
95 PAGE_SIZE) >> PAGE_SHIFT;
97 spin_lock_irqsave(&iommu_bitmap_lock, flags);
98 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
99 size, base_index, boundary_size, align_mask);
102 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
103 size, base_index, boundary_size,
107 next_bit = offset+size;
108 if (next_bit >= iommu_pages) {
115 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
120 static void free_iommu(unsigned long offset, int size)
124 spin_lock_irqsave(&iommu_bitmap_lock, flags);
125 iommu_area_free(iommu_gart_bitmap, offset, size);
126 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
130 * Use global flush state to avoid races with multiple flushers.
132 static void flush_gart(void)
136 spin_lock_irqsave(&iommu_bitmap_lock, flags);
141 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
144 #ifdef CONFIG_IOMMU_LEAK
146 #define SET_LEAK(x) \
148 if (iommu_leak_tab) \
149 iommu_leak_tab[x] = __builtin_return_address(0);\
152 #define CLEAR_LEAK(x) \
154 if (iommu_leak_tab) \
155 iommu_leak_tab[x] = NULL; \
158 /* Debugging aid for drivers that don't free their IOMMU tables */
159 static void **iommu_leak_tab;
160 static int leak_trace;
161 static int iommu_leak_pages = 20;
163 static void dump_leak(void)
168 if (dump || !iommu_leak_tab)
171 show_stack(NULL, NULL);
173 /* Very crude. dump some from the end of the table too */
174 printk(KERN_DEBUG "Dumping %d pages from end of IOMMU:\n",
176 for (i = 0; i < iommu_leak_pages; i += 2) {
177 printk(KERN_DEBUG "%lu: ", iommu_pages-i);
178 printk_address((unsigned long) iommu_leak_tab[iommu_pages-i], 0);
179 printk(KERN_CONT "%c", (i+1)%2 == 0 ? '\n' : ' ');
181 printk(KERN_DEBUG "\n");
185 # define CLEAR_LEAK(x)
188 static void iommu_full(struct device *dev, size_t size, int dir)
191 * Ran out of IOMMU space for this operation. This is very bad.
192 * Unfortunately the drivers cannot handle this operation properly.
193 * Return some non mapped prereserved space in the aperture and
194 * let the Northbridge deal with it. This will result in garbage
195 * in the IO operation. When the size exceeds the prereserved space
196 * memory corruption will occur or random memory will be DMAed
197 * out. Hopefully no network devices use single mappings that big.
200 dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
202 if (size > PAGE_SIZE*EMERGENCY_PAGES) {
203 if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
204 panic("PCI-DMA: Memory would be corrupted\n");
205 if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
207 "PCI-DMA: Random memory would be DMAed\n");
209 #ifdef CONFIG_IOMMU_LEAK
215 need_iommu(struct device *dev, unsigned long addr, size_t size)
217 u64 mask = *dev->dma_mask;
218 int high = addr + size > mask;
228 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
230 u64 mask = *dev->dma_mask;
231 int high = addr + size > mask;
237 /* Map a single continuous physical area into the IOMMU.
238 * Caller needs to check if the iommu is needed and flush.
240 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
241 size_t size, int dir, unsigned long align_mask)
243 unsigned long npages = iommu_num_pages(phys_mem, size);
244 unsigned long iommu_page = alloc_iommu(dev, npages, align_mask);
247 if (iommu_page == -1) {
248 if (!nonforced_iommu(dev, phys_mem, size))
250 if (panic_on_overflow)
251 panic("dma_map_area overflow %lu bytes\n", size);
252 iommu_full(dev, size, dir);
253 return bad_dma_address;
256 for (i = 0; i < npages; i++) {
257 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
258 SET_LEAK(iommu_page + i);
259 phys_mem += PAGE_SIZE;
261 return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
265 gart_map_simple(struct device *dev, phys_addr_t paddr, size_t size, int dir)
268 unsigned long align_mask;
270 align_mask = (1UL << get_order(size)) - 1;
271 map = dma_map_area(dev, paddr, size, dir, align_mask);
278 /* Map a single area into the IOMMU */
280 gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir)
287 if (!need_iommu(dev, paddr, size))
290 bus = dma_map_area(dev, paddr, size, dir, 0);
297 * Free a DMA mapping.
299 static void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
300 size_t size, int direction)
302 unsigned long iommu_page;
306 if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
307 dma_addr >= iommu_bus_base + iommu_size)
310 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
311 npages = iommu_num_pages(dma_addr, size);
312 for (i = 0; i < npages; i++) {
313 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
314 CLEAR_LEAK(iommu_page + i);
316 free_iommu(iommu_page, npages);
320 * Wrapper for pci_unmap_single working with scatterlists.
323 gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
325 struct scatterlist *s;
328 for_each_sg(sg, s, nents, i) {
329 if (!s->dma_length || !s->length)
331 gart_unmap_single(dev, s->dma_address, s->dma_length, dir);
335 /* Fallback for dma_map_sg in case of overflow */
336 static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
339 struct scatterlist *s;
342 #ifdef CONFIG_IOMMU_DEBUG
343 printk(KERN_DEBUG "dma_map_sg overflow\n");
346 for_each_sg(sg, s, nents, i) {
347 unsigned long addr = sg_phys(s);
349 if (nonforced_iommu(dev, addr, s->length)) {
350 addr = dma_map_area(dev, addr, s->length, dir, 0);
351 if (addr == bad_dma_address) {
353 gart_unmap_sg(dev, sg, i, dir);
355 sg[0].dma_length = 0;
359 s->dma_address = addr;
360 s->dma_length = s->length;
367 /* Map multiple scatterlist entries continuous into the first. */
368 static int __dma_map_cont(struct device *dev, struct scatterlist *start,
369 int nelems, struct scatterlist *sout,
372 unsigned long iommu_start = alloc_iommu(dev, pages, 0);
373 unsigned long iommu_page = iommu_start;
374 struct scatterlist *s;
377 if (iommu_start == -1)
380 for_each_sg(start, s, nelems, i) {
381 unsigned long pages, addr;
382 unsigned long phys_addr = s->dma_address;
384 BUG_ON(s != start && s->offset);
386 sout->dma_address = iommu_bus_base;
387 sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
388 sout->dma_length = s->length;
390 sout->dma_length += s->length;
394 pages = iommu_num_pages(s->offset, s->length);
396 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
397 SET_LEAK(iommu_page);
402 BUG_ON(iommu_page - iommu_start != pages);
408 dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
409 struct scatterlist *sout, unsigned long pages, int need)
413 sout->dma_address = start->dma_address;
414 sout->dma_length = start->length;
417 return __dma_map_cont(dev, start, nelems, sout, pages);
421 * DMA map all entries in a scatterlist.
422 * Merge chunks that have page aligned sizes into a continuous mapping.
425 gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
427 struct scatterlist *s, *ps, *start_sg, *sgmap;
428 int need = 0, nextneed, i, out, start;
429 unsigned long pages = 0;
430 unsigned int seg_size;
431 unsigned int max_seg_size;
441 start_sg = sgmap = sg;
443 max_seg_size = dma_get_max_seg_size(dev);
444 ps = NULL; /* shut up gcc */
445 for_each_sg(sg, s, nents, i) {
446 dma_addr_t addr = sg_phys(s);
448 s->dma_address = addr;
449 BUG_ON(s->length == 0);
451 nextneed = need_iommu(dev, addr, s->length);
453 /* Handle the previous not yet processed entries */
456 * Can only merge when the last chunk ends on a
457 * page boundary and the new one doesn't have an
460 if (!iommu_merge || !nextneed || !need || s->offset ||
461 (s->length + seg_size > max_seg_size) ||
462 (ps->offset + ps->length) % PAGE_SIZE) {
463 if (dma_map_cont(dev, start_sg, i - start,
464 sgmap, pages, need) < 0)
468 sgmap = sg_next(sgmap);
475 seg_size += s->length;
477 pages += iommu_num_pages(s->offset, s->length);
480 if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
485 sgmap = sg_next(sgmap);
486 sgmap->dma_length = 0;
492 gart_unmap_sg(dev, sg, out, dir);
494 /* When it was forced or merged try again in a dumb way */
495 if (force_iommu || iommu_merge) {
496 out = dma_map_sg_nonforce(dev, sg, nents, dir);
500 if (panic_on_overflow)
501 panic("dma_map_sg: overflow on %lu pages\n", pages);
503 iommu_full(dev, pages << PAGE_SHIFT, dir);
504 for_each_sg(sg, s, nents, i)
505 s->dma_address = bad_dma_address;
511 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
516 iommu_size = aper_size;
521 a = aper + iommu_size;
522 iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
524 if (iommu_size < 64*1024*1024) {
526 "PCI-DMA: Warning: Small IOMMU %luMB."
527 " Consider increasing the AGP aperture in BIOS\n",
534 static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
536 unsigned aper_size = 0, aper_base_32, aper_order;
539 pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
540 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
541 aper_order = (aper_order >> 1) & 7;
543 aper_base = aper_base_32 & 0x7fff;
546 aper_size = (32 * 1024 * 1024) << aper_order;
547 if (aper_base + aper_size > 0x100000000UL || !aper_size)
554 static void enable_gart_translations(void)
558 for (i = 0; i < num_k8_northbridges; i++) {
559 struct pci_dev *dev = k8_northbridges[i];
561 enable_gart_translation(dev, __pa(agp_gatt_table));
566 * If fix_up_north_bridges is set, the north bridges have to be fixed up on
567 * resume in the same way as they are handled in gart_iommu_hole_init().
569 static bool fix_up_north_bridges;
570 static u32 aperture_order;
571 static u32 aperture_alloc;
573 void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
575 fix_up_north_bridges = true;
576 aperture_order = aper_order;
577 aperture_alloc = aper_alloc;
580 static int gart_resume(struct sys_device *dev)
582 printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n");
584 if (fix_up_north_bridges) {
587 printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n");
589 for (i = 0; i < num_k8_northbridges; i++) {
590 struct pci_dev *dev = k8_northbridges[i];
593 * Don't enable translations just yet. That is the next
594 * step. Restore the pre-suspend aperture settings.
596 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL,
597 aperture_order << 1);
598 pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE,
599 aperture_alloc >> 25);
603 enable_gart_translations();
608 static int gart_suspend(struct sys_device *dev, pm_message_t state)
613 static struct sysdev_class gart_sysdev_class = {
615 .suspend = gart_suspend,
616 .resume = gart_resume,
620 static struct sys_device device_gart = {
622 .cls = &gart_sysdev_class,
626 * Private Northbridge GATT initialization in case we cannot use the
627 * AGP driver for some reason.
629 static __init int init_k8_gatt(struct agp_kern_info *info)
631 unsigned aper_size, gatt_size, new_aper_size;
632 unsigned aper_base, new_aper_base;
637 printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
638 aper_size = aper_base = info->aper_size = 0;
640 for (i = 0; i < num_k8_northbridges; i++) {
641 dev = k8_northbridges[i];
642 new_aper_base = read_aperture(dev, &new_aper_size);
647 aper_size = new_aper_size;
648 aper_base = new_aper_base;
650 if (aper_size != new_aper_size || aper_base != new_aper_base)
655 info->aper_base = aper_base;
656 info->aper_size = aper_size >> 20;
658 gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
659 gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size));
661 panic("Cannot allocate GATT table");
662 if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
663 panic("Could not set GART PTEs to uncacheable pages");
665 memset(gatt, 0, gatt_size);
666 agp_gatt_table = gatt;
668 enable_gart_translations();
670 error = sysdev_class_register(&gart_sysdev_class);
672 error = sysdev_register(&device_gart);
674 panic("Could not register gart_sysdev -- would corrupt data on next suspend");
678 printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
679 aper_base, aper_size>>10);
684 /* Should not happen anymore */
685 printk(KERN_WARNING "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
686 KERN_WARNING "falling back to iommu=soft.\n");
690 extern int agp_amd64_init(void);
692 static struct dma_mapping_ops gart_dma_ops = {
693 .map_single = gart_map_single,
694 .map_simple = gart_map_simple,
695 .unmap_single = gart_unmap_single,
696 .sync_single_for_cpu = NULL,
697 .sync_single_for_device = NULL,
698 .sync_single_range_for_cpu = NULL,
699 .sync_single_range_for_device = NULL,
700 .sync_sg_for_cpu = NULL,
701 .sync_sg_for_device = NULL,
702 .map_sg = gart_map_sg,
703 .unmap_sg = gart_unmap_sg,
706 void gart_iommu_shutdown(void)
711 if (no_agp && (dma_ops != &gart_dma_ops))
714 for (i = 0; i < num_k8_northbridges; i++) {
717 dev = k8_northbridges[i];
718 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
722 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
726 void __init gart_iommu_init(void)
728 struct agp_kern_info info;
729 unsigned long iommu_start;
730 unsigned long aper_base, aper_size;
731 unsigned long start_pfn, end_pfn;
732 unsigned long scratch;
735 if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) {
736 printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n");
740 #ifndef CONFIG_AGP_AMD64
743 /* Makefile puts PCI initialization via subsys_initcall first. */
744 /* Add other K8 AGP bridge drivers here */
746 (agp_amd64_init() < 0) ||
747 (agp_copy_info(agp_bridge, &info) < 0);
753 /* Did we detect a different HW IOMMU? */
754 if (iommu_detected && !gart_iommu_aperture)
758 (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
759 !gart_iommu_aperture ||
760 (no_agp && init_k8_gatt(&info) < 0)) {
761 if (max_pfn > MAX_DMA32_PFN) {
762 printk(KERN_WARNING "More than 4GB of memory "
763 "but GART IOMMU not available.\n"
764 KERN_WARNING "falling back to iommu=soft.\n");
769 /* need to map that range */
770 aper_size = info.aper_size << 20;
771 aper_base = info.aper_base;
772 end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
773 if (end_pfn > max_low_pfn_mapped) {
774 start_pfn = (aper_base>>PAGE_SHIFT);
775 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
778 printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
779 iommu_size = check_iommu_size(info.aper_base, aper_size);
780 iommu_pages = iommu_size >> PAGE_SHIFT;
782 iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL,
783 get_order(iommu_pages/8));
784 if (!iommu_gart_bitmap)
785 panic("Cannot allocate iommu bitmap\n");
786 memset(iommu_gart_bitmap, 0, iommu_pages/8);
788 #ifdef CONFIG_IOMMU_LEAK
790 iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL,
791 get_order(iommu_pages*sizeof(void *)));
793 memset(iommu_leak_tab, 0, iommu_pages * 8);
796 "PCI-DMA: Cannot allocate leak trace area\n");
801 * Out of IOMMU space handling.
802 * Reserve some invalid pages at the beginning of the GART.
804 set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
806 agp_memory_reserved = iommu_size;
808 "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
811 iommu_start = aper_size - iommu_size;
812 iommu_bus_base = info.aper_base + iommu_start;
813 bad_dma_address = iommu_bus_base;
814 iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
817 * Unmap the IOMMU part of the GART. The alias of the page is
818 * always mapped with cache enabled and there is no full cache
819 * coherency across the GART remapping. The unmapping avoids
820 * automatic prefetches from the CPU allocating cache lines in
821 * there. All CPU accesses are done via the direct mapping to
822 * the backing memory. The GART address is only used by PCI
825 set_memory_np((unsigned long)__va(iommu_bus_base),
826 iommu_size >> PAGE_SHIFT);
828 * Tricky. The GART table remaps the physical memory range,
829 * so the CPU wont notice potential aliases and if the memory
830 * is remapped to UC later on, we might surprise the PCI devices
831 * with a stray writeout of a cacheline. So play it sure and
832 * do an explicit, full-scale wbinvd() _after_ having marked all
833 * the pages as Not-Present:
838 * Try to workaround a bug (thanks to BenH):
839 * Set unmapped entries to a scratch page instead of 0.
840 * Any prefetches that hit unmapped entries won't get an bus abort
841 * then. (P2P bridge may be prefetching on DMA reads).
843 scratch = get_zeroed_page(GFP_KERNEL);
845 panic("Cannot allocate iommu scratch page");
846 gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
847 for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
848 iommu_gatt_base[i] = gart_unmapped_entry;
851 dma_ops = &gart_dma_ops;
854 void __init gart_parse_options(char *p)
858 #ifdef CONFIG_IOMMU_LEAK
859 if (!strncmp(p, "leak", 4)) {
863 if (isdigit(*p) && get_option(&p, &arg))
864 iommu_leak_pages = arg;
867 if (isdigit(*p) && get_option(&p, &arg))
869 if (!strncmp(p, "fullflush", 8))
871 if (!strncmp(p, "nofullflush", 11))
873 if (!strncmp(p, "noagp", 5))
875 if (!strncmp(p, "noaperture", 10))
877 /* duplicated from pci-dma.c */
878 if (!strncmp(p, "force", 5))
879 gart_iommu_aperture_allowed = 1;
880 if (!strncmp(p, "allowed", 7))
881 gart_iommu_aperture_allowed = 1;
882 if (!strncmp(p, "memaper", 7)) {
883 fallback_aper_force = 1;
887 if (get_option(&p, &arg))
888 fallback_aper_order = arg;