1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/slab.h>
6 #include <linux/sched.h>
7 #include <linux/module.h>
9 #include <linux/clockchips.h>
10 #include <asm/system.h>
12 unsigned long idle_halt;
13 EXPORT_SYMBOL(idle_halt);
14 unsigned long idle_nomwait;
15 EXPORT_SYMBOL(idle_nomwait);
17 struct kmem_cache *task_xstate_cachep;
19 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
22 if (src->thread.xstate) {
23 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
25 if (!dst->thread.xstate)
27 WARN_ON((unsigned long)dst->thread.xstate & 15);
28 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
33 void free_thread_xstate(struct task_struct *tsk)
35 if (tsk->thread.xstate) {
36 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
37 tsk->thread.xstate = NULL;
41 void free_thread_info(struct thread_info *ti)
43 free_thread_xstate(ti->task);
44 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
47 void arch_task_cache_init(void)
50 kmem_cache_create("task_xstate", xstate_size,
51 __alignof__(union thread_xstate),
56 * Idle related variables and functions
58 unsigned long boot_option_idle_override = 0;
59 EXPORT_SYMBOL(boot_option_idle_override);
62 * Powermanagement idle function, if any..
64 void (*pm_idle)(void);
65 EXPORT_SYMBOL(pm_idle);
69 * This halt magic was a workaround for ancient floppy DMA
70 * wreckage. It should be safe to remove.
72 static int hlt_counter;
73 void disable_hlt(void)
77 EXPORT_SYMBOL(disable_hlt);
83 EXPORT_SYMBOL(enable_hlt);
85 static inline int hlt_use_halt(void)
87 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
90 static inline int hlt_use_halt(void)
97 * We use this if we don't have any better
100 void default_idle(void)
102 if (hlt_use_halt()) {
103 current_thread_info()->status &= ~TS_POLLING;
105 * TS_POLLING-cleared state must be visible before we
111 safe_halt(); /* enables interrupts racelessly */
114 current_thread_info()->status |= TS_POLLING;
117 /* loop is done by the caller */
121 #ifdef CONFIG_APM_MODULE
122 EXPORT_SYMBOL(default_idle);
125 static void do_nothing(void *unused)
130 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
131 * pm_idle and update to new pm_idle value. Required while changing pm_idle
132 * handler on SMP systems.
134 * Caller must have changed pm_idle to the new value before the call. Old
135 * pm_idle value will not be used by any CPU after the return of this function.
137 void cpu_idle_wait(void)
140 /* kick all the CPUs so that they exit out of pm_idle */
141 smp_call_function(do_nothing, NULL, 1);
143 EXPORT_SYMBOL_GPL(cpu_idle_wait);
146 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
147 * which can obviate IPI to trigger checking of need_resched.
148 * We execute MONITOR against need_resched and enter optimized wait state
149 * through MWAIT. Whenever someone changes need_resched, we would be woken
150 * up from MWAIT (without an IPI).
152 * New with Core Duo processors, MWAIT can take some hints based on CPU
155 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
157 if (!need_resched()) {
158 __monitor((void *)¤t_thread_info()->flags, 0, 0);
165 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
166 static void mwait_idle(void)
168 if (!need_resched()) {
169 __monitor((void *)¤t_thread_info()->flags, 0, 0);
180 * On SMP it's slightly faster (but much more power-consuming!)
181 * to poll the ->work.need_resched flag instead of waiting for the
182 * cross-CPU IPI to arrive. Use this option with caution.
184 static void poll_idle(void)
191 * mwait selection logic:
193 * It depends on the CPU. For AMD CPUs that support MWAIT this is
194 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
195 * then depend on a clock divisor and current Pstate of the core. If
196 * all cores of a processor are in halt state (C1) the processor can
197 * enter the C1E (C1 enhanced) state. If mwait is used this will never
200 * idle=mwait overrides this decision and forces the usage of mwait.
202 static int __cpuinitdata force_mwait;
204 #define MWAIT_INFO 0x05
205 #define MWAIT_ECX_EXTENDED_INFO 0x01
206 #define MWAIT_EDX_C1 0xf0
208 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
210 u32 eax, ebx, ecx, edx;
215 if (c->cpuid_level < MWAIT_INFO)
218 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
219 /* Check, whether EDX has extended info about MWAIT */
220 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
224 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
227 return (edx & MWAIT_EDX_C1);
231 * Check for AMD CPUs, which have potentially C1E support
233 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
235 if (c->x86_vendor != X86_VENDOR_AMD)
241 /* Family 0x0f models < rev F do not have C1E */
242 if (c->x86 == 0x0f && c->x86_model < 0x40)
249 * C1E aware idle routine. We check for C1E active in the interrupt
250 * pending message MSR. If we detect C1E, then we handle it the same
251 * way as C3 power states (local apic timer and TSC stop)
253 static void c1e_idle(void)
255 static cpumask_t c1e_mask = CPU_MASK_NONE;
256 static int c1e_detected;
264 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
265 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
267 mark_tsc_unstable("TSC halt in C1E");
268 printk(KERN_INFO "System has C1E enabled\n");
273 int cpu = smp_processor_id();
275 if (!cpu_isset(cpu, c1e_mask)) {
276 cpu_set(cpu, c1e_mask);
278 * Force broadcast so ACPI can not interfere. Needs
279 * to run with interrupts enabled as it uses
283 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
285 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
289 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
294 * The switch back from broadcast mode needs to be
295 * called with interrupts disabled.
298 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
304 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
306 #ifdef CONFIG_X86_SMP
307 if (pm_idle == poll_idle && smp_num_siblings > 1) {
308 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
309 " performance may degrade.\n");
315 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
317 * One CPU supports mwait => All CPUs supports mwait
319 printk(KERN_INFO "using mwait in idle threads.\n");
320 pm_idle = mwait_idle;
321 } else if (check_c1e_idle(c)) {
322 printk(KERN_INFO "using C1E aware idle routine\n");
325 pm_idle = default_idle;
328 static int __init idle_setup(char *str)
333 if (!strcmp(str, "poll")) {
334 printk("using polling idle threads.\n");
336 } else if (!strcmp(str, "mwait"))
338 else if (!strcmp(str, "halt")) {
340 * When the boot option of idle=halt is added, halt is
341 * forced to be used for CPU idle. In such case CPU C2/C3
342 * won't be used again.
343 * To continue to load the CPU idle driver, don't touch
344 * the boot_option_idle_override.
346 pm_idle = default_idle;
349 } else if (!strcmp(str, "nomwait")) {
351 * If the boot option of "idle=nomwait" is added,
352 * it means that mwait will be disabled for CPU C2/C3
353 * states. In such case it won't touch the variable
354 * of boot_option_idle_override.
361 boot_option_idle_override = 1;
364 early_param("idle", idle_setup);