2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/module.h>
45 #include <linux/sched.h>
46 #include <linux/percpu.h>
47 #include <linux/bootmem.h>
48 #include <linux/err.h>
49 #include <linux/nmi.h>
58 #include <asm/pgtable.h>
59 #include <asm/tlbflush.h>
63 #include <linux/mc146818rtc.h>
65 #include <mach_apic.h>
66 #include <mach_wakecpu.h>
67 #include <smpboot_hooks.h>
70 * FIXME: For x86_64, those are defined in other files. But moving them here,
71 * would make the setup areas dependent on smp, which is a loss. When we
72 * integrate apic between arches, we can probably do a better job, but
73 * right now, they'll stay here -- glommer
76 /* which logical CPU number maps to which CPU (physical APIC ID) */
77 u16 x86_cpu_to_apicid_init[NR_CPUS] __initdata =
78 { [0 ... NR_CPUS-1] = BAD_APICID };
79 void *x86_cpu_to_apicid_early_ptr;
80 DEFINE_PER_CPU(u16, x86_cpu_to_apicid) = BAD_APICID;
81 EXPORT_PER_CPU_SYMBOL(x86_cpu_to_apicid);
83 u16 x86_bios_cpu_apicid_init[NR_CPUS] __initdata
84 = { [0 ... NR_CPUS-1] = BAD_APICID };
85 void *x86_bios_cpu_apicid_early_ptr;
87 /* Internal processor count */
88 unsigned int num_processors;
89 unsigned disabled_cpus __cpuinitdata;
91 u8 apicid_2_node[MAX_APICID];
94 /* Bitmask of physically existing CPUs */
95 physid_mask_t phys_cpu_present_map;
97 /* State of each CPU */
98 DEFINE_PER_CPU(int, cpu_state) = { 0 };
100 /* Store all idle threads, this can be reused instead of creating
101 * a new thread. Also avoids complicated thread destroy functionality
104 #ifdef CONFIG_HOTPLUG_CPU
106 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
107 * removed after init for !CONFIG_HOTPLUG_CPU.
109 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
110 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
111 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
113 struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
114 #define get_idle_for_cpu(x) (idle_thread_array[(x)])
115 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
118 /* Number of siblings per CPU package */
119 int smp_num_siblings = 1;
120 EXPORT_SYMBOL(smp_num_siblings);
122 /* Last level cache ID of each logical CPU */
123 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
125 /* bitmap of online cpus */
126 cpumask_t cpu_online_map __read_mostly;
127 EXPORT_SYMBOL(cpu_online_map);
129 cpumask_t cpu_callin_map;
130 cpumask_t cpu_callout_map;
131 cpumask_t cpu_possible_map;
132 EXPORT_SYMBOL(cpu_possible_map);
134 /* representing HT siblings of each logical CPU */
135 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map);
136 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
138 /* representing HT and core siblings of each logical CPU */
139 DEFINE_PER_CPU(cpumask_t, cpu_core_map);
140 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
142 /* Per CPU bogomips and other parameters */
143 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
144 EXPORT_PER_CPU_SYMBOL(cpu_info);
146 static atomic_t init_deasserted;
148 static int boot_cpu_logical_apicid;
150 /* ready for x86_64, no harm for x86, since it will overwrite after alloc */
151 unsigned char *trampoline_base = __va(SMP_TRAMPOLINE_BASE);
153 /* representing cpus for which sibling maps can be computed */
154 static cpumask_t cpu_sibling_setup_map;
156 /* Set if we find a B stepping CPU */
157 int __cpuinitdata smp_b_stepping;
159 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32)
161 /* which logical CPUs are on which nodes */
162 cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly =
163 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
164 EXPORT_SYMBOL(node_to_cpumask_map);
165 /* which node each logical CPU is on */
166 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
167 EXPORT_SYMBOL(cpu_to_node_map);
169 /* set up a mapping between cpu and node. */
170 static void map_cpu_to_node(int cpu, int node)
172 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node);
173 cpu_set(cpu, node_to_cpumask_map[node]);
174 cpu_to_node_map[cpu] = node;
177 /* undo a mapping between cpu and node. */
178 static void unmap_cpu_to_node(int cpu)
182 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu);
183 for (node = 0; node < MAX_NUMNODES; node++)
184 cpu_clear(cpu, node_to_cpumask_map[node]);
185 cpu_to_node_map[cpu] = 0;
187 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */
188 #define map_cpu_to_node(cpu, node) ({})
189 #define unmap_cpu_to_node(cpu) ({})
193 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
194 { [0 ... NR_CPUS-1] = BAD_APICID };
196 void map_cpu_to_logical_apicid(void)
198 int cpu = smp_processor_id();
199 int apicid = logical_smp_processor_id();
200 int node = apicid_to_node(apicid);
202 if (!node_online(node))
203 node = first_online_node;
205 cpu_2_logical_apicid[cpu] = apicid;
206 map_cpu_to_node(cpu, node);
209 void unmap_cpu_to_logical_apicid(int cpu)
211 cpu_2_logical_apicid[cpu] = BAD_APICID;
212 unmap_cpu_to_node(cpu);
215 #define unmap_cpu_to_logical_apicid(cpu) do {} while (0)
216 #define map_cpu_to_logical_apicid() do {} while (0)
220 * Report back to the Boot Processor.
223 void __cpuinit smp_callin(void)
226 unsigned long timeout;
229 * If waken up by an INIT in an 82489DX configuration
230 * we may get here before an INIT-deassert IPI reaches
231 * our local APIC. We have to wait for the IPI or we'll
232 * lock up on an APIC access.
234 wait_for_init_deassert(&init_deasserted);
237 * (This works even if the APIC is not enabled.)
239 phys_id = GET_APIC_ID(apic_read(APIC_ID));
240 cpuid = smp_processor_id();
241 if (cpu_isset(cpuid, cpu_callin_map)) {
242 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
245 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
248 * STARTUP IPIs are fragile beasts as they might sometimes
249 * trigger some glue motherboard logic. Complete APIC bus
250 * silence for 1 second, this overestimates the time the
251 * boot CPU is spending to send the up to 2 STARTUP IPIs
252 * by a factor of two. This should be enough.
256 * Waiting 2s total for startup (udelay is not yet working)
258 timeout = jiffies + 2*HZ;
259 while (time_before(jiffies, timeout)) {
261 * Has the boot CPU finished it's STARTUP sequence?
263 if (cpu_isset(cpuid, cpu_callout_map))
268 if (!time_before(jiffies, timeout)) {
269 panic("%s: CPU%d started up but did not get a callout!\n",
274 * the boot CPU has finished the init stage and is spinning
275 * on callin_map until we finish. We are free to set up this
276 * CPU, first the APIC. (this is probably redundant on most
280 Dprintk("CALLIN, before setup_local_APIC().\n");
281 smp_callin_clear_local_apic();
283 end_local_APIC_setup();
284 map_cpu_to_logical_apicid();
289 * Need to enable IRQs because it can take longer and then
290 * the NMI watchdog might kill us.
295 Dprintk("Stack at about %p\n", &cpuid);
298 * Save our processor parameters
300 smp_store_cpu_info(cpuid);
303 * Allow the master to continue.
305 cpu_set(cpuid, cpu_callin_map);
309 * Activate a secondary processor.
311 void __cpuinit start_secondary(void *unused)
314 * Don't put *anything* before cpu_init(), SMP booting is too
315 * fragile that we want to limit the things done here to the
316 * most necessary things.
325 /* otherwise gcc will move up smp_processor_id before the cpu_init */
328 * Check TSC synchronization with the BP:
330 check_tsc_sync_target();
332 if (nmi_watchdog == NMI_IO_APIC) {
333 disable_8259A_irq(0);
334 enable_NMI_through_LVT0();
338 /* This must be done before setting cpu_online_map */
339 set_cpu_sibling_map(raw_smp_processor_id());
343 * We need to hold call_lock, so there is no inconsistency
344 * between the time smp_call_function() determines number of
345 * IPI recipients, and the time when the determination is made
346 * for which cpus receive the IPI. Holding this
347 * lock helps us to not include this cpu in a currently in progress
348 * smp_call_function().
350 lock_ipi_call_lock();
352 spin_lock(&vector_lock);
354 /* Setup the per cpu irq handling data structures */
355 __setup_vector_irq(smp_processor_id());
357 * Allow the master to continue.
359 spin_unlock(&vector_lock);
361 cpu_set(smp_processor_id(), cpu_online_map);
362 unlock_ipi_call_lock();
363 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
365 setup_secondary_clock();
373 * Everything has been set up for the secondary
374 * CPUs - they just need to reload everything
375 * from the task structure
376 * This function must not return.
378 void __devinit initialize_secondary(void)
381 * We don't actually need to load the full TSS,
382 * basically just the stack pointer and the ip.
389 :"m" (current->thread.sp), "m" (current->thread.ip));
393 static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c)
397 * Mask B, Pentium, but not Pentium MMX
399 if (c->x86_vendor == X86_VENDOR_INTEL &&
401 c->x86_mask >= 1 && c->x86_mask <= 4 &&
404 * Remember we have B step Pentia with bugs
409 * Certain Athlons might work (for various values of 'work') in SMP
410 * but they are not certified as MP capable.
412 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
414 if (num_possible_cpus() == 1)
417 /* Athlon 660/661 is valid. */
418 if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
422 /* Duron 670 is valid */
423 if ((c->x86_model == 7) && (c->x86_mask == 0))
427 * Athlon 662, Duron 671, and Athlon >model 7 have capability
428 * bit. It's worth noting that the A5 stepping (662) of some
429 * Athlon XP's have the MP bit set.
430 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
433 if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
434 ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
439 /* If we get here, not a certified SMP capable AMD system. */
440 add_taint(TAINT_UNSAFE_SMP);
448 void smp_checks(void)
451 printk(KERN_WARNING "WARNING: SMP operation may be unreliable"
452 "with B stepping processors.\n");
455 * Don't taint if we are running SMP kernel on a single non-MP
458 if (tainted & TAINT_UNSAFE_SMP) {
459 if (num_online_cpus())
460 printk(KERN_INFO "WARNING: This combination of AMD"
461 "processors is not suitable for SMP.\n");
463 tainted &= ~TAINT_UNSAFE_SMP;
468 * The bootstrap kernel entry code has set these up. Save them for
472 void __cpuinit smp_store_cpu_info(int id)
474 struct cpuinfo_x86 *c = &cpu_data(id);
479 identify_secondary_cpu(c);
484 void __cpuinit set_cpu_sibling_map(int cpu)
487 struct cpuinfo_x86 *c = &cpu_data(cpu);
489 cpu_set(cpu, cpu_sibling_setup_map);
491 if (smp_num_siblings > 1) {
492 for_each_cpu_mask(i, cpu_sibling_setup_map) {
493 if (c->phys_proc_id == cpu_data(i).phys_proc_id &&
494 c->cpu_core_id == cpu_data(i).cpu_core_id) {
495 cpu_set(i, per_cpu(cpu_sibling_map, cpu));
496 cpu_set(cpu, per_cpu(cpu_sibling_map, i));
497 cpu_set(i, per_cpu(cpu_core_map, cpu));
498 cpu_set(cpu, per_cpu(cpu_core_map, i));
499 cpu_set(i, c->llc_shared_map);
500 cpu_set(cpu, cpu_data(i).llc_shared_map);
504 cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
507 cpu_set(cpu, c->llc_shared_map);
509 if (current_cpu_data.x86_max_cores == 1) {
510 per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu);
515 for_each_cpu_mask(i, cpu_sibling_setup_map) {
516 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
517 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
518 cpu_set(i, c->llc_shared_map);
519 cpu_set(cpu, cpu_data(i).llc_shared_map);
521 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
522 cpu_set(i, per_cpu(cpu_core_map, cpu));
523 cpu_set(cpu, per_cpu(cpu_core_map, i));
525 * Does this new cpu bringup a new core?
527 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) {
529 * for each core in package, increment
530 * the booted_cores for this new cpu
532 if (first_cpu(per_cpu(cpu_sibling_map, i)) == i)
535 * increment the core count for all
536 * the other cpus in this package
539 cpu_data(i).booted_cores++;
540 } else if (i != cpu && !c->booted_cores)
541 c->booted_cores = cpu_data(i).booted_cores;
546 /* maps the cpu to the sched domain representing multi-core */
547 cpumask_t cpu_coregroup_map(int cpu)
549 struct cpuinfo_x86 *c = &cpu_data(cpu);
551 * For perf, we return last level cache shared map.
552 * And for power savings, we return cpu_core_map
554 if (sched_mc_power_savings || sched_smt_power_savings)
555 return per_cpu(cpu_core_map, cpu);
557 return c->llc_shared_map;
561 * Currently trivial. Write the real->protected mode
562 * bootstrap into the page concerned. The caller
563 * has made sure it's suitably aligned.
566 unsigned long __cpuinit setup_trampoline(void)
568 memcpy(trampoline_base, trampoline_data,
569 trampoline_end - trampoline_data);
570 return virt_to_phys(trampoline_base);
575 * We are called very early to get the low memory for the
576 * SMP bootup trampoline page.
578 void __init smp_alloc_memory(void)
580 trampoline_base = alloc_bootmem_low_pages(PAGE_SIZE);
582 * Has to be in very low memory so we can execute
585 if (__pa(trampoline_base) >= 0x9F000)
590 void impress_friends(void)
593 unsigned long bogosum = 0;
595 * Allow the user to impress friends.
597 Dprintk("Before bogomips.\n");
598 for_each_possible_cpu(cpu)
599 if (cpu_isset(cpu, cpu_callout_map))
600 bogosum += cpu_data(cpu).loops_per_jiffy;
602 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
605 (bogosum/(5000/HZ))%100);
607 Dprintk("Before bogocount - setting activated=1.\n");
610 static inline void __inquire_remote_apic(int apicid)
612 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
613 char *names[] = { "ID", "VERSION", "SPIV" };
617 printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
619 for (i = 0; i < ARRAY_SIZE(regs); i++) {
620 printk(KERN_INFO "... APIC #%d %s: ", apicid, names[i]);
625 status = safe_apic_wait_icr_idle();
628 "a previous APIC delivery may have failed\n");
630 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
631 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
636 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
637 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
640 case APIC_ICR_RR_VALID:
641 status = apic_read(APIC_RRR);
642 printk(KERN_CONT "%08x\n", status);
645 printk(KERN_CONT "failed\n");
650 #ifdef WAKE_SECONDARY_VIA_NMI
652 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
653 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
654 * won't ... remember to clear down the APIC, etc later.
657 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
659 unsigned long send_status, accept_status = 0;
663 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
665 /* Boot on the stack */
666 /* Kick the second */
667 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
669 Dprintk("Waiting for send to finish...\n");
670 send_status = safe_apic_wait_icr_idle();
673 * Give the other CPU some time to accept the IPI.
677 * Due to the Pentium erratum 3AP.
679 maxlvt = lapic_get_maxlvt();
681 apic_read_around(APIC_SPIV);
682 apic_write(APIC_ESR, 0);
684 accept_status = (apic_read(APIC_ESR) & 0xEF);
685 Dprintk("NMI sent.\n");
688 printk(KERN_ERR "APIC never delivered???\n");
690 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
692 return (send_status | accept_status);
694 #endif /* WAKE_SECONDARY_VIA_NMI */
696 #ifdef WAKE_SECONDARY_VIA_INIT
698 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
700 unsigned long send_status, accept_status = 0;
701 int maxlvt, num_starts, j;
704 * Be paranoid about clearing APIC errors.
706 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
707 apic_read_around(APIC_SPIV);
708 apic_write(APIC_ESR, 0);
712 Dprintk("Asserting INIT.\n");
715 * Turn INIT on target chip
717 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
722 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
725 Dprintk("Waiting for send to finish...\n");
726 send_status = safe_apic_wait_icr_idle();
730 Dprintk("Deasserting INIT.\n");
733 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
736 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
738 Dprintk("Waiting for send to finish...\n");
739 send_status = safe_apic_wait_icr_idle();
742 atomic_set(&init_deasserted, 1);
745 * Should we send STARTUP IPIs ?
747 * Determine this based on the APIC version.
748 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
750 if (APIC_INTEGRATED(apic_version[phys_apicid]))
756 * Paravirt / VMI wants a startup IPI hook here to set up the
757 * target processor state.
759 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
761 (unsigned long)init_rsp);
763 (unsigned long)stack_start.sp);
767 * Run STARTUP IPI loop.
769 Dprintk("#startup loops: %d.\n", num_starts);
771 maxlvt = lapic_get_maxlvt();
773 for (j = 1; j <= num_starts; j++) {
774 Dprintk("Sending STARTUP #%d.\n", j);
775 apic_read_around(APIC_SPIV);
776 apic_write(APIC_ESR, 0);
778 Dprintk("After apic_write.\n");
785 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
787 /* Boot on the stack */
788 /* Kick the second */
789 apic_write_around(APIC_ICR, APIC_DM_STARTUP
790 | (start_eip >> 12));
793 * Give the other CPU some time to accept the IPI.
797 Dprintk("Startup point 1.\n");
799 Dprintk("Waiting for send to finish...\n");
800 send_status = safe_apic_wait_icr_idle();
803 * Give the other CPU some time to accept the IPI.
807 * Due to the Pentium erratum 3AP.
810 apic_read_around(APIC_SPIV);
811 apic_write(APIC_ESR, 0);
813 accept_status = (apic_read(APIC_ESR) & 0xEF);
814 if (send_status || accept_status)
817 Dprintk("After Startup.\n");
820 printk(KERN_ERR "APIC never delivered???\n");
822 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
824 return (send_status | accept_status);
826 #endif /* WAKE_SECONDARY_VIA_INIT */
829 struct work_struct work;
830 struct task_struct *idle;
831 struct completion done;
835 static void __cpuinit do_fork_idle(struct work_struct *work)
837 struct create_idle *c_idle =
838 container_of(work, struct create_idle, work);
840 c_idle->idle = fork_idle(c_idle->cpu);
841 complete(&c_idle->done);
844 static int __cpuinit do_boot_cpu(int apicid, int cpu)
846 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
847 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
848 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
851 unsigned long boot_error = 0;
853 unsigned long start_ip;
854 unsigned short nmi_high = 0, nmi_low = 0;
855 struct create_idle c_idle = {
857 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
859 INIT_WORK(&c_idle.work, do_fork_idle);
861 /* allocate memory for gdts of secondary cpus. Hotplug is considered */
862 if (!cpu_gdt_descr[cpu].address &&
863 !(cpu_gdt_descr[cpu].address = get_zeroed_page(GFP_KERNEL))) {
864 printk(KERN_ERR "Failed to allocate GDT for CPU %d\n", cpu);
868 /* Allocate node local memory for AP pdas */
869 if (cpu_pda(cpu) == &boot_cpu_pda[cpu]) {
870 struct x8664_pda *newpda, *pda;
871 int node = cpu_to_node(cpu);
873 newpda = kmalloc_node(sizeof(struct x8664_pda), GFP_ATOMIC,
876 memcpy(newpda, pda, sizeof(struct x8664_pda));
877 cpu_pda(cpu) = newpda;
880 "Could not allocate node local PDA for CPU %d on node %d\n",
885 alternatives_smp_switch(1);
887 c_idle.idle = get_idle_for_cpu(cpu);
890 * We can't use kernel_thread since we must avoid to
891 * reschedule the child.
894 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
895 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
896 init_idle(c_idle.idle, cpu);
900 if (!keventd_up() || current_is_keventd())
901 c_idle.work.func(&c_idle.work);
903 schedule_work(&c_idle.work);
904 wait_for_completion(&c_idle.done);
907 if (IS_ERR(c_idle.idle)) {
908 printk("failed fork for CPU %d\n", cpu);
909 return PTR_ERR(c_idle.idle);
912 set_idle_for_cpu(cpu, c_idle.idle);
915 per_cpu(current_task, cpu) = c_idle.idle;
917 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
918 c_idle.idle->thread.ip = (unsigned long) start_secondary;
919 /* Stack for startup_32 can be just as for start_secondary onwards */
920 stack_start.sp = (void *) c_idle.idle->thread.sp;
923 cpu_pda(cpu)->pcurrent = c_idle.idle;
924 init_rsp = c_idle.idle->thread.sp;
925 load_sp0(&per_cpu(init_tss, cpu), &c_idle.idle->thread);
926 initial_code = (unsigned long)start_secondary;
927 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
930 /* start_ip had better be page-aligned! */
931 start_ip = setup_trampoline();
933 /* So we see what's up */
934 printk(KERN_INFO "Booting processor %d/%d ip %lx\n",
935 cpu, apicid, start_ip);
938 * This grunge runs the startup process for
939 * the targeted processor.
942 atomic_set(&init_deasserted, 0);
944 Dprintk("Setting warm reset code and vector.\n");
946 store_NMI_vector(&nmi_high, &nmi_low);
948 smpboot_setup_warm_reset_vector(start_ip);
950 * Be paranoid about clearing APIC errors.
952 apic_write(APIC_ESR, 0);
956 * Starting actual IPI sequence...
958 boot_error = wakeup_secondary_cpu(apicid, start_ip);
962 * allow APs to start initializing.
964 Dprintk("Before Callout %d.\n", cpu);
965 cpu_set(cpu, cpu_callout_map);
966 Dprintk("After Callout %d.\n", cpu);
969 * Wait 5s total for a response
971 for (timeout = 0; timeout < 50000; timeout++) {
972 if (cpu_isset(cpu, cpu_callin_map))
973 break; /* It has booted */
977 if (cpu_isset(cpu, cpu_callin_map)) {
978 /* number CPUs logically, starting from 1 (BSP is 0) */
980 printk(KERN_INFO "CPU%d: ", cpu);
981 print_cpu_info(&cpu_data(cpu));
982 Dprintk("CPU has booted.\n");
985 if (*((volatile unsigned char *)trampoline_base)
987 /* trampoline started but...? */
988 printk(KERN_ERR "Stuck ??\n");
990 /* trampoline code not run */
991 printk(KERN_ERR "Not responding.\n");
992 inquire_remote_apic(apicid);
997 /* Try to put things back the way they were before ... */
998 unmap_cpu_to_logical_apicid(cpu);
1000 clear_node_cpumask(cpu); /* was set by numa_add_cpu */
1002 cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */
1003 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
1004 cpu_clear(cpu, cpu_possible_map);
1005 cpu_clear(cpu, cpu_present_map);
1006 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
1009 /* mark "stuck" area as not stuck */
1010 *((volatile unsigned long *)trampoline_base) = 0;
1015 int __cpuinit native_cpu_up(unsigned int cpu)
1017 int apicid = cpu_present_to_apicid(cpu);
1018 unsigned long flags;
1021 WARN_ON(irqs_disabled());
1023 Dprintk("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1025 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
1026 !physid_isset(apicid, phys_cpu_present_map)) {
1027 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
1032 * Already booted CPU?
1034 if (cpu_isset(cpu, cpu_callin_map)) {
1035 Dprintk("do_boot_cpu %d Already started\n", cpu);
1040 * Save current MTRR state in case it was changed since early boot
1041 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1045 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1047 #ifdef CONFIG_X86_32
1048 /* init low mem mapping */
1049 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + USER_PGD_PTRS,
1050 min_t(unsigned long, KERNEL_PGD_PTRS, USER_PGD_PTRS));
1054 err = do_boot_cpu(apicid, cpu);
1056 Dprintk("do_boot_cpu failed %d\n", err);
1061 * Check TSC synchronization with the AP (keep irqs disabled
1064 local_irq_save(flags);
1065 check_tsc_sync_source(cpu);
1066 local_irq_restore(flags);
1068 while (!cpu_isset(cpu, cpu_online_map)) {
1070 touch_nmi_watchdog();
1077 * Fall back to non SMP mode after errors.
1079 * RED-PEN audit/test this more. I bet there is more state messed up here.
1081 static __init void disable_smp(void)
1083 cpu_present_map = cpumask_of_cpu(0);
1084 cpu_possible_map = cpumask_of_cpu(0);
1085 #ifdef CONFIG_X86_32
1086 smpboot_clear_io_apic_irqs();
1088 if (smp_found_config)
1089 phys_cpu_present_map =
1090 physid_mask_of_physid(boot_cpu_physical_apicid);
1092 phys_cpu_present_map = physid_mask_of_physid(0);
1093 map_cpu_to_logical_apicid();
1094 cpu_set(0, per_cpu(cpu_sibling_map, 0));
1095 cpu_set(0, per_cpu(cpu_core_map, 0));
1099 * Various sanity checks.
1101 static int __init smp_sanity_check(unsigned max_cpus)
1103 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1104 printk(KERN_WARNING "weird, boot CPU (#%d) not listed"
1105 "by the BIOS.\n", hard_smp_processor_id());
1106 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1110 * If we couldn't find an SMP configuration at boot time,
1111 * get out of here now!
1113 if (!smp_found_config && !acpi_lapic) {
1114 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1116 if (APIC_init_uniprocessor())
1117 printk(KERN_NOTICE "Local APIC not detected."
1118 " Using dummy APIC emulation.\n");
1123 * Should not be necessary because the MP table should list the boot
1124 * CPU too, but we do it for the sake of robustness anyway.
1126 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1128 "weird, boot CPU (#%d) not listed by the BIOS.\n",
1129 boot_cpu_physical_apicid);
1130 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1134 * If we couldn't find a local APIC, then get out of here now!
1136 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1138 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1139 boot_cpu_physical_apicid);
1140 printk(KERN_ERR "... forcing use of dummy APIC emulation."
1141 "(tell your hw vendor)\n");
1142 smpboot_clear_io_apic();
1146 verify_local_APIC();
1149 * If SMP should be disabled, then really disable it!
1152 printk(KERN_INFO "SMP mode deactivated,"
1153 "forcing use of dummy APIC emulation.\n");
1154 smpboot_clear_io_apic();
1155 #ifdef CONFIG_X86_32
1156 if (nmi_watchdog == NMI_LOCAL_APIC) {
1157 printk(KERN_INFO "activating minimal APIC for"
1158 "NMI watchdog use.\n");
1161 end_local_APIC_setup();
1170 static void __init smp_cpu_index_default(void)
1173 struct cpuinfo_x86 *c;
1175 for_each_cpu_mask(i, cpu_possible_map) {
1177 /* mark all to hotplug */
1178 c->cpu_index = NR_CPUS;
1183 * Prepare for SMP bootup. The MP table or ACPI has been read
1184 * earlier. Just do some sanity checking here and enable APIC mode.
1186 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1188 nmi_watchdog_default();
1189 smp_cpu_index_default();
1190 current_cpu_data = boot_cpu_data;
1191 cpu_callin_map = cpumask_of_cpu(0);
1194 * Setup boot CPU information
1196 smp_store_cpu_info(0); /* Final full version of the data */
1197 boot_cpu_logical_apicid = logical_smp_processor_id();
1198 current_thread_info()->cpu = 0; /* needed? */
1199 set_cpu_sibling_map(0);
1201 if (smp_sanity_check(max_cpus) < 0) {
1202 printk(KERN_INFO "SMP disabled\n");
1207 if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_physical_apicid) {
1208 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1209 GET_APIC_ID(apic_read(APIC_ID)), boot_cpu_physical_apicid);
1210 /* Or can we switch back to PIC here? */
1213 #ifdef CONFIG_X86_32
1217 * Switch from PIC to APIC mode.
1221 #ifdef CONFIG_X86_64
1223 * Enable IO APIC before setting up error vector
1225 if (!skip_ioapic_setup && nr_ioapics)
1228 end_local_APIC_setup();
1230 map_cpu_to_logical_apicid();
1232 setup_portio_remap();
1234 smpboot_setup_io_apic();
1236 * Set up local APIC timer on boot CPU.
1239 printk(KERN_INFO "CPU%d: ", 0);
1240 print_cpu_info(&cpu_data(0));
1244 * Early setup to make printk work.
1246 void __init native_smp_prepare_boot_cpu(void)
1248 int me = smp_processor_id();
1249 #ifdef CONFIG_X86_32
1251 switch_to_new_gdt();
1253 /* already set me in cpu_online_map in boot_cpu_init() */
1254 cpu_set(me, cpu_callout_map);
1255 per_cpu(cpu_state, me) = CPU_ONLINE;
1258 void __init native_smp_cpus_done(unsigned int max_cpus)
1261 * Cleanup possible dangling ends...
1263 smpboot_restore_warm_reset_vector();
1265 Dprintk("Boot done.\n");
1269 #ifdef CONFIG_X86_IO_APIC
1270 setup_ioapic_dest();
1272 check_nmi_watchdog();
1273 #ifdef CONFIG_X86_32
1278 #ifdef CONFIG_HOTPLUG_CPU
1280 # ifdef CONFIG_X86_32
1281 void cpu_exit_clear(void)
1283 int cpu = raw_smp_processor_id();
1290 cpu_clear(cpu, cpu_callout_map);
1291 cpu_clear(cpu, cpu_callin_map);
1293 unmap_cpu_to_logical_apicid(cpu);
1295 # endif /* CONFIG_X86_32 */
1297 void remove_siblinginfo(int cpu)
1300 struct cpuinfo_x86 *c = &cpu_data(cpu);
1302 for_each_cpu_mask(sibling, per_cpu(cpu_core_map, cpu)) {
1303 cpu_clear(cpu, per_cpu(cpu_core_map, sibling));
1305 * last thread sibling in this cpu core going down
1307 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1)
1308 cpu_data(sibling).booted_cores--;
1311 for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu))
1312 cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling));
1313 cpus_clear(per_cpu(cpu_sibling_map, cpu));
1314 cpus_clear(per_cpu(cpu_core_map, cpu));
1315 c->phys_proc_id = 0;
1317 cpu_clear(cpu, cpu_sibling_setup_map);
1320 int additional_cpus __initdata = -1;
1322 static __init int setup_additional_cpus(char *s)
1324 return s && get_option(&s, &additional_cpus) ? 0 : -EINVAL;
1326 early_param("additional_cpus", setup_additional_cpus);
1329 * cpu_possible_map should be static, it cannot change as cpu's
1330 * are onlined, or offlined. The reason is per-cpu data-structures
1331 * are allocated by some modules at init time, and dont expect to
1332 * do this dynamically on cpu arrival/departure.
1333 * cpu_present_map on the other hand can change dynamically.
1334 * In case when cpu_hotplug is not compiled, then we resort to current
1335 * behaviour, which is cpu_possible == cpu_present.
1338 * Three ways to find out the number of additional hotplug CPUs:
1339 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1340 * - The user can overwrite it with additional_cpus=NUM
1341 * - Otherwise don't reserve additional CPUs.
1342 * We do this because additional CPUs waste a lot of memory.
1345 __init void prefill_possible_map(void)
1350 if (additional_cpus == -1) {
1351 if (disabled_cpus > 0)
1352 additional_cpus = disabled_cpus;
1354 additional_cpus = 0;
1356 possible = num_processors + additional_cpus;
1357 if (possible > NR_CPUS)
1360 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1361 possible, max_t(int, possible - num_processors, 0));
1363 for (i = 0; i < possible; i++)
1364 cpu_set(i, cpu_possible_map);
1367 static void __ref remove_cpu_from_maps(int cpu)
1369 cpu_clear(cpu, cpu_online_map);
1370 #ifdef CONFIG_X86_64
1371 cpu_clear(cpu, cpu_callout_map);
1372 cpu_clear(cpu, cpu_callin_map);
1373 /* was set by cpu_init() */
1374 clear_bit(cpu, (unsigned long *)&cpu_initialized);
1375 clear_node_cpumask(cpu);
1379 int __cpu_disable(void)
1381 int cpu = smp_processor_id();
1384 * Perhaps use cpufreq to drop frequency, but that could go
1385 * into generic code.
1387 * We won't take down the boot processor on i386 due to some
1388 * interrupts only being able to be serviced by the BSP.
1389 * Especially so if we're not using an IOAPIC -zwane
1394 if (nmi_watchdog == NMI_LOCAL_APIC)
1395 stop_apic_nmi_watchdog(NULL);
1400 * Allow any queued timer interrupts to get serviced
1401 * This is only a temporary solution until we cleanup
1402 * fixup_irqs as we do for IA64.
1407 local_irq_disable();
1408 remove_siblinginfo(cpu);
1410 /* It's now safe to remove this processor from the online map */
1411 remove_cpu_from_maps(cpu);
1412 fixup_irqs(cpu_online_map);
1416 void __cpu_die(unsigned int cpu)
1418 /* We don't do anything here: idle task is faking death itself. */
1421 for (i = 0; i < 10; i++) {
1422 /* They ack this in play_dead by setting CPU_DEAD */
1423 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1424 printk(KERN_INFO "CPU %d is now offline\n", cpu);
1425 if (1 == num_online_cpus())
1426 alternatives_smp_switch(0);
1431 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1433 #else /* ... !CONFIG_HOTPLUG_CPU */
1434 int __cpu_disable(void)
1439 void __cpu_die(unsigned int cpu)
1441 /* We said "no" in __cpu_disable */
1447 * If the BIOS enumerates physical processors before logical,
1448 * maxcpus=N at enumeration-time can be used to disable HT.
1450 static int __init parse_maxcpus(char *arg)
1452 extern unsigned int maxcpus;
1454 maxcpus = simple_strtoul(arg, NULL, 0);
1457 early_param("maxcpus", parse_maxcpus);