2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
21 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
22 * so the code in this file is compiled twice, once per pte size.
26 #define pt_element_t u64
27 #define guest_walker guest_walker64
28 #define FNAME(name) paging##64_##name
29 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
30 #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
31 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
32 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
33 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
48 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
49 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
50 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
51 #define PT_LEVEL_BITS PT32_LEVEL_BITS
52 #define PT_MAX_FULL_LEVELS 2
53 #define CMPXCHG cmpxchg
55 #error Invalid PTTYPE value
58 #define gpte_to_gfn FNAME(gpte_to_gfn)
59 #define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
62 * The guest_walker structure emulates the behavior of the hardware page
67 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
68 pt_element_t ptes[PT_MAX_FULL_LEVELS];
69 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
76 static gfn_t gpte_to_gfn(pt_element_t gpte)
78 return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
81 static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
83 return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
86 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
87 gfn_t table_gfn, unsigned index,
88 pt_element_t orig_pte, pt_element_t new_pte)
94 down_read(¤t->mm->mmap_sem);
95 page = gfn_to_page(kvm, table_gfn);
96 up_read(¤t->mm->mmap_sem);
98 table = kmap_atomic(page, KM_USER0);
100 ret = CMPXCHG(&table[index], orig_pte, new_pte);
102 kunmap_atomic(table, KM_USER0);
104 kvm_release_page_dirty(page);
106 return (ret != orig_pte);
109 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
113 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
116 access &= ~(gpte >> PT64_NX_SHIFT);
122 * Fetch a guest pte for a guest virtual address
124 static int FNAME(walk_addr)(struct guest_walker *walker,
125 struct kvm_vcpu *vcpu, gva_t addr,
126 int write_fault, int user_fault, int fetch_fault)
130 unsigned index, pt_access, pte_access;
133 pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
135 walker->level = vcpu->arch.mmu.root_level;
136 pte = vcpu->arch.cr3;
138 if (!is_long_mode(vcpu)) {
139 pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
140 if (!is_present_pte(pte))
145 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
146 (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
151 index = PT_INDEX(addr, walker->level);
153 table_gfn = gpte_to_gfn(pte);
154 pte_gpa = gfn_to_gpa(table_gfn);
155 pte_gpa += index * sizeof(pt_element_t);
156 walker->table_gfn[walker->level - 1] = table_gfn;
157 walker->pte_gpa[walker->level - 1] = pte_gpa;
158 pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
159 walker->level - 1, table_gfn);
161 kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
163 if (!is_present_pte(pte))
166 if (write_fault && !is_writeble_pte(pte))
167 if (user_fault || is_write_protection(vcpu))
170 if (user_fault && !(pte & PT_USER_MASK))
174 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
178 if (!(pte & PT_ACCESSED_MASK)) {
179 mark_page_dirty(vcpu->kvm, table_gfn);
180 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
181 index, pte, pte|PT_ACCESSED_MASK))
183 pte |= PT_ACCESSED_MASK;
186 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
188 walker->ptes[walker->level - 1] = pte;
190 if (walker->level == PT_PAGE_TABLE_LEVEL) {
191 walker->gfn = gpte_to_gfn(pte);
195 if (walker->level == PT_DIRECTORY_LEVEL
196 && (pte & PT_PAGE_SIZE_MASK)
197 && (PTTYPE == 64 || is_pse(vcpu))) {
198 walker->gfn = gpte_to_gfn_pde(pte);
199 walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
200 if (PTTYPE == 32 && is_cpuid_PSE36())
201 walker->gfn += pse36_gfn_delta(pte);
205 pt_access = pte_access;
209 if (write_fault && !is_dirty_pte(pte)) {
212 mark_page_dirty(vcpu->kvm, table_gfn);
213 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
217 pte |= PT_DIRTY_MASK;
218 kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
219 walker->ptes[walker->level - 1] = pte;
222 walker->pt_access = pt_access;
223 walker->pte_access = pte_access;
224 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
225 __FUNCTION__, (u64)pte, pt_access, pte_access);
229 walker->error_code = 0;
233 walker->error_code = PFERR_PRESENT_MASK;
237 walker->error_code |= PFERR_WRITE_MASK;
239 walker->error_code |= PFERR_USER_MASK;
241 walker->error_code |= PFERR_FETCH_MASK;
245 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
246 u64 *spte, const void *pte)
252 gpte = *(const pt_element_t *)pte;
253 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
254 if (!is_present_pte(gpte))
255 set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
258 pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
259 pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
260 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
262 npage = vcpu->arch.update_pte.page;
266 mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
267 gpte & PT_DIRTY_MASK, NULL, gpte_to_gfn(gpte), npage);
271 * Fetch a shadow pte for a specific level in the paging hierarchy.
273 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
274 struct guest_walker *walker,
275 int user_fault, int write_fault, int *ptwrite,
281 unsigned access = walker->pt_access;
283 if (!is_present_pte(walker->ptes[walker->level - 1]))
286 shadow_addr = vcpu->arch.mmu.root_hpa;
287 level = vcpu->arch.mmu.shadow_root_level;
288 if (level == PT32E_ROOT_LEVEL) {
289 shadow_addr = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
290 shadow_addr &= PT64_BASE_ADDR_MASK;
295 u32 index = SHADOW_PT_INDEX(addr, level);
296 struct kvm_mmu_page *shadow_page;
301 shadow_ent = ((u64 *)__va(shadow_addr)) + index;
302 if (level == PT_PAGE_TABLE_LEVEL)
304 if (is_shadow_present_pte(*shadow_ent)) {
305 shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
309 if (level - 1 == PT_PAGE_TABLE_LEVEL
310 && walker->level == PT_DIRECTORY_LEVEL) {
312 if (!is_dirty_pte(walker->ptes[level - 1]))
313 access &= ~ACC_WRITE_MASK;
314 table_gfn = gpte_to_gfn(walker->ptes[level - 1]);
317 table_gfn = walker->table_gfn[level - 2];
319 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
320 metaphysical, access,
324 pt_element_t curr_pte;
325 r = kvm_read_guest_atomic(vcpu->kvm,
326 walker->pte_gpa[level - 2],
327 &curr_pte, sizeof(curr_pte));
328 if (r || curr_pte != walker->ptes[level - 2]) {
329 kvm_release_page_clean(page);
333 shadow_addr = __pa(shadow_page->spt);
334 shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
335 | PT_WRITABLE_MASK | PT_USER_MASK;
336 *shadow_ent = shadow_pte;
339 mmu_set_spte(vcpu, shadow_ent, access, walker->pte_access & access,
340 user_fault, write_fault,
341 walker->ptes[walker->level-1] & PT_DIRTY_MASK,
342 ptwrite, walker->gfn, page);
348 * Page fault handler. There are several causes for a page fault:
349 * - there is no shadow pte for the guest pte
350 * - write access through a shadow pte marked read only so that we can set
352 * - write access to a shadow pte marked read only so we can update the page
353 * dirty bitmap, when userspace requests it
354 * - mmio access; in this case we will never install a present shadow pte
355 * - normal guest page fault due to the guest pte marked not present, not
356 * writable, or not executable
358 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
359 * a negative value on error.
361 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
364 int write_fault = error_code & PFERR_WRITE_MASK;
365 int user_fault = error_code & PFERR_USER_MASK;
366 int fetch_fault = error_code & PFERR_FETCH_MASK;
367 struct guest_walker walker;
373 pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
374 kvm_mmu_audit(vcpu, "pre page fault");
376 r = mmu_topup_memory_caches(vcpu);
380 down_read(&vcpu->kvm->slots_lock);
382 * Look up the shadow pte for the faulting address.
384 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
388 * The page is not mapped by the guest. Let the guest handle it.
391 pgprintk("%s: guest page fault\n", __FUNCTION__);
392 inject_page_fault(vcpu, addr, walker.error_code);
393 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
394 up_read(&vcpu->kvm->slots_lock);
398 down_read(¤t->mm->mmap_sem);
399 page = gfn_to_page(vcpu->kvm, walker.gfn);
400 up_read(¤t->mm->mmap_sem);
402 spin_lock(&vcpu->kvm->mmu_lock);
403 kvm_mmu_free_some_pages(vcpu);
404 shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
406 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
407 shadow_pte, *shadow_pte, write_pt);
410 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
413 * mmio: emulate if accessible, otherwise its a guest fault.
415 if (shadow_pte && is_io_pte(*shadow_pte)) {
416 spin_unlock(&vcpu->kvm->mmu_lock);
417 up_read(&vcpu->kvm->slots_lock);
421 ++vcpu->stat.pf_fixed;
422 kvm_mmu_audit(vcpu, "post page fault (fixed)");
423 spin_unlock(&vcpu->kvm->mmu_lock);
424 up_read(&vcpu->kvm->slots_lock);
429 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
431 struct guest_walker walker;
432 gpa_t gpa = UNMAPPED_GVA;
435 r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
438 gpa = gfn_to_gpa(walker.gfn);
439 gpa |= vaddr & ~PAGE_MASK;
445 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
446 struct kvm_mmu_page *sp)
448 int i, offset = 0, r = 0;
451 if (sp->role.metaphysical
452 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
453 nonpaging_prefetch_page(vcpu, sp);
458 offset = sp->role.quadrant << PT64_LEVEL_BITS;
460 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
461 gpa_t pte_gpa = gfn_to_gpa(sp->gfn);
462 pte_gpa += (i+offset) * sizeof(pt_element_t);
464 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &pt,
465 sizeof(pt_element_t));
466 if (r || is_present_pte(pt))
467 sp->spt[i] = shadow_trap_nonpresent_pte;
469 sp->spt[i] = shadow_notrap_nonpresent_pte;
476 #undef PT_BASE_ADDR_MASK
478 #undef SHADOW_PT_INDEX
480 #undef PT_DIR_BASE_ADDR_MASK
482 #undef PT_MAX_FULL_LEVELS
484 #undef gpte_to_gfn_pde