arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/vmalloc.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27
  28 #include <asm/desc.h>
  29
  30 MODULE_AUTHOR("Qumranet");
  31 MODULE_LICENSE("GPL");
  32
  33 #define IOPM_ALLOC_ORDER 2
  34 #define MSRPM_ALLOC_ORDER 1
  35
  36 #define DB_VECTOR 1
  37 #define UD_VECTOR 6
  38 #define GP_VECTOR 13
  39
  40 #define DR7_GD_MASK (1 << 13)
  41 #define DR6_BD_MASK (1 << 13)
  42
  43 #define SEG_TYPE_LDT 2
  44 #define SEG_TYPE_BUSY_TSS16 3
  45
  46 #define SVM_FEATURE_NPT  (1 << 0)
  47 #define SVM_FEATURE_LBRV (1 << 1)
  48 #define SVM_DEATURE_SVML (1 << 2)
  49
  50 /* enable NPT for AMD64 and X86 with PAE */
  51 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  52 static bool npt_enabled = true;
  53 #else
  54 static bool npt_enabled = false;
  55 #endif
  56 static int npt = 1;
  57
  58 module_param(npt, int, S_IRUGO);
  59
  60 static void kvm_reput_irq(struct vcpu_svm *svm);
  61
  62 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  63 {
  64         return container_of(vcpu, struct vcpu_svm, vcpu);
  65 }
  66
  67 unsigned long iopm_base;
  68
  69 struct kvm_ldttss_desc {
  70         u16 limit0;
  71         u16 base0;
  72         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  73         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  74         u32 base3;
  75         u32 zero1;
  76 } __attribute__((packed));
  77
  78 struct svm_cpu_data {
  79         int cpu;
  80
  81         u64 asid_generation;
  82         u32 max_asid;
  83         u32 next_asid;
  84         struct kvm_ldttss_desc *tss_desc;
  85
  86         struct page *save_area;
  87 };
  88
  89 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  90 static uint32_t svm_features;
  91
  92 struct svm_init_data {
  93         int cpu;
  94         int r;
  95 };
  96
  97 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
  98
  99 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 100 #define MSRS_RANGE_SIZE 2048
 101 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 102
 103 #define MAX_INST_SIZE 15
 104
 105 static inline u32 svm_has(u32 feat)
 106 {
 107         return svm_features & feat;
 108 }
 109
 110 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 111 {
 112         int word_index = __ffs(vcpu->arch.irq_summary);
 113         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 114         int irq = word_index * BITS_PER_LONG + bit_index;
 115
 116         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 117         if (!vcpu->arch.irq_pending[word_index])
 118                 clear_bit(word_index, &vcpu->arch.irq_summary);
 119         return irq;
 120 }
 121
 122 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 123 {
 124         set_bit(irq, vcpu->arch.irq_pending);
 125         set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 126 }
 127
 128 static inline void clgi(void)
 129 {
 130         asm volatile (SVM_CLGI);
 131 }
 132
 133 static inline void stgi(void)
 134 {
 135         asm volatile (SVM_STGI);
 136 }
 137
 138 static inline void invlpga(unsigned long addr, u32 asid)
 139 {
 140         asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
 141 }
 142
 143 static inline unsigned long kvm_read_cr2(void)
 144 {
 145         unsigned long cr2;
 146
 147         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 148         return cr2;
 149 }
 150
 151 static inline void kvm_write_cr2(unsigned long val)
 152 {
 153         asm volatile ("mov %0, %%cr2" :: "r" (val));
 154 }
 155
 156 static inline unsigned long read_dr6(void)
 157 {
 158         unsigned long dr6;
 159
 160         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 161         return dr6;
 162 }
 163
 164 static inline void write_dr6(unsigned long val)
 165 {
 166         asm volatile ("mov %0, %%dr6" :: "r" (val));
 167 }
 168
 169 static inline unsigned long read_dr7(void)
 170 {
 171         unsigned long dr7;
 172
 173         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 174         return dr7;
 175 }
 176
 177 static inline void write_dr7(unsigned long val)
 178 {
 179         asm volatile ("mov %0, %%dr7" :: "r" (val));
 180 }
 181
 182 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 183 {
 184         to_svm(vcpu)->asid_generation--;
 185 }
 186
 187 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 188 {
 189         force_new_asid(vcpu);
 190 }
 191
 192 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 193 {
 194         if (!npt_enabled && !(efer & EFER_LMA))
 195                 efer &= ~EFER_LME;
 196
 197         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 198         vcpu->arch.shadow_efer = efer;
 199 }
 200
 201 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 202                                 bool has_error_code, u32 error_code)
 203 {
 204         struct vcpu_svm *svm = to_svm(vcpu);
 205
 206         svm->vmcb->control.event_inj = nr
 207                 | SVM_EVTINJ_VALID
 208                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 209                 | SVM_EVTINJ_TYPE_EXEPT;
 210         svm->vmcb->control.event_inj_err = error_code;
 211 }
 212
 213 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 214 {
 215         struct vcpu_svm *svm = to_svm(vcpu);
 216
 217         return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 218 }
 219
 220 static int is_external_interrupt(u32 info)
 221 {
 222         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 223         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 224 }
 225
 226 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 227 {
 228         struct vcpu_svm *svm = to_svm(vcpu);
 229
 230         if (!svm->next_rip) {
 231                 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
 232                 return;
 233         }
 234         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 235                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 236                        __FUNCTION__,
 237                        svm->vmcb->save.rip,
 238                        svm->next_rip);
 239
 240         vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
 241         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 242
 243         vcpu->arch.interrupt_window_open = 1;
 244 }
 245
 246 static int has_svm(void)
 247 {
 248         uint32_t eax, ebx, ecx, edx;
 249
 250         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 251                 printk(KERN_INFO "has_svm: not amd\n");
 252                 return 0;
 253         }
 254
 255         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 256         if (eax < SVM_CPUID_FUNC) {
 257                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 258                 return 0;
 259         }
 260
 261         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 262         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 263                 printk(KERN_DEBUG "has_svm: svm not available\n");
 264                 return 0;
 265         }
 266         return 1;
 267 }
 268
 269 static void svm_hardware_disable(void *garbage)
 270 {
 271         struct svm_cpu_data *svm_data
 272                 = per_cpu(svm_data, raw_smp_processor_id());
 273
 274         if (svm_data) {
 275                 uint64_t efer;
 276
 277                 wrmsrl(MSR_VM_HSAVE_PA, 0);
 278                 rdmsrl(MSR_EFER, efer);
 279                 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 280                 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 281                 __free_page(svm_data->save_area);
 282                 kfree(svm_data);
 283         }
 284 }
 285
 286 static void svm_hardware_enable(void *garbage)
 287 {
 288
 289         struct svm_cpu_data *svm_data;
 290         uint64_t efer;
 291 #ifdef CONFIG_X86_64
 292         struct desc_ptr gdt_descr;
 293 #else
 294         struct desc_ptr gdt_descr;
 295 #endif
 296         struct desc_struct *gdt;
 297         int me = raw_smp_processor_id();
 298
 299         if (!has_svm()) {
 300                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 301                 return;
 302         }
 303         svm_data = per_cpu(svm_data, me);
 304
 305         if (!svm_data) {
 306                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 307                        me);
 308                 return;
 309         }
 310
 311         svm_data->asid_generation = 1;
 312         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 313         svm_data->next_asid = svm_data->max_asid + 1;
 314
 315         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 316         gdt = (struct desc_struct *)gdt_descr.address;
 317         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 318
 319         rdmsrl(MSR_EFER, efer);
 320         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 321
 322         wrmsrl(MSR_VM_HSAVE_PA,
 323                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 324 }
 325
 326 static int svm_cpu_init(int cpu)
 327 {
 328         struct svm_cpu_data *svm_data;
 329         int r;
 330
 331         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 332         if (!svm_data)
 333                 return -ENOMEM;
 334         svm_data->cpu = cpu;
 335         svm_data->save_area = alloc_page(GFP_KERNEL);
 336         r = -ENOMEM;
 337         if (!svm_data->save_area)
 338                 goto err_1;
 339
 340         per_cpu(svm_data, cpu) = svm_data;
 341
 342         return 0;
 343
 344 err_1:
 345         kfree(svm_data);
 346         return r;
 347
 348 }
 349
 350 static void set_msr_interception(u32 *msrpm, unsigned msr,
 351                                  int read, int write)
 352 {
 353         int i;
 354
 355         for (i = 0; i < NUM_MSR_MAPS; i++) {
 356                 if (msr >= msrpm_ranges[i] &&
 357                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 358                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 359                                           msrpm_ranges[i]) * 2;
 360
 361                         u32 *base = msrpm + (msr_offset / 32);
 362                         u32 msr_shift = msr_offset % 32;
 363                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 364                         *base = (*base & ~(0x3 << msr_shift)) |
 365                                 (mask << msr_shift);
 366                         return;
 367                 }
 368         }
 369         BUG();
 370 }
 371
 372 static void svm_vcpu_init_msrpm(u32 *msrpm)
 373 {
 374         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 375
 376 #ifdef CONFIG_X86_64
 377         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 378         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 379         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 380         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 381         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 382         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 383 #endif
 384         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 385         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 386         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 387         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 388 }
 389
 390 static __init int svm_hardware_setup(void)
 391 {
 392         int cpu;
 393         struct page *iopm_pages;
 394         void *iopm_va;
 395         int r;
 396
 397         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 398
 399         if (!iopm_pages)
 400                 return -ENOMEM;
 401
 402         iopm_va = page_address(iopm_pages);
 403         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 404         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 405         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 406
 407         if (boot_cpu_has(X86_FEATURE_NX))
 408                 kvm_enable_efer_bits(EFER_NX);
 409
 410         for_each_online_cpu(cpu) {
 411                 r = svm_cpu_init(cpu);
 412                 if (r)
 413                         goto err;
 414         }
 415
 416         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 417
 418         if (!svm_has(SVM_FEATURE_NPT))
 419                 npt_enabled = false;
 420
 421         if (npt_enabled && !npt) {
 422                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 423                 npt_enabled = false;
 424         }
 425
 426         if (npt_enabled) {
 427                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 428                 kvm_enable_tdp();
 429         }
 430
 431         return 0;
 432
 433 err:
 434         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 435         iopm_base = 0;
 436         return r;
 437 }
 438
 439 static __exit void svm_hardware_unsetup(void)
 440 {
 441         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 442         iopm_base = 0;
 443 }
 444
 445 static void init_seg(struct vmcb_seg *seg)
 446 {
 447         seg->selector = 0;
 448         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 449                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 450         seg->limit = 0xffff;
 451         seg->base = 0;
 452 }
 453
 454 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 455 {
 456         seg->selector = 0;
 457         seg->attrib = SVM_SELECTOR_P_MASK | type;
 458         seg->limit = 0xffff;
 459         seg->base = 0;
 460 }
 461
 462 static void init_vmcb(struct vcpu_svm *svm)
 463 {
 464         struct vmcb_control_area *control = &svm->vmcb->control;
 465         struct vmcb_save_area *save = &svm->vmcb->save;
 466
 467         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 468                                         INTERCEPT_CR3_MASK |
 469                                         INTERCEPT_CR4_MASK |
 470                                         INTERCEPT_CR8_MASK;
 471
 472         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 473                                         INTERCEPT_CR3_MASK |
 474                                         INTERCEPT_CR4_MASK |
 475                                         INTERCEPT_CR8_MASK;
 476
 477         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 478                                         INTERCEPT_DR1_MASK |
 479                                         INTERCEPT_DR2_MASK |
 480                                         INTERCEPT_DR3_MASK;
 481
 482         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 483                                         INTERCEPT_DR1_MASK |
 484                                         INTERCEPT_DR2_MASK |
 485                                         INTERCEPT_DR3_MASK |
 486                                         INTERCEPT_DR5_MASK |
 487                                         INTERCEPT_DR7_MASK;
 488
 489         control->intercept_exceptions = (1 << PF_VECTOR) |
 490                                         (1 << UD_VECTOR);
 491
 492
 493         control->intercept =    (1ULL << INTERCEPT_INTR) |
 494                                 (1ULL << INTERCEPT_NMI) |
 495                                 (1ULL << INTERCEPT_SMI) |
 496                 /*
 497                  * selective cr0 intercept bug?
 498                  *      0:   0f 22 d8                mov    %eax,%cr3
 499                  *      3:   0f 20 c0                mov    %cr0,%eax
 500                  *      6:   0d 00 00 00 80          or     $0x80000000,%eax
 501                  *      b:   0f 22 c0                mov    %eax,%cr0
 502                  * set cr3 ->interception
 503                  * get cr0 ->interception
 504                  * set cr0 -> no interception
 505                  */
 506                 /*              (1ULL << INTERCEPT_SELECTIVE_CR0) | */
 507                                 (1ULL << INTERCEPT_CPUID) |
 508                                 (1ULL << INTERCEPT_INVD) |
 509                                 (1ULL << INTERCEPT_HLT) |
 510                                 (1ULL << INTERCEPT_INVLPGA) |
 511                                 (1ULL << INTERCEPT_IOIO_PROT) |
 512                                 (1ULL << INTERCEPT_MSR_PROT) |
 513                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 514                                 (1ULL << INTERCEPT_SHUTDOWN) |
 515                                 (1ULL << INTERCEPT_VMRUN) |
 516                                 (1ULL << INTERCEPT_VMMCALL) |
 517                                 (1ULL << INTERCEPT_VMLOAD) |
 518                                 (1ULL << INTERCEPT_VMSAVE) |
 519                                 (1ULL << INTERCEPT_STGI) |
 520                                 (1ULL << INTERCEPT_CLGI) |
 521                                 (1ULL << INTERCEPT_SKINIT) |
 522                                 (1ULL << INTERCEPT_WBINVD) |
 523                                 (1ULL << INTERCEPT_MONITOR) |
 524                                 (1ULL << INTERCEPT_MWAIT);
 525
 526         control->iopm_base_pa = iopm_base;
 527         control->msrpm_base_pa = __pa(svm->msrpm);
 528         control->tsc_offset = 0;
 529         control->int_ctl = V_INTR_MASKING_MASK;
 530
 531         init_seg(&save->es);
 532         init_seg(&save->ss);
 533         init_seg(&save->ds);
 534         init_seg(&save->fs);
 535         init_seg(&save->gs);
 536
 537         save->cs.selector = 0xf000;
 538         /* Executable/Readable Code Segment */
 539         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 540                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 541         save->cs.limit = 0xffff;
 542         /*
 543          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 544          * be consistent with it.
 545          *
 546          * Replace when we have real mode working for vmx.
 547          */
 548         save->cs.base = 0xf0000;
 549
 550         save->gdtr.limit = 0xffff;
 551         save->idtr.limit = 0xffff;
 552
 553         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 554         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 555
 556         save->efer = MSR_EFER_SVME_MASK;
 557         save->dr6 = 0xffff0ff0;
 558         save->dr7 = 0x400;
 559         save->rflags = 2;
 560         save->rip = 0x0000fff0;
 561
 562         /*
 563          * cr0 val on cpu init should be 0x60000010, we enable cpu
 564          * cache by default. the orderly way is to enable cache in bios.
 565          */
 566         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 567         save->cr4 = X86_CR4_PAE;
 568         /* rdx = ?? */
 569
 570         if (npt_enabled) {
 571                 /* Setup VMCB for Nested Paging */
 572                 control->nested_ctl = 1;
 573                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 574                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 575                                                 INTERCEPT_CR3_MASK);
 576                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 577                                                  INTERCEPT_CR3_MASK);
 578                 save->g_pat = 0x0007040600070406ULL;
 579                 /* enable caching because the QEMU Bios doesn't enable it */
 580                 save->cr0 = X86_CR0_ET;
 581                 save->cr3 = 0;
 582                 save->cr4 = 0;
 583         }
 584
 585 }
 586
 587 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 588 {
 589         struct vcpu_svm *svm = to_svm(vcpu);
 590
 591         init_vmcb(svm);
 592
 593         if (vcpu->vcpu_id != 0) {
 594                 svm->vmcb->save.rip = 0;
 595                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 596                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 597         }
 598
 599         return 0;
 600 }
 601
 602 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 603 {
 604         struct vcpu_svm *svm;
 605         struct page *page;
 606         struct page *msrpm_pages;
 607         int err;
 608
 609         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 610         if (!svm) {
 611                 err = -ENOMEM;
 612                 goto out;
 613         }
 614
 615         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 616         if (err)
 617                 goto free_svm;
 618
 619         page = alloc_page(GFP_KERNEL);
 620         if (!page) {
 621                 err = -ENOMEM;
 622                 goto uninit;
 623         }
 624
 625         err = -ENOMEM;
 626         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 627         if (!msrpm_pages)
 628                 goto uninit;
 629         svm->msrpm = page_address(msrpm_pages);
 630         svm_vcpu_init_msrpm(svm->msrpm);
 631
 632         svm->vmcb = page_address(page);
 633         clear_page(svm->vmcb);
 634         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 635         svm->asid_generation = 0;
 636         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 637         init_vmcb(svm);
 638
 639         fx_init(&svm->vcpu);
 640         svm->vcpu.fpu_active = 1;
 641         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 642         if (svm->vcpu.vcpu_id == 0)
 643                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 644
 645         return &svm->vcpu;
 646
 647 uninit:
 648         kvm_vcpu_uninit(&svm->vcpu);
 649 free_svm:
 650         kmem_cache_free(kvm_vcpu_cache, svm);
 651 out:
 652         return ERR_PTR(err);
 653 }
 654
 655 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 656 {
 657         struct vcpu_svm *svm = to_svm(vcpu);
 658
 659         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 660         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 661         kvm_vcpu_uninit(vcpu);
 662         kmem_cache_free(kvm_vcpu_cache, svm);
 663 }
 664
 665 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 666 {
 667         struct vcpu_svm *svm = to_svm(vcpu);
 668         int i;
 669
 670         if (unlikely(cpu != vcpu->cpu)) {
 671                 u64 tsc_this, delta;
 672
 673                 /*
 674                  * Make sure that the guest sees a monotonically
 675                  * increasing TSC.
 676                  */
 677                 rdtscll(tsc_this);
 678                 delta = vcpu->arch.host_tsc - tsc_this;
 679                 svm->vmcb->control.tsc_offset += delta;
 680                 vcpu->cpu = cpu;
 681                 kvm_migrate_apic_timer(vcpu);
 682         }
 683
 684         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 685                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 686 }
 687
 688 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 689 {
 690         struct vcpu_svm *svm = to_svm(vcpu);
 691         int i;
 692
 693         ++vcpu->stat.host_state_reload;
 694         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 695                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 696
 697         rdtscll(vcpu->arch.host_tsc);
 698 }
 699
 700 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
 701 {
 702 }
 703
 704 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 705 {
 706         struct vcpu_svm *svm = to_svm(vcpu);
 707
 708         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 709         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 710         vcpu->arch.rip = svm->vmcb->save.rip;
 711 }
 712
 713 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 714 {
 715         struct vcpu_svm *svm = to_svm(vcpu);
 716         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
 717         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
 718         svm->vmcb->save.rip = vcpu->arch.rip;
 719 }
 720
 721 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 722 {
 723         return to_svm(vcpu)->vmcb->save.rflags;
 724 }
 725
 726 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 727 {
 728         to_svm(vcpu)->vmcb->save.rflags = rflags;
 729 }
 730
 731 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 732 {
 733         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 734
 735         switch (seg) {
 736         case VCPU_SREG_CS: return &save->cs;
 737         case VCPU_SREG_DS: return &save->ds;
 738         case VCPU_SREG_ES: return &save->es;
 739         case VCPU_SREG_FS: return &save->fs;
 740         case VCPU_SREG_GS: return &save->gs;
 741         case VCPU_SREG_SS: return &save->ss;
 742         case VCPU_SREG_TR: return &save->tr;
 743         case VCPU_SREG_LDTR: return &save->ldtr;
 744         }
 745         BUG();
 746         return NULL;
 747 }
 748
 749 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 750 {
 751         struct vmcb_seg *s = svm_seg(vcpu, seg);
 752
 753         return s->base;
 754 }
 755
 756 static void svm_get_segment(struct kvm_vcpu *vcpu,
 757                             struct kvm_segment *var, int seg)
 758 {
 759         struct vmcb_seg *s = svm_seg(vcpu, seg);
 760
 761         var->base = s->base;
 762         var->limit = s->limit;
 763         var->selector = s->selector;
 764         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 765         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 766         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 767         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 768         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 769         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 770         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 771         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 772         var->unusable = !var->present;
 773 }
 774
 775 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 776 {
 777         struct vcpu_svm *svm = to_svm(vcpu);
 778
 779         dt->limit = svm->vmcb->save.idtr.limit;
 780         dt->base = svm->vmcb->save.idtr.base;
 781 }
 782
 783 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 784 {
 785         struct vcpu_svm *svm = to_svm(vcpu);
 786
 787         svm->vmcb->save.idtr.limit = dt->limit;
 788         svm->vmcb->save.idtr.base = dt->base ;
 789 }
 790
 791 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 792 {
 793         struct vcpu_svm *svm = to_svm(vcpu);
 794
 795         dt->limit = svm->vmcb->save.gdtr.limit;
 796         dt->base = svm->vmcb->save.gdtr.base;
 797 }
 798
 799 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 800 {
 801         struct vcpu_svm *svm = to_svm(vcpu);
 802
 803         svm->vmcb->save.gdtr.limit = dt->limit;
 804         svm->vmcb->save.gdtr.base = dt->base ;
 805 }
 806
 807 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 808 {
 809 }
 810
 811 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 812 {
 813         struct vcpu_svm *svm = to_svm(vcpu);
 814
 815 #ifdef CONFIG_X86_64
 816         if (vcpu->arch.shadow_efer & EFER_LME) {
 817                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 818                         vcpu->arch.shadow_efer |= EFER_LMA;
 819                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 820                 }
 821
 822                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 823                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 824                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 825                 }
 826         }
 827 #endif
 828         if (npt_enabled)
 829                 goto set;
 830
 831         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 832                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 833                 vcpu->fpu_active = 1;
 834         }
 835
 836         vcpu->arch.cr0 = cr0;
 837         cr0 |= X86_CR0_PG | X86_CR0_WP;
 838         if (!vcpu->fpu_active) {
 839                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 840                 cr0 |= X86_CR0_TS;
 841         }
 842 set:
 843         /*
 844          * re-enable caching here because the QEMU bios
 845          * does not do it - this results in some delay at
 846          * reboot
 847          */
 848         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 849         svm->vmcb->save.cr0 = cr0;
 850 }
 851
 852 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 853 {
 854        vcpu->arch.cr4 = cr4;
 855        if (!npt_enabled)
 856                cr4 |= X86_CR4_PAE;
 857        to_svm(vcpu)->vmcb->save.cr4 = cr4;
 858 }
 859
 860 static void svm_set_segment(struct kvm_vcpu *vcpu,
 861                             struct kvm_segment *var, int seg)
 862 {
 863         struct vcpu_svm *svm = to_svm(vcpu);
 864         struct vmcb_seg *s = svm_seg(vcpu, seg);
 865
 866         s->base = var->base;
 867         s->limit = var->limit;
 868         s->selector = var->selector;
 869         if (var->unusable)
 870                 s->attrib = 0;
 871         else {
 872                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 873                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 874                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 875                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 876                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 877                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 878                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 879                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 880         }
 881         if (seg == VCPU_SREG_CS)
 882                 svm->vmcb->save.cpl
 883                         = (svm->vmcb->save.cs.attrib
 884                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 885
 886 }
 887
 888 /* FIXME:
 889
 890         svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
 891         svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
 892
 893 */
 894
 895 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 896 {
 897         return -EOPNOTSUPP;
 898 }
 899
 900 static int svm_get_irq(struct kvm_vcpu *vcpu)
 901 {
 902         struct vcpu_svm *svm = to_svm(vcpu);
 903         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 904
 905         if (is_external_interrupt(exit_int_info))
 906                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 907         return -1;
 908 }
 909
 910 static void load_host_msrs(struct kvm_vcpu *vcpu)
 911 {
 912 #ifdef CONFIG_X86_64
 913         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 914 #endif
 915 }
 916
 917 static void save_host_msrs(struct kvm_vcpu *vcpu)
 918 {
 919 #ifdef CONFIG_X86_64
 920         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 921 #endif
 922 }
 923
 924 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 925 {
 926         if (svm_data->next_asid > svm_data->max_asid) {
 927                 ++svm_data->asid_generation;
 928                 svm_data->next_asid = 1;
 929                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 930         }
 931
 932         svm->vcpu.cpu = svm_data->cpu;
 933         svm->asid_generation = svm_data->asid_generation;
 934         svm->vmcb->control.asid = svm_data->next_asid++;
 935 }
 936
 937 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 938 {
 939         return to_svm(vcpu)->db_regs[dr];
 940 }
 941
 942 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 943                        int *exception)
 944 {
 945         struct vcpu_svm *svm = to_svm(vcpu);
 946
 947         *exception = 0;
 948
 949         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 950                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 951                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 952                 *exception = DB_VECTOR;
 953                 return;
 954         }
 955
 956         switch (dr) {
 957         case 0 ... 3:
 958                 svm->db_regs[dr] = value;
 959                 return;
 960         case 4 ... 5:
 961                 if (vcpu->arch.cr4 & X86_CR4_DE) {
 962                         *exception = UD_VECTOR;
 963                         return;
 964                 }
 965         case 7: {
 966                 if (value & ~((1ULL << 32) - 1)) {
 967                         *exception = GP_VECTOR;
 968                         return;
 969                 }
 970                 svm->vmcb->save.dr7 = value;
 971                 return;
 972         }
 973         default:
 974                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 975                        __FUNCTION__, dr);
 976                 *exception = UD_VECTOR;
 977                 return;
 978         }
 979 }
 980
 981 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 982 {
 983         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 984         struct kvm *kvm = svm->vcpu.kvm;
 985         u64 fault_address;
 986         u32 error_code;
 987
 988         if (!irqchip_in_kernel(kvm) &&
 989                 is_external_interrupt(exit_int_info))
 990                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
 991
 992         fault_address  = svm->vmcb->control.exit_info_2;
 993         error_code = svm->vmcb->control.exit_info_1;
 994         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
 995 }
 996
 997 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 998 {
 999         int er;
1000
1001         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1002         if (er != EMULATE_DONE)
1003                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1004         return 1;
1005 }
1006
1007 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1008 {
1009         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1010         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1011                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1012         svm->vcpu.fpu_active = 1;
1013
1014         return 1;
1015 }
1016
1017 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1018 {
1019         /*
1020          * VMCB is undefined after a SHUTDOWN intercept
1021          * so reinitialize it.
1022          */
1023         clear_page(svm->vmcb);
1024         init_vmcb(svm);
1025
1026         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1027         return 0;
1028 }
1029
1030 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1031 {
1032         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1033         int size, down, in, string, rep;
1034         unsigned port;
1035
1036         ++svm->vcpu.stat.io_exits;
1037
1038         svm->next_rip = svm->vmcb->control.exit_info_2;
1039
1040         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1041
1042         if (string) {
1043                 if (emulate_instruction(&svm->vcpu,
1044                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1045                         return 0;
1046                 return 1;
1047         }
1048
1049         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1050         port = io_info >> 16;
1051         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1052         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1053         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1054
1055         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1056 }
1057
1058 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1059 {
1060         return 1;
1061 }
1062
1063 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1064 {
1065         svm->next_rip = svm->vmcb->save.rip + 1;
1066         skip_emulated_instruction(&svm->vcpu);
1067         return kvm_emulate_halt(&svm->vcpu);
1068 }
1069
1070 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1071 {
1072         svm->next_rip = svm->vmcb->save.rip + 3;
1073         skip_emulated_instruction(&svm->vcpu);
1074         kvm_emulate_hypercall(&svm->vcpu);
1075         return 1;
1076 }
1077
1078 static int invalid_op_interception(struct vcpu_svm *svm,
1079                                    struct kvm_run *kvm_run)
1080 {
1081         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1082         return 1;
1083 }
1084
1085 static int task_switch_interception(struct vcpu_svm *svm,
1086                                     struct kvm_run *kvm_run)
1087 {
1088         pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1089         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1090         return 0;
1091 }
1092
1093 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1094 {
1095         svm->next_rip = svm->vmcb->save.rip + 2;
1096         kvm_emulate_cpuid(&svm->vcpu);
1097         return 1;
1098 }
1099
1100 static int emulate_on_interception(struct vcpu_svm *svm,
1101                                    struct kvm_run *kvm_run)
1102 {
1103         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1104                 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1105         return 1;
1106 }
1107
1108 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1109 {
1110         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1111         if (irqchip_in_kernel(svm->vcpu.kvm))
1112                 return 1;
1113         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1114         return 0;
1115 }
1116
1117 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1118 {
1119         struct vcpu_svm *svm = to_svm(vcpu);
1120
1121         switch (ecx) {
1122         case MSR_IA32_TIME_STAMP_COUNTER: {
1123                 u64 tsc;
1124
1125                 rdtscll(tsc);
1126                 *data = svm->vmcb->control.tsc_offset + tsc;
1127                 break;
1128         }
1129         case MSR_K6_STAR:
1130                 *data = svm->vmcb->save.star;
1131                 break;
1132 #ifdef CONFIG_X86_64
1133         case MSR_LSTAR:
1134                 *data = svm->vmcb->save.lstar;
1135                 break;
1136         case MSR_CSTAR:
1137                 *data = svm->vmcb->save.cstar;
1138                 break;
1139         case MSR_KERNEL_GS_BASE:
1140                 *data = svm->vmcb->save.kernel_gs_base;
1141                 break;
1142         case MSR_SYSCALL_MASK:
1143                 *data = svm->vmcb->save.sfmask;
1144                 break;
1145 #endif
1146         case MSR_IA32_SYSENTER_CS:
1147                 *data = svm->vmcb->save.sysenter_cs;
1148                 break;
1149         case MSR_IA32_SYSENTER_EIP:
1150                 *data = svm->vmcb->save.sysenter_eip;
1151                 break;
1152         case MSR_IA32_SYSENTER_ESP:
1153                 *data = svm->vmcb->save.sysenter_esp;
1154                 break;
1155         /* Nobody will change the following 5 values in the VMCB so
1156            we can safely return them on rdmsr. They will always be 0
1157            until LBRV is implemented. */
1158         case MSR_IA32_DEBUGCTLMSR:
1159                 *data = svm->vmcb->save.dbgctl;
1160                 break;
1161         case MSR_IA32_LASTBRANCHFROMIP:
1162                 *data = svm->vmcb->save.br_from;
1163                 break;
1164         case MSR_IA32_LASTBRANCHTOIP:
1165                 *data = svm->vmcb->save.br_to;
1166                 break;
1167         case MSR_IA32_LASTINTFROMIP:
1168                 *data = svm->vmcb->save.last_excp_from;
1169                 break;
1170         case MSR_IA32_LASTINTTOIP:
1171                 *data = svm->vmcb->save.last_excp_to;
1172                 break;
1173         default:
1174                 return kvm_get_msr_common(vcpu, ecx, data);
1175         }
1176         return 0;
1177 }
1178
1179 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1180 {
1181         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1182         u64 data;
1183
1184         if (svm_get_msr(&svm->vcpu, ecx, &data))
1185                 kvm_inject_gp(&svm->vcpu, 0);
1186         else {
1187                 svm->vmcb->save.rax = data & 0xffffffff;
1188                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1189                 svm->next_rip = svm->vmcb->save.rip + 2;
1190                 skip_emulated_instruction(&svm->vcpu);
1191         }
1192         return 1;
1193 }
1194
1195 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1196 {
1197         struct vcpu_svm *svm = to_svm(vcpu);
1198
1199         switch (ecx) {
1200         case MSR_IA32_TIME_STAMP_COUNTER: {
1201                 u64 tsc;
1202
1203                 rdtscll(tsc);
1204                 svm->vmcb->control.tsc_offset = data - tsc;
1205                 break;
1206         }
1207         case MSR_K6_STAR:
1208                 svm->vmcb->save.star = data;
1209                 break;
1210 #ifdef CONFIG_X86_64
1211         case MSR_LSTAR:
1212                 svm->vmcb->save.lstar = data;
1213                 break;
1214         case MSR_CSTAR:
1215                 svm->vmcb->save.cstar = data;
1216                 break;
1217         case MSR_KERNEL_GS_BASE:
1218                 svm->vmcb->save.kernel_gs_base = data;
1219                 break;
1220         case MSR_SYSCALL_MASK:
1221                 svm->vmcb->save.sfmask = data;
1222                 break;
1223 #endif
1224         case MSR_IA32_SYSENTER_CS:
1225                 svm->vmcb->save.sysenter_cs = data;
1226                 break;
1227         case MSR_IA32_SYSENTER_EIP:
1228                 svm->vmcb->save.sysenter_eip = data;
1229                 break;
1230         case MSR_IA32_SYSENTER_ESP:
1231                 svm->vmcb->save.sysenter_esp = data;
1232                 break;
1233         case MSR_IA32_DEBUGCTLMSR:
1234                 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1235                                 __FUNCTION__, data);
1236                 break;
1237         case MSR_K7_EVNTSEL0:
1238         case MSR_K7_EVNTSEL1:
1239         case MSR_K7_EVNTSEL2:
1240         case MSR_K7_EVNTSEL3:
1241                 /*
1242                  * only support writing 0 to the performance counters for now
1243                  * to make Windows happy. Should be replaced by a real
1244                  * performance counter emulation later.
1245                  */
1246                 if (data != 0)
1247                         goto unhandled;
1248                 break;
1249         default:
1250         unhandled:
1251                 return kvm_set_msr_common(vcpu, ecx, data);
1252         }
1253         return 0;
1254 }
1255
1256 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1257 {
1258         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1259         u64 data = (svm->vmcb->save.rax & -1u)
1260                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1261         svm->next_rip = svm->vmcb->save.rip + 2;
1262         if (svm_set_msr(&svm->vcpu, ecx, data))
1263                 kvm_inject_gp(&svm->vcpu, 0);
1264         else
1265                 skip_emulated_instruction(&svm->vcpu);
1266         return 1;
1267 }
1268
1269 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1270 {
1271         if (svm->vmcb->control.exit_info_1)
1272                 return wrmsr_interception(svm, kvm_run);
1273         else
1274                 return rdmsr_interception(svm, kvm_run);
1275 }
1276
1277 static int interrupt_window_interception(struct vcpu_svm *svm,
1278                                    struct kvm_run *kvm_run)
1279 {
1280         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1281         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1282         /*
1283          * If the user space waits to inject interrupts, exit as soon as
1284          * possible
1285          */
1286         if (kvm_run->request_interrupt_window &&
1287             !svm->vcpu.arch.irq_summary) {
1288                 ++svm->vcpu.stat.irq_window_exits;
1289                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1290                 return 0;
1291         }
1292
1293         return 1;
1294 }
1295
1296 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1297                                       struct kvm_run *kvm_run) = {
1298         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1299         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1300         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1301         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1302         /* for now: */
1303         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1304         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1305         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1306         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1307         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1308         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1309         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1310         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1311         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1312         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1313         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1314         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1315         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1316         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1317         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1318         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1319         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1320         [SVM_EXIT_INTR]                         = nop_on_interception,
1321         [SVM_EXIT_NMI]                          = nop_on_interception,
1322         [SVM_EXIT_SMI]                          = nop_on_interception,
1323         [SVM_EXIT_INIT]                         = nop_on_interception,
1324         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1325         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1326         [SVM_EXIT_CPUID]                        = cpuid_interception,
1327         [SVM_EXIT_INVD]                         = emulate_on_interception,
1328         [SVM_EXIT_HLT]                          = halt_interception,
1329         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1330         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1331         [SVM_EXIT_IOIO]                         = io_interception,
1332         [SVM_EXIT_MSR]                          = msr_interception,
1333         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1334         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1335         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1336         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1337         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1338         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1339         [SVM_EXIT_STGI]                         = invalid_op_interception,
1340         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1341         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1342         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1343         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1344         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1345         [SVM_EXIT_NPF]                          = pf_interception,
1346 };
1347
1348 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1349 {
1350         struct vcpu_svm *svm = to_svm(vcpu);
1351         u32 exit_code = svm->vmcb->control.exit_code;
1352
1353         if (npt_enabled) {
1354                 int mmu_reload = 0;
1355                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1356                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1357                         mmu_reload = 1;
1358                 }
1359                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1360                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1361                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1362                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1363                                 kvm_inject_gp(vcpu, 0);
1364                                 return 1;
1365                         }
1366                 }
1367                 if (mmu_reload) {
1368                         kvm_mmu_reset_context(vcpu);
1369                         kvm_mmu_load(vcpu);
1370                 }
1371         }
1372
1373         kvm_reput_irq(svm);
1374
1375         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1376                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1377                 kvm_run->fail_entry.hardware_entry_failure_reason
1378                         = svm->vmcb->control.exit_code;
1379                 return 0;
1380         }
1381
1382         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1383             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1384             exit_code != SVM_EXIT_NPF)
1385                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1386                        "exit_code 0x%x\n",
1387                        __FUNCTION__, svm->vmcb->control.exit_int_info,
1388                        exit_code);
1389
1390         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1391             || !svm_exit_handlers[exit_code]) {
1392                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1393                 kvm_run->hw.hardware_exit_reason = exit_code;
1394                 return 0;
1395         }
1396
1397         return svm_exit_handlers[exit_code](svm, kvm_run);
1398 }
1399
1400 static void reload_tss(struct kvm_vcpu *vcpu)
1401 {
1402         int cpu = raw_smp_processor_id();
1403
1404         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1405         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1406         load_TR_desc();
1407 }
1408
1409 static void pre_svm_run(struct vcpu_svm *svm)
1410 {
1411         int cpu = raw_smp_processor_id();
1412
1413         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1414
1415         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1416         if (svm->vcpu.cpu != cpu ||
1417             svm->asid_generation != svm_data->asid_generation)
1418                 new_asid(svm, svm_data);
1419 }
1420
1421
1422 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1423 {
1424         struct vmcb_control_area *control;
1425
1426         control = &svm->vmcb->control;
1427         control->int_vector = irq;
1428         control->int_ctl &= ~V_INTR_PRIO_MASK;
1429         control->int_ctl |= V_IRQ_MASK |
1430                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1431 }
1432
1433 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1434 {
1435         struct vcpu_svm *svm = to_svm(vcpu);
1436
1437         svm_inject_irq(svm, irq);
1438 }
1439
1440 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1441 {
1442         struct vcpu_svm *svm = to_svm(vcpu);
1443         struct vmcb *vmcb = svm->vmcb;
1444         int intr_vector = -1;
1445
1446         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1447             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1448                 intr_vector = vmcb->control.exit_int_info &
1449                               SVM_EVTINJ_VEC_MASK;
1450                 vmcb->control.exit_int_info = 0;
1451                 svm_inject_irq(svm, intr_vector);
1452                 return;
1453         }
1454
1455         if (vmcb->control.int_ctl & V_IRQ_MASK)
1456                 return;
1457
1458         if (!kvm_cpu_has_interrupt(vcpu))
1459                 return;
1460
1461         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1462             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1463             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1464                 /* unable to deliver irq, set pending irq */
1465                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1466                 svm_inject_irq(svm, 0x0);
1467                 return;
1468         }
1469         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1470         intr_vector = kvm_cpu_get_interrupt(vcpu);
1471         svm_inject_irq(svm, intr_vector);
1472         kvm_timer_intr_post(vcpu, intr_vector);
1473 }
1474
1475 static void kvm_reput_irq(struct vcpu_svm *svm)
1476 {
1477         struct vmcb_control_area *control = &svm->vmcb->control;
1478
1479         if ((control->int_ctl & V_IRQ_MASK)
1480             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1481                 control->int_ctl &= ~V_IRQ_MASK;
1482                 push_irq(&svm->vcpu, control->int_vector);
1483         }
1484
1485         svm->vcpu.arch.interrupt_window_open =
1486                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1487 }
1488
1489 static void svm_do_inject_vector(struct vcpu_svm *svm)
1490 {
1491         struct kvm_vcpu *vcpu = &svm->vcpu;
1492         int word_index = __ffs(vcpu->arch.irq_summary);
1493         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1494         int irq = word_index * BITS_PER_LONG + bit_index;
1495
1496         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1497         if (!vcpu->arch.irq_pending[word_index])
1498                 clear_bit(word_index, &vcpu->arch.irq_summary);
1499         svm_inject_irq(svm, irq);
1500 }
1501
1502 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1503                                        struct kvm_run *kvm_run)
1504 {
1505         struct vcpu_svm *svm = to_svm(vcpu);
1506         struct vmcb_control_area *control = &svm->vmcb->control;
1507
1508         svm->vcpu.arch.interrupt_window_open =
1509                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1510                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1511
1512         if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1513                 /*
1514                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1515                  */
1516                 svm_do_inject_vector(svm);
1517
1518         /*
1519          * Interrupts blocked.  Wait for unblock.
1520          */
1521         if (!svm->vcpu.arch.interrupt_window_open &&
1522             (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1523                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1524          else
1525                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1526 }
1527
1528 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1529 {
1530         return 0;
1531 }
1532
1533 static void save_db_regs(unsigned long *db_regs)
1534 {
1535         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1536         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1537         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1538         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1539 }
1540
1541 static void load_db_regs(unsigned long *db_regs)
1542 {
1543         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1544         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1545         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1546         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1547 }
1548
1549 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1550 {
1551         force_new_asid(vcpu);
1552 }
1553
1554 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1555 {
1556 }
1557
1558 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1559 {
1560         struct vcpu_svm *svm = to_svm(vcpu);
1561         u16 fs_selector;
1562         u16 gs_selector;
1563         u16 ldt_selector;
1564
1565         pre_svm_run(svm);
1566
1567         save_host_msrs(vcpu);
1568         fs_selector = read_fs();
1569         gs_selector = read_gs();
1570         ldt_selector = read_ldt();
1571         svm->host_cr2 = kvm_read_cr2();
1572         svm->host_dr6 = read_dr6();
1573         svm->host_dr7 = read_dr7();
1574         svm->vmcb->save.cr2 = vcpu->arch.cr2;
1575         /* required for live migration with NPT */
1576         if (npt_enabled)
1577                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1578
1579         if (svm->vmcb->save.dr7 & 0xff) {
1580                 write_dr7(0);
1581                 save_db_regs(svm->host_db_regs);
1582                 load_db_regs(svm->db_regs);
1583         }
1584
1585         clgi();
1586
1587         local_irq_enable();
1588
1589         asm volatile (
1590 #ifdef CONFIG_X86_64
1591                 "push %%rbp; \n\t"
1592 #else
1593                 "push %%ebp; \n\t"
1594 #endif
1595
1596 #ifdef CONFIG_X86_64
1597                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1598                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1599                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1600                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1601                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1602                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1603                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1604                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1605                 "mov %c[r10](%[svm]), %%r10 \n\t"
1606                 "mov %c[r11](%[svm]), %%r11 \n\t"
1607                 "mov %c[r12](%[svm]), %%r12 \n\t"
1608                 "mov %c[r13](%[svm]), %%r13 \n\t"
1609                 "mov %c[r14](%[svm]), %%r14 \n\t"
1610                 "mov %c[r15](%[svm]), %%r15 \n\t"
1611 #else
1612                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1613                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1614                 "mov %c[rdx](%[svm]), %%edx \n\t"
1615                 "mov %c[rsi](%[svm]), %%esi \n\t"
1616                 "mov %c[rdi](%[svm]), %%edi \n\t"
1617                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1618 #endif
1619
1620 #ifdef CONFIG_X86_64
1621                 /* Enter guest mode */
1622                 "push %%rax \n\t"
1623                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1624                 SVM_VMLOAD "\n\t"
1625                 SVM_VMRUN "\n\t"
1626                 SVM_VMSAVE "\n\t"
1627                 "pop %%rax \n\t"
1628 #else
1629                 /* Enter guest mode */
1630                 "push %%eax \n\t"
1631                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1632                 SVM_VMLOAD "\n\t"
1633                 SVM_VMRUN "\n\t"
1634                 SVM_VMSAVE "\n\t"
1635                 "pop %%eax \n\t"
1636 #endif
1637
1638                 /* Save guest registers, load host registers */
1639 #ifdef CONFIG_X86_64
1640                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1641                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1642                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1643                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1644                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1645                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1646                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1647                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1648                 "mov %%r10, %c[r10](%[svm]) \n\t"
1649                 "mov %%r11, %c[r11](%[svm]) \n\t"
1650                 "mov %%r12, %c[r12](%[svm]) \n\t"
1651                 "mov %%r13, %c[r13](%[svm]) \n\t"
1652                 "mov %%r14, %c[r14](%[svm]) \n\t"
1653                 "mov %%r15, %c[r15](%[svm]) \n\t"
1654
1655                 "pop  %%rbp; \n\t"
1656 #else
1657                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1658                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1659                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1660                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1661                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1662                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1663
1664                 "pop  %%ebp; \n\t"
1665 #endif
1666                 :
1667                 : [svm]"a"(svm),
1668                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1669                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1670                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1671                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1672                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1673                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1674                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1675 #ifdef CONFIG_X86_64
1676                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1677                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1678                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1679                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1680                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1681                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1682                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1683                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1684 #endif
1685                 : "cc", "memory"
1686 #ifdef CONFIG_X86_64
1687                 , "rbx", "rcx", "rdx", "rsi", "rdi"
1688                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1689 #else
1690                 , "ebx", "ecx", "edx" , "esi", "edi"
1691 #endif
1692                 );
1693
1694         if ((svm->vmcb->save.dr7 & 0xff))
1695                 load_db_regs(svm->host_db_regs);
1696
1697         vcpu->arch.cr2 = svm->vmcb->save.cr2;
1698
1699         write_dr6(svm->host_dr6);
1700         write_dr7(svm->host_dr7);
1701         kvm_write_cr2(svm->host_cr2);
1702
1703         load_fs(fs_selector);
1704         load_gs(gs_selector);
1705         load_ldt(ldt_selector);
1706         load_host_msrs(vcpu);
1707
1708         reload_tss(vcpu);
1709
1710         local_irq_disable();
1711
1712         stgi();
1713
1714         svm->next_rip = 0;
1715 }
1716
1717 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1718 {
1719         struct vcpu_svm *svm = to_svm(vcpu);
1720
1721         if (npt_enabled) {
1722                 svm->vmcb->control.nested_cr3 = root;
1723                 force_new_asid(vcpu);
1724                 return;
1725         }
1726
1727         svm->vmcb->save.cr3 = root;
1728         force_new_asid(vcpu);
1729
1730         if (vcpu->fpu_active) {
1731                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1732                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1733                 vcpu->fpu_active = 0;
1734         }
1735 }
1736
1737 static int is_disabled(void)
1738 {
1739         u64 vm_cr;
1740
1741         rdmsrl(MSR_VM_CR, vm_cr);
1742         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1743                 return 1;
1744
1745         return 0;
1746 }
1747
1748 static void
1749 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1750 {
1751         /*
1752          * Patch in the VMMCALL instruction:
1753          */
1754         hypercall[0] = 0x0f;
1755         hypercall[1] = 0x01;
1756         hypercall[2] = 0xd9;
1757 }
1758
1759 static void svm_check_processor_compat(void *rtn)
1760 {
1761         *(int *)rtn = 0;
1762 }
1763
1764 static bool svm_cpu_has_accelerated_tpr(void)
1765 {
1766         return false;
1767 }
1768
1769 static struct kvm_x86_ops svm_x86_ops = {
1770         .cpu_has_kvm_support = has_svm,
1771         .disabled_by_bios = is_disabled,
1772         .hardware_setup = svm_hardware_setup,
1773         .hardware_unsetup = svm_hardware_unsetup,
1774         .check_processor_compatibility = svm_check_processor_compat,
1775         .hardware_enable = svm_hardware_enable,
1776         .hardware_disable = svm_hardware_disable,
1777         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1778
1779         .vcpu_create = svm_create_vcpu,
1780         .vcpu_free = svm_free_vcpu,
1781         .vcpu_reset = svm_vcpu_reset,
1782
1783         .prepare_guest_switch = svm_prepare_guest_switch,
1784         .vcpu_load = svm_vcpu_load,
1785         .vcpu_put = svm_vcpu_put,
1786         .vcpu_decache = svm_vcpu_decache,
1787
1788         .set_guest_debug = svm_guest_debug,
1789         .get_msr = svm_get_msr,
1790         .set_msr = svm_set_msr,
1791         .get_segment_base = svm_get_segment_base,
1792         .get_segment = svm_get_segment,
1793         .set_segment = svm_set_segment,
1794         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1795         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1796         .set_cr0 = svm_set_cr0,
1797         .set_cr3 = svm_set_cr3,
1798         .set_cr4 = svm_set_cr4,
1799         .set_efer = svm_set_efer,
1800         .get_idt = svm_get_idt,
1801         .set_idt = svm_set_idt,
1802         .get_gdt = svm_get_gdt,
1803         .set_gdt = svm_set_gdt,
1804         .get_dr = svm_get_dr,
1805         .set_dr = svm_set_dr,
1806         .cache_regs = svm_cache_regs,
1807         .decache_regs = svm_decache_regs,
1808         .get_rflags = svm_get_rflags,
1809         .set_rflags = svm_set_rflags,
1810
1811         .tlb_flush = svm_flush_tlb,
1812
1813         .run = svm_vcpu_run,
1814         .handle_exit = handle_exit,
1815         .skip_emulated_instruction = skip_emulated_instruction,
1816         .patch_hypercall = svm_patch_hypercall,
1817         .get_irq = svm_get_irq,
1818         .set_irq = svm_set_irq,
1819         .queue_exception = svm_queue_exception,
1820         .exception_injected = svm_exception_injected,
1821         .inject_pending_irq = svm_intr_assist,
1822         .inject_pending_vectors = do_interrupt_requests,
1823
1824         .set_tss_addr = svm_set_tss_addr,
1825 };
1826
1827 static int __init svm_init(void)
1828 {
1829         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1830                               THIS_MODULE);
1831 }
1832
1833 static void __exit svm_exit(void)
1834 {
1835         kvm_exit();
1836 }
1837
1838 module_init(svm_init)
1839 module_exit(svm_exit)