2 * Derived from arch/powerpc/kernel/iommu.c
4 * Copyright (C) IBM Corporation, 2006
5 * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
7 * Author: Jon Mason <jdmason@kudzu.us>
8 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/kernel.h>
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/string.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/init.h>
34 #include <linux/bitops.h>
35 #include <linux/pci_ids.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
38 #include <asm/proto.h>
39 #include <asm/calgary.h>
41 #include <asm/pci-direct.h>
42 #include <asm/system.h>
46 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
47 int use_calgary __read_mostly = 1;
49 int use_calgary __read_mostly = 0;
50 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
52 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
53 #define PCI_VENDOR_DEVICE_ID_CALGARY \
54 (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
56 /* we need these for register space address calculation */
57 #define START_ADDRESS 0xfe000000
58 #define CHASSIS_BASE 0
59 #define ONE_BASED_CHASSIS_NUM 1
61 /* register offsets inside the host bridge space */
62 #define CALGARY_CONFIG_REG 0x0108
63 #define PHB_CSR_OFFSET 0x0110 /* Channel Status */
64 #define PHB_PLSSR_OFFSET 0x0120
65 #define PHB_CONFIG_RW_OFFSET 0x0160
66 #define PHB_IOBASE_BAR_LOW 0x0170
67 #define PHB_IOBASE_BAR_HIGH 0x0180
68 #define PHB_MEM_1_LOW 0x0190
69 #define PHB_MEM_1_HIGH 0x01A0
70 #define PHB_IO_ADDR_SIZE 0x01B0
71 #define PHB_MEM_1_SIZE 0x01C0
72 #define PHB_MEM_ST_OFFSET 0x01D0
73 #define PHB_AER_OFFSET 0x0200
74 #define PHB_CONFIG_0_HIGH 0x0220
75 #define PHB_CONFIG_0_LOW 0x0230
76 #define PHB_CONFIG_0_END 0x0240
77 #define PHB_MEM_2_LOW 0x02B0
78 #define PHB_MEM_2_HIGH 0x02C0
79 #define PHB_MEM_2_SIZE_HIGH 0x02D0
80 #define PHB_MEM_2_SIZE_LOW 0x02E0
81 #define PHB_DOSHOLE_OFFSET 0x08E0
84 #define PHB_TCE_ENABLE 0x20000000
85 #define PHB_SLOT_DISABLE 0x1C000000
86 #define PHB_DAC_DISABLE 0x01000000
87 #define PHB_MEM2_ENABLE 0x00400000
88 #define PHB_MCSR_ENABLE 0x00100000
89 /* TAR (Table Address Register) */
90 #define TAR_SW_BITS 0x0000ffffffff800fUL
91 #define TAR_VALID 0x0000000000000008UL
92 /* CSR (Channel/DMA Status Register) */
93 #define CSR_AGENT_MASK 0xffe0ffff
94 /* CCR (Calgary Configuration Register) */
95 #define CCR_2SEC_TIMEOUT 0x000000000000000EUL
97 #define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
98 #define MAX_NUM_CHASSIS 8 /* max number of chassis */
99 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
100 #define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
101 #define PHBS_PER_CALGARY 4
103 /* register offsets in Calgary's internal register space */
104 static const unsigned long tar_offsets[] = {
111 static const unsigned long split_queue_offsets[] = {
112 0x4870 /* SPLIT QUEUE 0 */,
113 0x5870 /* SPLIT QUEUE 1 */,
114 0x6870 /* SPLIT QUEUE 2 */,
115 0x7870 /* SPLIT QUEUE 3 */
118 static const unsigned long phb_offsets[] = {
125 /* PHB debug registers */
127 static const unsigned long phb_debug_offsets[] = {
128 0x4000 /* PHB 0 DEBUG */,
129 0x5000 /* PHB 1 DEBUG */,
130 0x6000 /* PHB 2 DEBUG */,
131 0x7000 /* PHB 3 DEBUG */
135 * STUFF register for each debug PHB,
136 * byte 1 = start bus number, byte 2 = end bus number
139 #define PHB_DEBUG_STUFF_OFFSET 0x0020
141 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
142 static int translate_empty_slots __read_mostly = 0;
143 static int calgary_detected __read_mostly = 0;
145 static struct rio_table_hdr *rio_table_hdr __initdata;
146 static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata;
147 static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata;
149 struct calgary_bus_info {
151 unsigned char translation_disabled;
156 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
158 static void tce_cache_blast(struct iommu_table *tbl);
160 /* enable this to stress test the chip's TCE cache */
161 #ifdef CONFIG_IOMMU_DEBUG
162 int debugging __read_mostly = 1;
164 static inline unsigned long verify_bit_range(unsigned long* bitmap,
165 int expected, unsigned long start, unsigned long end)
167 unsigned long idx = start;
169 BUG_ON(start >= end);
172 if (!!test_bit(idx, bitmap) != expected)
177 /* all bits have the expected value */
180 #else /* debugging is disabled */
181 int debugging __read_mostly = 0;
183 static inline unsigned long verify_bit_range(unsigned long* bitmap,
184 int expected, unsigned long start, unsigned long end)
188 #endif /* CONFIG_IOMMU_DEBUG */
190 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
194 npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
195 npages >>= PAGE_SHIFT;
200 static inline int translate_phb(struct pci_dev* dev)
202 int disabled = bus_info[dev->bus->number].translation_disabled;
206 static void iommu_range_reserve(struct iommu_table *tbl,
207 unsigned long start_addr, unsigned int npages)
211 unsigned long badbit;
213 index = start_addr >> PAGE_SHIFT;
215 /* bail out if we're asked to reserve a region we don't cover */
216 if (index >= tbl->it_size)
219 end = index + npages;
220 if (end > tbl->it_size) /* don't go off the table */
223 badbit = verify_bit_range(tbl->it_map, 0, index, end);
224 if (badbit != ~0UL) {
225 if (printk_ratelimit())
226 printk(KERN_ERR "Calgary: entry already allocated at "
227 "0x%lx tbl %p dma 0x%lx npages %u\n",
228 badbit, tbl, start_addr, npages);
231 set_bit_string(tbl->it_map, index, npages);
234 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
237 unsigned long offset;
241 offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
242 tbl->it_size, npages);
243 if (offset == ~0UL) {
244 tce_cache_blast(tbl);
245 offset = find_next_zero_string(tbl->it_map, 0,
246 tbl->it_size, npages);
247 if (offset == ~0UL) {
248 printk(KERN_WARNING "Calgary: IOMMU full.\n");
249 if (panic_on_overflow)
250 panic("Calgary: fix the allocator.\n");
252 return bad_dma_address;
256 set_bit_string(tbl->it_map, offset, npages);
257 tbl->it_hint = offset + npages;
258 BUG_ON(tbl->it_hint > tbl->it_size);
263 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
264 unsigned int npages, int direction)
266 unsigned long entry, flags;
267 dma_addr_t ret = bad_dma_address;
269 spin_lock_irqsave(&tbl->it_lock, flags);
271 entry = iommu_range_alloc(tbl, npages);
273 if (unlikely(entry == bad_dma_address))
276 /* set the return dma address */
277 ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
279 /* put the TCEs in the HW table */
280 tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
283 spin_unlock_irqrestore(&tbl->it_lock, flags);
288 spin_unlock_irqrestore(&tbl->it_lock, flags);
289 printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
290 "iommu %p\n", npages, tbl);
291 return bad_dma_address;
294 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
298 unsigned long badbit;
300 entry = dma_addr >> PAGE_SHIFT;
302 BUG_ON(entry + npages > tbl->it_size);
304 tce_free(tbl, entry, npages);
306 badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
307 if (badbit != ~0UL) {
308 if (printk_ratelimit())
309 printk(KERN_ERR "Calgary: bit is off at 0x%lx "
310 "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
311 badbit, tbl, dma_addr, entry, npages);
314 __clear_bit_string(tbl->it_map, entry, npages);
317 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
322 spin_lock_irqsave(&tbl->it_lock, flags);
324 __iommu_free(tbl, dma_addr, npages);
326 spin_unlock_irqrestore(&tbl->it_lock, flags);
329 static void __calgary_unmap_sg(struct iommu_table *tbl,
330 struct scatterlist *sglist, int nelems, int direction)
334 dma_addr_t dma = sglist->dma_address;
335 unsigned int dmalen = sglist->dma_length;
340 npages = num_dma_pages(dma, dmalen);
341 __iommu_free(tbl, dma, npages);
346 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
347 int nelems, int direction)
350 struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
352 if (!translate_phb(to_pci_dev(dev)))
355 spin_lock_irqsave(&tbl->it_lock, flags);
357 __calgary_unmap_sg(tbl, sglist, nelems, direction);
359 spin_unlock_irqrestore(&tbl->it_lock, flags);
362 static int calgary_nontranslate_map_sg(struct device* dev,
363 struct scatterlist *sg, int nelems, int direction)
367 for (i = 0; i < nelems; i++ ) {
368 struct scatterlist *s = &sg[i];
370 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
371 s->dma_length = s->length;
376 int calgary_map_sg(struct device *dev, struct scatterlist *sg,
377 int nelems, int direction)
379 struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
386 if (!translate_phb(to_pci_dev(dev)))
387 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
389 spin_lock_irqsave(&tbl->it_lock, flags);
391 for (i = 0; i < nelems; i++ ) {
392 struct scatterlist *s = &sg[i];
395 vaddr = (unsigned long)page_address(s->page) + s->offset;
396 npages = num_dma_pages(vaddr, s->length);
398 entry = iommu_range_alloc(tbl, npages);
399 if (entry == bad_dma_address) {
400 /* makes sure unmap knows to stop */
405 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
407 /* insert into HW table */
408 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
411 s->dma_length = s->length;
414 spin_unlock_irqrestore(&tbl->it_lock, flags);
418 __calgary_unmap_sg(tbl, sg, nelems, direction);
419 for (i = 0; i < nelems; i++) {
420 sg[i].dma_address = bad_dma_address;
421 sg[i].dma_length = 0;
423 spin_unlock_irqrestore(&tbl->it_lock, flags);
427 dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
428 size_t size, int direction)
430 dma_addr_t dma_handle = bad_dma_address;
433 struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
435 uaddr = (unsigned long)vaddr;
436 npages = num_dma_pages(uaddr, size);
438 if (translate_phb(to_pci_dev(dev)))
439 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
441 dma_handle = virt_to_bus(vaddr);
446 void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
447 size_t size, int direction)
449 struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
452 if (!translate_phb(to_pci_dev(dev)))
455 npages = num_dma_pages(dma_handle, size);
456 iommu_free(tbl, dma_handle, npages);
459 void* calgary_alloc_coherent(struct device *dev, size_t size,
460 dma_addr_t *dma_handle, gfp_t flag)
464 unsigned int npages, order;
465 struct iommu_table *tbl;
467 tbl = to_pci_dev(dev)->bus->self->sysdata;
469 size = PAGE_ALIGN(size); /* size rounded up to full pages */
470 npages = size >> PAGE_SHIFT;
471 order = get_order(size);
473 /* alloc enough pages (and possibly more) */
474 ret = (void *)__get_free_pages(flag, order);
477 memset(ret, 0, size);
479 if (translate_phb(to_pci_dev(dev))) {
480 /* set up tces to cover the allocated range */
481 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
482 if (mapping == bad_dma_address)
485 *dma_handle = mapping;
486 } else /* non translated slot */
487 *dma_handle = virt_to_bus(ret);
492 free_pages((unsigned long)ret, get_order(size));
498 static struct dma_mapping_ops calgary_dma_ops = {
499 .alloc_coherent = calgary_alloc_coherent,
500 .map_single = calgary_map_single,
501 .unmap_single = calgary_unmap_single,
502 .map_sg = calgary_map_sg,
503 .unmap_sg = calgary_unmap_sg,
506 static inline void __iomem * busno_to_bbar(unsigned char num)
508 return bus_info[num].bbar;
511 static inline int busno_to_phbid(unsigned char num)
513 return bus_info[num].phbid;
516 static inline unsigned long split_queue_offset(unsigned char num)
518 size_t idx = busno_to_phbid(num);
520 return split_queue_offsets[idx];
523 static inline unsigned long tar_offset(unsigned char num)
525 size_t idx = busno_to_phbid(num);
527 return tar_offsets[idx];
530 static inline unsigned long phb_offset(unsigned char num)
532 size_t idx = busno_to_phbid(num);
534 return phb_offsets[idx];
537 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
539 unsigned long target = ((unsigned long)bar) | offset;
540 return (void __iomem*)target;
543 static void tce_cache_blast(struct iommu_table *tbl)
548 void __iomem *bbar = tbl->bbar;
549 void __iomem *target;
551 /* disable arbitration on the bus */
552 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
556 /* read plssr to ensure it got there */
557 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
560 /* poll split queues until all DMA activity is done */
561 target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
565 } while ((val & 0xff) != 0xff && i < 100);
567 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
568 "continuing anyway\n");
570 /* invalidate TCE cache */
571 target = calgary_reg(bbar, tar_offset(tbl->it_busno));
572 writeq(tbl->tar_val, target);
574 /* enable arbitration */
575 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
577 (void)readl(target); /* flush */
580 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
583 unsigned int numpages;
585 limit = limit | 0xfffff;
588 numpages = ((limit - start) >> PAGE_SHIFT);
589 iommu_range_reserve(dev->sysdata, start, numpages);
592 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
594 void __iomem *target;
595 u64 low, high, sizelow;
597 struct iommu_table *tbl = dev->sysdata;
598 unsigned char busnum = dev->bus->number;
599 void __iomem *bbar = tbl->bbar;
601 /* peripheral MEM_1 region */
602 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
603 low = be32_to_cpu(readl(target));
604 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
605 high = be32_to_cpu(readl(target));
606 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
607 sizelow = be32_to_cpu(readl(target));
609 start = (high << 32) | low;
612 calgary_reserve_mem_region(dev, start, limit);
615 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
617 void __iomem *target;
619 u64 low, high, sizelow, sizehigh;
621 struct iommu_table *tbl = dev->sysdata;
622 unsigned char busnum = dev->bus->number;
623 void __iomem *bbar = tbl->bbar;
626 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
627 val32 = be32_to_cpu(readl(target));
628 if (!(val32 & PHB_MEM2_ENABLE))
631 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
632 low = be32_to_cpu(readl(target));
633 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
634 high = be32_to_cpu(readl(target));
635 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
636 sizelow = be32_to_cpu(readl(target));
637 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
638 sizehigh = be32_to_cpu(readl(target));
640 start = (high << 32) | low;
641 limit = (sizehigh << 32) | sizelow;
643 calgary_reserve_mem_region(dev, start, limit);
647 * some regions of the IO address space do not get translated, so we
648 * must not give devices IO addresses in those regions. The regions
649 * are the 640KB-1MB region and the two PCI peripheral memory holes.
650 * Reserve all of them in the IOMMU bitmap to avoid giving them out
653 static void __init calgary_reserve_regions(struct pci_dev *dev)
657 struct iommu_table *tbl = dev->sysdata;
659 /* reserve bad_dma_address in case it's a legal address */
660 iommu_range_reserve(tbl, bad_dma_address, 1);
662 /* avoid the BIOS/VGA first 640KB-1MB region */
663 start = (640 * 1024);
664 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
665 iommu_range_reserve(tbl, start, npages);
667 /* reserve the two PCI peripheral memory regions in IO space */
668 calgary_reserve_peripheral_mem_1(dev);
669 calgary_reserve_peripheral_mem_2(dev);
672 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
676 void __iomem *target;
678 struct iommu_table *tbl;
680 /* build TCE tables for each PHB */
681 ret = build_tce_table(dev, bbar);
686 tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
687 tce_free(tbl, 0, tbl->it_size);
689 calgary_reserve_regions(dev);
691 /* set TARs for each PHB */
692 target = calgary_reg(bbar, tar_offset(dev->bus->number));
693 val64 = be64_to_cpu(readq(target));
695 /* zero out all TAR bits under sw control */
696 val64 &= ~TAR_SW_BITS;
699 table_phys = (u64)__pa(tbl->it_base);
702 BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
703 val64 |= (u64) specified_table_size;
705 tbl->tar_val = cpu_to_be64(val64);
706 writeq(tbl->tar_val, target);
707 readq(target); /* flush */
712 static void __init calgary_free_bus(struct pci_dev *dev)
715 struct iommu_table *tbl = dev->sysdata;
716 void __iomem *target;
717 unsigned int bitmapsz;
719 target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
720 val64 = be64_to_cpu(readq(target));
721 val64 &= ~TAR_SW_BITS;
722 writeq(cpu_to_be64(val64), target);
723 readq(target); /* flush */
725 bitmapsz = tbl->it_size / BITS_PER_BYTE;
726 free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
732 /* Can't free bootmem allocated memory after system is up :-( */
733 bus_info[dev->bus->number].tce_space = NULL;
736 static void calgary_watchdog(unsigned long data)
738 struct pci_dev *dev = (struct pci_dev *)data;
739 struct iommu_table *tbl = dev->sysdata;
740 void __iomem *bbar = tbl->bbar;
742 void __iomem *target;
744 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
745 val32 = be32_to_cpu(readl(target));
747 /* If no error, the agent ID in the CSR is not valid */
748 if (val32 & CSR_AGENT_MASK) {
749 printk(KERN_EMERG "calgary_watchdog: DMA error on PHB %#x, "
750 "CSR = %#x\n", dev->bus->number, val32);
753 /* Disable bus that caused the error */
754 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
755 PHB_CONFIG_RW_OFFSET);
756 val32 = be32_to_cpu(readl(target));
757 val32 |= PHB_SLOT_DISABLE;
758 writel(cpu_to_be32(val32), target);
759 readl(target); /* flush */
761 /* Reset the timer */
762 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
766 static void __init calgary_increase_split_completion_timeout(void __iomem *bbar,
767 unsigned char busnum)
770 void __iomem *target;
771 unsigned int phb_shift = ~0; /* silence gcc */
774 switch (busno_to_phbid(busnum)) {
775 case 0: phb_shift = (63 - 19);
777 case 1: phb_shift = (63 - 23);
779 case 2: phb_shift = (63 - 27);
781 case 3: phb_shift = (63 - 35);
784 BUG_ON(busno_to_phbid(busnum));
787 target = calgary_reg(bbar, CALGARY_CONFIG_REG);
788 val64 = be64_to_cpu(readq(target));
790 /* zero out this PHB's timer bits */
791 mask = ~(0xFUL << phb_shift);
793 val64 |= (CCR_2SEC_TIMEOUT << phb_shift);
794 writeq(cpu_to_be64(val64), target);
795 readq(target); /* flush */
798 static void __init calgary_enable_translation(struct pci_dev *dev)
801 unsigned char busnum;
802 void __iomem *target;
804 struct iommu_table *tbl;
806 busnum = dev->bus->number;
810 /* enable TCE in PHB Config Register */
811 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
812 val32 = be32_to_cpu(readl(target));
813 val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
815 printk(KERN_INFO "Calgary: enabling translation on PHB %#x\n", busnum);
816 printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
819 writel(cpu_to_be32(val32), target);
820 readl(target); /* flush */
823 * Give split completion a longer timeout on bus 1 for aic94xx
824 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
827 calgary_increase_split_completion_timeout(bbar, busnum);
829 init_timer(&tbl->watchdog_timer);
830 tbl->watchdog_timer.function = &calgary_watchdog;
831 tbl->watchdog_timer.data = (unsigned long)dev;
832 mod_timer(&tbl->watchdog_timer, jiffies);
835 static void __init calgary_disable_translation(struct pci_dev *dev)
838 unsigned char busnum;
839 void __iomem *target;
841 struct iommu_table *tbl;
843 busnum = dev->bus->number;
847 /* disable TCE in PHB Config Register */
848 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
849 val32 = be32_to_cpu(readl(target));
850 val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
852 printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
853 writel(cpu_to_be32(val32), target);
854 readl(target); /* flush */
856 del_timer_sync(&tbl->watchdog_timer);
859 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
863 dev->bus->self = dev;
866 static int __init calgary_init_one(struct pci_dev *dev)
871 BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
873 bbar = busno_to_bbar(dev->bus->number);
874 ret = calgary_setup_tar(dev, bbar);
879 dev->bus->self = dev;
880 calgary_enable_translation(dev);
888 static int __init calgary_locate_bbars(void)
891 int rioidx, phb, bus;
893 void __iomem *target;
894 unsigned long offset;
895 u8 start_bus, end_bus;
899 for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
900 struct rio_detail *rio = rio_devs[rioidx];
902 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
905 /* map entire 1MB of Calgary config space */
906 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
910 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
911 offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
912 target = calgary_reg(bbar, offset);
914 val = be32_to_cpu(readl(target));
915 start_bus = (u8)((val & 0x00FF0000) >> 16);
916 end_bus = (u8)((val & 0x0000FF00) >> 8);
917 for (bus = start_bus; bus <= end_bus; bus++) {
918 bus_info[bus].bbar = bbar;
919 bus_info[bus].phbid = phb;
927 /* scan bus_info and iounmap any bbars we previously ioremap'd */
928 for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
929 if (bus_info[bus].bbar)
930 iounmap(bus_info[bus].bbar);
935 static int __init calgary_init(void)
938 struct pci_dev *dev = NULL;
940 ret = calgary_locate_bbars();
945 dev = pci_get_device(PCI_VENDOR_ID_IBM,
946 PCI_DEVICE_ID_IBM_CALGARY,
950 if (!translate_phb(dev)) {
951 calgary_init_one_nontraslated(dev);
954 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
957 ret = calgary_init_one(dev);
966 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
967 PCI_DEVICE_ID_IBM_CALGARY,
971 if (!translate_phb(dev)) {
975 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
978 calgary_disable_translation(dev);
979 calgary_free_bus(dev);
980 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
986 static inline int __init determine_tce_table_size(u64 ram)
990 if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
991 return specified_table_size;
994 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
995 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
996 * larger table size has twice as many entries, so shift the
997 * max ram address by 13 to divide by 8K and then look at the
998 * order of the result to choose between 0-7.
1000 ret = get_order(ram >> 13);
1001 if (ret > TCE_TABLE_SIZE_8M)
1002 ret = TCE_TABLE_SIZE_8M;
1007 static int __init build_detail_arrays(void)
1010 int i, scal_detail_size, rio_detail_size;
1012 if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1014 "Calgary: MAX_NUMNODES too low! Defined as %d, "
1015 "but system has %d nodes.\n",
1016 MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1020 switch (rio_table_hdr->version){
1022 scal_detail_size = 11;
1023 rio_detail_size = 13;
1026 scal_detail_size = 12;
1027 rio_detail_size = 15;
1031 "Calgary: Invalid Rio Grande Table Version: %d\n",
1032 rio_table_hdr->version);
1036 ptr = ((unsigned long)rio_table_hdr) + 3;
1037 for (i = 0; i < rio_table_hdr->num_scal_dev;
1038 i++, ptr += scal_detail_size)
1039 scal_devs[i] = (struct scal_detail *)ptr;
1041 for (i = 0; i < rio_table_hdr->num_rio_dev;
1042 i++, ptr += rio_detail_size)
1043 rio_devs[i] = (struct rio_detail *)ptr;
1048 void __init detect_calgary(void)
1053 int calgary_found = 0;
1059 * if the user specified iommu=off or iommu=soft or we found
1060 * another HW IOMMU already, bail out.
1062 if (swiotlb || no_iommu || iommu_detected)
1068 if (!early_pci_allowed())
1071 ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1073 rio_table_hdr = NULL;
1076 /* The block id is stored in the 2nd word */
1077 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1078 /* set the pointer past the offset & block id */
1079 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1082 /* The next offset is stored in the 1st word. 0 means no more */
1083 offset = *((unsigned short *)(ptr + offset));
1085 if (!rio_table_hdr) {
1086 printk(KERN_ERR "Calgary: Unable to locate "
1087 "Rio Grande Table in EBDA - bailing!\n");
1091 ret = build_detail_arrays();
1093 printk(KERN_ERR "Calgary: build_detail_arrays ret %d\n", ret);
1097 specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1099 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1101 struct calgary_bus_info *info = &bus_info[bus];
1103 if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY)
1106 if (info->translation_disabled)
1110 * Scan the slots of the PCI bus to see if there is a device present.
1111 * The parent bus will be the zero-ith device, so start at 1.
1113 for (dev = 1; dev < 8; dev++) {
1114 val = read_pci_config(bus, dev, 0, 0);
1115 if (val != 0xffffffff || translate_empty_slots) {
1116 tbl = alloc_tce_table();
1119 info->tce_space = tbl;
1126 if (calgary_found) {
1128 calgary_detected = 1;
1129 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1130 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1131 "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1132 debugging ? "enabled" : "disabled");
1137 for (--bus; bus >= 0; --bus) {
1138 struct calgary_bus_info *info = &bus_info[bus];
1140 if (info->tce_space)
1141 free_tce_table(info->tce_space);
1145 int __init calgary_iommu_init(void)
1149 if (no_iommu || swiotlb)
1152 if (!calgary_detected)
1155 /* ok, we're trying to use Calgary - let's roll */
1156 printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1158 ret = calgary_init();
1160 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1161 "falling back to no_iommu\n", ret);
1162 if (end_pfn > MAX_DMA32_PFN)
1163 printk(KERN_ERR "WARNING more than 4GB of memory, "
1164 "32bit PCI may malfunction.\n");
1169 dma_ops = &calgary_dma_ops;
1174 static int __init calgary_parse_options(char *p)
1176 unsigned int bridge;
1181 if (!strncmp(p, "64k", 3))
1182 specified_table_size = TCE_TABLE_SIZE_64K;
1183 else if (!strncmp(p, "128k", 4))
1184 specified_table_size = TCE_TABLE_SIZE_128K;
1185 else if (!strncmp(p, "256k", 4))
1186 specified_table_size = TCE_TABLE_SIZE_256K;
1187 else if (!strncmp(p, "512k", 4))
1188 specified_table_size = TCE_TABLE_SIZE_512K;
1189 else if (!strncmp(p, "1M", 2))
1190 specified_table_size = TCE_TABLE_SIZE_1M;
1191 else if (!strncmp(p, "2M", 2))
1192 specified_table_size = TCE_TABLE_SIZE_2M;
1193 else if (!strncmp(p, "4M", 2))
1194 specified_table_size = TCE_TABLE_SIZE_4M;
1195 else if (!strncmp(p, "8M", 2))
1196 specified_table_size = TCE_TABLE_SIZE_8M;
1198 len = strlen("translate_empty_slots");
1199 if (!strncmp(p, "translate_empty_slots", len))
1200 translate_empty_slots = 1;
1202 len = strlen("disable");
1203 if (!strncmp(p, "disable", len)) {
1209 bridge = simple_strtol(p, &endp, 0);
1213 if (bridge < MAX_PHB_BUS_NUM) {
1214 printk(KERN_INFO "Calgary: disabling "
1215 "translation for PHB %#x\n", bridge);
1216 bus_info[bridge].translation_disabled = 1;
1220 p = strpbrk(p, ",");
1228 __setup("calgary=", calgary_parse_options);