2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "3.0"
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 1,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
80 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
100 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
101 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
102 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
103 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
104 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
106 /* registers for each SATA port */
107 PORT_LST_ADDR = 0x00, /* command list DMA addr */
108 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
109 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
110 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
111 PORT_IRQ_STAT = 0x10, /* interrupt status */
112 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
113 PORT_CMD = 0x18, /* port command */
114 PORT_TFDATA = 0x20, /* taskfile data */
115 PORT_SIG = 0x24, /* device TF signature */
116 PORT_CMD_ISSUE = 0x38, /* command issue */
117 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
118 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
119 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
120 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
121 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
123 /* PORT_IRQ_{STAT,MASK} bits */
124 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
125 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
126 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
127 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
128 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
129 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
130 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
131 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
133 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
134 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
135 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
136 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
137 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
138 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
139 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
140 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
141 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
143 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
149 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
151 PORT_IRQ_HBUS_DATA_ERR,
152 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
153 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
154 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
157 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
158 PORT_CMD_PMP = (1 << 17), /* PMP attached */
159 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
160 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
161 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
162 PORT_CMD_CLO = (1 << 3), /* Command list override */
163 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
164 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
165 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
167 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
168 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
169 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
170 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
172 /* hpriv->flags bits */
173 AHCI_HFLAG_NO_NCQ = (1 << 0),
174 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
175 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
176 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
177 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
178 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
181 AHCI_FLAG_NO_HOTPLUG = (1 << 24), /* ignore PxSERR.DIAG.N */
183 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
184 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
185 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
186 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
189 struct ahci_cmd_hdr {
204 struct ahci_host_priv {
205 unsigned int flags; /* AHCI_HFLAG_* */
206 u32 cap; /* cap to use */
207 u32 port_map; /* port map to use */
208 u32 saved_cap; /* saved initial cap */
209 u32 saved_port_map; /* saved initial port_map */
212 struct ahci_port_priv {
213 struct ata_link *active_link;
214 struct ahci_cmd_hdr *cmd_slot;
215 dma_addr_t cmd_slot_dma;
217 dma_addr_t cmd_tbl_dma;
219 dma_addr_t rx_fis_dma;
220 /* for NCQ spurious interrupt analysis */
221 unsigned int ncq_saw_d2h:1;
222 unsigned int ncq_saw_dmas:1;
223 unsigned int ncq_saw_sdb:1;
224 u32 intr_mask; /* interrupts to enable */
227 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
228 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
229 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
230 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
231 static void ahci_irq_clear(struct ata_port *ap);
232 static int ahci_port_start(struct ata_port *ap);
233 static void ahci_port_stop(struct ata_port *ap);
234 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
235 static void ahci_qc_prep(struct ata_queued_cmd *qc);
236 static u8 ahci_check_status(struct ata_port *ap);
237 static void ahci_freeze(struct ata_port *ap);
238 static void ahci_thaw(struct ata_port *ap);
239 static void ahci_pmp_attach(struct ata_port *ap);
240 static void ahci_pmp_detach(struct ata_port *ap);
241 static int ahci_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val);
242 static int ahci_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val);
243 static void ahci_error_handler(struct ata_port *ap);
244 static void ahci_vt8251_error_handler(struct ata_port *ap);
245 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
246 static int ahci_port_resume(struct ata_port *ap);
247 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
248 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
251 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
252 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
253 static int ahci_pci_device_resume(struct pci_dev *pdev);
256 static struct scsi_host_template ahci_sht = {
257 .module = THIS_MODULE,
259 .ioctl = ata_scsi_ioctl,
260 .queuecommand = ata_scsi_queuecmd,
261 .change_queue_depth = ata_scsi_change_queue_depth,
262 .can_queue = AHCI_MAX_CMDS - 1,
263 .this_id = ATA_SHT_THIS_ID,
264 .sg_tablesize = AHCI_MAX_SG,
265 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
266 .emulated = ATA_SHT_EMULATED,
267 .use_clustering = AHCI_USE_CLUSTERING,
268 .proc_name = DRV_NAME,
269 .dma_boundary = AHCI_DMA_BOUNDARY,
270 .slave_configure = ata_scsi_slave_config,
271 .slave_destroy = ata_scsi_slave_destroy,
272 .bios_param = ata_std_bios_param,
275 static const struct ata_port_operations ahci_ops = {
276 .check_status = ahci_check_status,
277 .check_altstatus = ahci_check_status,
278 .dev_select = ata_noop_dev_select,
280 .tf_read = ahci_tf_read,
282 .qc_defer = sata_pmp_qc_defer_cmd_switch,
283 .qc_prep = ahci_qc_prep,
284 .qc_issue = ahci_qc_issue,
286 .irq_clear = ahci_irq_clear,
288 .scr_read = ahci_scr_read,
289 .scr_write = ahci_scr_write,
291 .freeze = ahci_freeze,
294 .error_handler = ahci_error_handler,
295 .post_internal_cmd = ahci_post_internal_cmd,
297 .pmp_attach = ahci_pmp_attach,
298 .pmp_detach = ahci_pmp_detach,
299 .pmp_read = ahci_pmp_read,
300 .pmp_write = ahci_pmp_write,
303 .port_suspend = ahci_port_suspend,
304 .port_resume = ahci_port_resume,
307 .port_start = ahci_port_start,
308 .port_stop = ahci_port_stop,
311 static const struct ata_port_operations ahci_vt8251_ops = {
312 .check_status = ahci_check_status,
313 .check_altstatus = ahci_check_status,
314 .dev_select = ata_noop_dev_select,
316 .tf_read = ahci_tf_read,
318 .qc_defer = sata_pmp_qc_defer_cmd_switch,
319 .qc_prep = ahci_qc_prep,
320 .qc_issue = ahci_qc_issue,
322 .irq_clear = ahci_irq_clear,
324 .scr_read = ahci_scr_read,
325 .scr_write = ahci_scr_write,
327 .freeze = ahci_freeze,
330 .error_handler = ahci_vt8251_error_handler,
331 .post_internal_cmd = ahci_post_internal_cmd,
333 .pmp_attach = ahci_pmp_attach,
334 .pmp_detach = ahci_pmp_detach,
335 .pmp_read = ahci_pmp_read,
336 .pmp_write = ahci_pmp_write,
339 .port_suspend = ahci_port_suspend,
340 .port_resume = ahci_port_resume,
343 .port_start = ahci_port_start,
344 .port_stop = ahci_port_stop,
347 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
349 static const struct ata_port_info ahci_port_info[] = {
352 .flags = AHCI_FLAG_COMMON,
353 .link_flags = AHCI_LFLAG_COMMON,
354 .pio_mask = 0x1f, /* pio0-4 */
355 .udma_mask = ATA_UDMA6,
356 .port_ops = &ahci_ops,
358 /* board_ahci_vt8251 */
360 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
361 .flags = AHCI_FLAG_COMMON,
362 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
363 .pio_mask = 0x1f, /* pio0-4 */
364 .udma_mask = ATA_UDMA6,
365 .port_ops = &ahci_vt8251_ops,
367 /* board_ahci_ign_iferr */
369 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
370 .flags = AHCI_FLAG_COMMON,
371 .link_flags = AHCI_LFLAG_COMMON,
372 .pio_mask = 0x1f, /* pio0-4 */
373 .udma_mask = ATA_UDMA6,
374 .port_ops = &ahci_ops,
376 /* board_ahci_sb600 */
378 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
379 AHCI_HFLAG_32BIT_ONLY),
380 .flags = AHCI_FLAG_COMMON,
381 .link_flags = AHCI_LFLAG_COMMON,
382 .pio_mask = 0x1f, /* pio0-4 */
383 .udma_mask = ATA_UDMA6,
384 .port_ops = &ahci_ops,
388 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
390 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
391 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
392 .link_flags = AHCI_LFLAG_COMMON,
393 .pio_mask = 0x1f, /* pio0-4 */
394 .udma_mask = ATA_UDMA6,
395 .port_ops = &ahci_ops,
399 static const struct pci_device_id ahci_pci_tbl[] = {
401 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
402 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
403 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
404 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
405 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
406 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
407 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
408 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
409 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
410 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
411 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
412 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
413 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
414 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
415 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
416 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
417 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
418 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
419 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
420 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
421 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
422 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
423 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
424 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
425 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
426 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
427 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
428 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
429 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
431 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
432 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
433 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
436 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
437 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
438 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
439 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
440 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
441 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
442 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
445 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
446 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
449 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
450 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
451 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
452 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
453 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
454 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
455 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
456 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
457 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
458 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
459 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
460 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
461 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
462 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
463 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
464 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
465 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
466 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
467 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
468 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
469 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
470 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
471 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
472 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
473 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
474 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
475 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
476 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
477 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
478 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
479 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
480 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
481 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
482 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
483 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
484 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
485 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
486 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
487 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
488 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
489 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
490 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
491 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
492 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
495 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
496 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
497 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
500 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
502 /* Generic, PCI class code for AHCI */
503 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
504 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
506 { } /* terminate list */
510 static struct pci_driver ahci_pci_driver = {
512 .id_table = ahci_pci_tbl,
513 .probe = ahci_init_one,
514 .remove = ata_pci_remove_one,
516 .suspend = ahci_pci_device_suspend,
517 .resume = ahci_pci_device_resume,
522 static inline int ahci_nr_ports(u32 cap)
524 return (cap & 0x1f) + 1;
527 static inline void __iomem *__ahci_port_base(struct ata_host *host,
528 unsigned int port_no)
530 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
532 return mmio + 0x100 + (port_no * 0x80);
535 static inline void __iomem *ahci_port_base(struct ata_port *ap)
537 return __ahci_port_base(ap->host, ap->port_no);
541 * ahci_save_initial_config - Save and fixup initial config values
542 * @pdev: target PCI device
543 * @hpriv: host private area to store config values
545 * Some registers containing configuration info might be setup by
546 * BIOS and might be cleared on reset. This function saves the
547 * initial values of those registers into @hpriv such that they
548 * can be restored after controller reset.
550 * If inconsistent, config values are fixed up by this function.
555 static void ahci_save_initial_config(struct pci_dev *pdev,
556 struct ahci_host_priv *hpriv)
558 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
562 /* Values prefixed with saved_ are written back to host after
563 * reset. Values without are used for driver operation.
565 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
566 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
568 /* some chips have errata preventing 64bit use */
569 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
570 dev_printk(KERN_INFO, &pdev->dev,
571 "controller can't do 64bit DMA, forcing 32bit\n");
575 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
576 dev_printk(KERN_INFO, &pdev->dev,
577 "controller can't do NCQ, turning off CAP_NCQ\n");
578 cap &= ~HOST_CAP_NCQ;
582 * Temporary Marvell 6145 hack: PATA port presence
583 * is asserted through the standard AHCI port
584 * presence register, as bit 4 (counting from 0)
586 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
587 dev_printk(KERN_ERR, &pdev->dev,
588 "MV_AHCI HACK: port_map %x -> %x\n",
590 hpriv->port_map & 0xf);
595 /* cross check port_map and cap.n_ports */
597 u32 tmp_port_map = port_map;
598 int n_ports = ahci_nr_ports(cap);
600 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
601 if (tmp_port_map & (1 << i)) {
603 tmp_port_map &= ~(1 << i);
607 /* If n_ports and port_map are inconsistent, whine and
608 * clear port_map and let it be generated from n_ports.
610 if (n_ports || tmp_port_map) {
611 dev_printk(KERN_WARNING, &pdev->dev,
612 "nr_ports (%u) and implemented port map "
613 "(0x%x) don't match, using nr_ports\n",
614 ahci_nr_ports(cap), port_map);
619 /* fabricate port_map from cap.nr_ports */
621 port_map = (1 << ahci_nr_ports(cap)) - 1;
622 dev_printk(KERN_WARNING, &pdev->dev,
623 "forcing PORTS_IMPL to 0x%x\n", port_map);
625 /* write the fixed up value to the PI register */
626 hpriv->saved_port_map = port_map;
629 /* record values to use during operation */
631 hpriv->port_map = port_map;
635 * ahci_restore_initial_config - Restore initial config
636 * @host: target ATA host
638 * Restore initial config stored by ahci_save_initial_config().
643 static void ahci_restore_initial_config(struct ata_host *host)
645 struct ahci_host_priv *hpriv = host->private_data;
646 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
648 writel(hpriv->saved_cap, mmio + HOST_CAP);
649 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
650 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
653 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
655 static const int offset[] = {
656 [SCR_STATUS] = PORT_SCR_STAT,
657 [SCR_CONTROL] = PORT_SCR_CTL,
658 [SCR_ERROR] = PORT_SCR_ERR,
659 [SCR_ACTIVE] = PORT_SCR_ACT,
660 [SCR_NOTIFICATION] = PORT_SCR_NTF,
662 struct ahci_host_priv *hpriv = ap->host->private_data;
664 if (sc_reg < ARRAY_SIZE(offset) &&
665 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
666 return offset[sc_reg];
670 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
672 void __iomem *port_mmio = ahci_port_base(ap);
673 int offset = ahci_scr_offset(ap, sc_reg);
676 *val = readl(port_mmio + offset);
682 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
684 void __iomem *port_mmio = ahci_port_base(ap);
685 int offset = ahci_scr_offset(ap, sc_reg);
688 writel(val, port_mmio + offset);
694 static void ahci_start_engine(struct ata_port *ap)
696 void __iomem *port_mmio = ahci_port_base(ap);
700 tmp = readl(port_mmio + PORT_CMD);
701 tmp |= PORT_CMD_START;
702 writel(tmp, port_mmio + PORT_CMD);
703 readl(port_mmio + PORT_CMD); /* flush */
706 static int ahci_stop_engine(struct ata_port *ap)
708 void __iomem *port_mmio = ahci_port_base(ap);
711 tmp = readl(port_mmio + PORT_CMD);
713 /* check if the HBA is idle */
714 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
717 /* setting HBA to idle */
718 tmp &= ~PORT_CMD_START;
719 writel(tmp, port_mmio + PORT_CMD);
721 /* wait for engine to stop. This could be as long as 500 msec */
722 tmp = ata_wait_register(port_mmio + PORT_CMD,
723 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
724 if (tmp & PORT_CMD_LIST_ON)
730 static void ahci_start_fis_rx(struct ata_port *ap)
732 void __iomem *port_mmio = ahci_port_base(ap);
733 struct ahci_host_priv *hpriv = ap->host->private_data;
734 struct ahci_port_priv *pp = ap->private_data;
737 /* set FIS registers */
738 if (hpriv->cap & HOST_CAP_64)
739 writel((pp->cmd_slot_dma >> 16) >> 16,
740 port_mmio + PORT_LST_ADDR_HI);
741 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
743 if (hpriv->cap & HOST_CAP_64)
744 writel((pp->rx_fis_dma >> 16) >> 16,
745 port_mmio + PORT_FIS_ADDR_HI);
746 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
748 /* enable FIS reception */
749 tmp = readl(port_mmio + PORT_CMD);
750 tmp |= PORT_CMD_FIS_RX;
751 writel(tmp, port_mmio + PORT_CMD);
754 readl(port_mmio + PORT_CMD);
757 static int ahci_stop_fis_rx(struct ata_port *ap)
759 void __iomem *port_mmio = ahci_port_base(ap);
762 /* disable FIS reception */
763 tmp = readl(port_mmio + PORT_CMD);
764 tmp &= ~PORT_CMD_FIS_RX;
765 writel(tmp, port_mmio + PORT_CMD);
767 /* wait for completion, spec says 500ms, give it 1000 */
768 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
769 PORT_CMD_FIS_ON, 10, 1000);
770 if (tmp & PORT_CMD_FIS_ON)
776 static void ahci_power_up(struct ata_port *ap)
778 struct ahci_host_priv *hpriv = ap->host->private_data;
779 void __iomem *port_mmio = ahci_port_base(ap);
782 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
785 if (hpriv->cap & HOST_CAP_SSS) {
786 cmd |= PORT_CMD_SPIN_UP;
787 writel(cmd, port_mmio + PORT_CMD);
791 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
795 static void ahci_power_down(struct ata_port *ap)
797 struct ahci_host_priv *hpriv = ap->host->private_data;
798 void __iomem *port_mmio = ahci_port_base(ap);
801 if (!(hpriv->cap & HOST_CAP_SSS))
804 /* put device into listen mode, first set PxSCTL.DET to 0 */
805 scontrol = readl(port_mmio + PORT_SCR_CTL);
807 writel(scontrol, port_mmio + PORT_SCR_CTL);
809 /* then set PxCMD.SUD to 0 */
810 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
811 cmd &= ~PORT_CMD_SPIN_UP;
812 writel(cmd, port_mmio + PORT_CMD);
816 static void ahci_start_port(struct ata_port *ap)
818 /* enable FIS reception */
819 ahci_start_fis_rx(ap);
822 ahci_start_engine(ap);
825 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
830 rc = ahci_stop_engine(ap);
832 *emsg = "failed to stop engine";
836 /* disable FIS reception */
837 rc = ahci_stop_fis_rx(ap);
839 *emsg = "failed stop FIS RX";
846 static int ahci_reset_controller(struct ata_host *host)
848 struct pci_dev *pdev = to_pci_dev(host->dev);
849 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
852 /* we must be in AHCI mode, before using anything
853 * AHCI-specific, such as HOST_RESET.
855 tmp = readl(mmio + HOST_CTL);
856 if (!(tmp & HOST_AHCI_EN))
857 writel(tmp | HOST_AHCI_EN, mmio + HOST_CTL);
859 /* global controller reset */
860 if ((tmp & HOST_RESET) == 0) {
861 writel(tmp | HOST_RESET, mmio + HOST_CTL);
862 readl(mmio + HOST_CTL); /* flush */
865 /* reset must complete within 1 second, or
866 * the hardware should be considered fried.
870 tmp = readl(mmio + HOST_CTL);
871 if (tmp & HOST_RESET) {
872 dev_printk(KERN_ERR, host->dev,
873 "controller reset failed (0x%x)\n", tmp);
877 /* turn on AHCI mode */
878 writel(HOST_AHCI_EN, mmio + HOST_CTL);
879 (void) readl(mmio + HOST_CTL); /* flush */
881 /* some registers might be cleared on reset. restore initial values */
882 ahci_restore_initial_config(host);
884 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
888 pci_read_config_word(pdev, 0x92, &tmp16);
890 pci_write_config_word(pdev, 0x92, tmp16);
896 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
897 int port_no, void __iomem *mmio,
898 void __iomem *port_mmio)
900 const char *emsg = NULL;
904 /* make sure port is not active */
905 rc = ahci_deinit_port(ap, &emsg);
907 dev_printk(KERN_WARNING, &pdev->dev,
908 "%s (%d)\n", emsg, rc);
911 tmp = readl(port_mmio + PORT_SCR_ERR);
912 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
913 writel(tmp, port_mmio + PORT_SCR_ERR);
916 tmp = readl(port_mmio + PORT_IRQ_STAT);
917 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
919 writel(tmp, port_mmio + PORT_IRQ_STAT);
921 writel(1 << port_no, mmio + HOST_IRQ_STAT);
924 static void ahci_init_controller(struct ata_host *host)
926 struct ahci_host_priv *hpriv = host->private_data;
927 struct pci_dev *pdev = to_pci_dev(host->dev);
928 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
930 void __iomem *port_mmio;
933 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
934 port_mmio = __ahci_port_base(host, 4);
936 writel(0, port_mmio + PORT_IRQ_MASK);
939 tmp = readl(port_mmio + PORT_IRQ_STAT);
940 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
942 writel(tmp, port_mmio + PORT_IRQ_STAT);
945 for (i = 0; i < host->n_ports; i++) {
946 struct ata_port *ap = host->ports[i];
948 port_mmio = ahci_port_base(ap);
949 if (ata_port_is_dummy(ap))
952 ahci_port_init(pdev, ap, i, mmio, port_mmio);
955 tmp = readl(mmio + HOST_CTL);
956 VPRINTK("HOST_CTL 0x%x\n", tmp);
957 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
958 tmp = readl(mmio + HOST_CTL);
959 VPRINTK("HOST_CTL 0x%x\n", tmp);
962 static unsigned int ahci_dev_classify(struct ata_port *ap)
964 void __iomem *port_mmio = ahci_port_base(ap);
965 struct ata_taskfile tf;
968 tmp = readl(port_mmio + PORT_SIG);
969 tf.lbah = (tmp >> 24) & 0xff;
970 tf.lbam = (tmp >> 16) & 0xff;
971 tf.lbal = (tmp >> 8) & 0xff;
972 tf.nsect = (tmp) & 0xff;
974 return ata_dev_classify(&tf);
977 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
980 dma_addr_t cmd_tbl_dma;
982 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
984 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
985 pp->cmd_slot[tag].status = 0;
986 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
987 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
990 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
992 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
993 struct ahci_host_priv *hpriv = ap->host->private_data;
997 /* do we need to kick the port? */
998 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
999 if (!busy && !force_restart)
1003 rc = ahci_stop_engine(ap);
1007 /* need to do CLO? */
1013 if (!(hpriv->cap & HOST_CAP_CLO)) {
1019 tmp = readl(port_mmio + PORT_CMD);
1020 tmp |= PORT_CMD_CLO;
1021 writel(tmp, port_mmio + PORT_CMD);
1024 tmp = ata_wait_register(port_mmio + PORT_CMD,
1025 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1026 if (tmp & PORT_CMD_CLO)
1029 /* restart engine */
1031 ahci_start_engine(ap);
1035 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1036 struct ata_taskfile *tf, int is_cmd, u16 flags,
1037 unsigned long timeout_msec)
1039 const u32 cmd_fis_len = 5; /* five dwords */
1040 struct ahci_port_priv *pp = ap->private_data;
1041 void __iomem *port_mmio = ahci_port_base(ap);
1042 u8 *fis = pp->cmd_tbl;
1045 /* prep the command */
1046 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1047 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1050 writel(1, port_mmio + PORT_CMD_ISSUE);
1053 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1056 ahci_kick_engine(ap, 1);
1060 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1065 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1066 int pmp, unsigned long deadline)
1068 struct ata_port *ap = link->ap;
1069 const char *reason = NULL;
1070 unsigned long now, msecs;
1071 struct ata_taskfile tf;
1076 if (ata_link_offline(link)) {
1077 DPRINTK("PHY reports no device\n");
1078 *class = ATA_DEV_NONE;
1082 /* prepare for SRST (AHCI-1.1 10.4.1) */
1083 rc = ahci_kick_engine(ap, 1);
1085 ata_link_printk(link, KERN_WARNING,
1086 "failed to reset engine (errno=%d)", rc);
1088 ata_tf_init(link->device, &tf);
1090 /* issue the first D2H Register FIS */
1093 if (time_after(now, deadline))
1094 msecs = jiffies_to_msecs(deadline - now);
1097 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1098 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1100 reason = "1st FIS failed";
1104 /* spec says at least 5us, but be generous and sleep for 1ms */
1107 /* issue the second D2H Register FIS */
1108 tf.ctl &= ~ATA_SRST;
1109 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1111 /* spec mandates ">= 2ms" before checking status.
1112 * We wait 150ms, because that was the magic delay used for
1113 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1114 * between when the ATA command register is written, and then
1115 * status is checked. Because waiting for "a while" before
1116 * checking status is fine, post SRST, we perform this magic
1117 * delay here as well.
1121 rc = ata_wait_ready(ap, deadline);
1122 /* link occupied, -ENODEV too is an error */
1124 reason = "device not ready";
1127 *class = ahci_dev_classify(ap);
1129 DPRINTK("EXIT, class=%u\n", *class);
1133 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1137 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1138 unsigned long deadline)
1142 if (link->ap->flags & ATA_FLAG_PMP)
1143 pmp = SATA_PMP_CTRL_PORT;
1145 return ahci_do_softreset(link, class, pmp, deadline);
1148 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1149 unsigned long deadline)
1151 struct ata_port *ap = link->ap;
1152 struct ahci_port_priv *pp = ap->private_data;
1153 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1154 struct ata_taskfile tf;
1159 ahci_stop_engine(ap);
1161 /* clear D2H reception area to properly wait for D2H FIS */
1162 ata_tf_init(link->device, &tf);
1164 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1166 rc = sata_std_hardreset(link, class, deadline);
1168 ahci_start_engine(ap);
1170 if (rc == 0 && ata_link_online(link))
1171 *class = ahci_dev_classify(ap);
1172 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
1173 *class = ATA_DEV_NONE;
1175 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1179 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1180 unsigned long deadline)
1182 struct ata_port *ap = link->ap;
1188 ahci_stop_engine(ap);
1190 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1193 /* vt8251 needs SError cleared for the port to operate */
1194 ahci_scr_read(ap, SCR_ERROR, &serror);
1195 ahci_scr_write(ap, SCR_ERROR, serror);
1197 ahci_start_engine(ap);
1199 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1201 /* vt8251 doesn't clear BSY on signature FIS reception,
1202 * request follow-up softreset.
1204 return rc ?: -EAGAIN;
1207 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1209 struct ata_port *ap = link->ap;
1210 void __iomem *port_mmio = ahci_port_base(ap);
1213 ata_std_postreset(link, class);
1215 /* Make sure port's ATAPI bit is set appropriately */
1216 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1217 if (*class == ATA_DEV_ATAPI)
1218 new_tmp |= PORT_CMD_ATAPI;
1220 new_tmp &= ~PORT_CMD_ATAPI;
1221 if (new_tmp != tmp) {
1222 writel(new_tmp, port_mmio + PORT_CMD);
1223 readl(port_mmio + PORT_CMD); /* flush */
1227 static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1228 unsigned long deadline)
1230 return ahci_do_softreset(link, class, link->pmp, deadline);
1233 static u8 ahci_check_status(struct ata_port *ap)
1235 void __iomem *mmio = ap->ioaddr.cmd_addr;
1237 return readl(mmio + PORT_TFDATA) & 0xFF;
1240 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1242 struct ahci_port_priv *pp = ap->private_data;
1243 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1245 ata_tf_from_fis(d2h_fis, tf);
1248 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1250 struct scatterlist *sg;
1251 struct ahci_sg *ahci_sg;
1252 unsigned int n_sg = 0;
1257 * Next, the S/G list.
1259 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1260 ata_for_each_sg(sg, qc) {
1261 dma_addr_t addr = sg_dma_address(sg);
1262 u32 sg_len = sg_dma_len(sg);
1264 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1265 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1266 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1275 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1277 struct ata_port *ap = qc->ap;
1278 struct ahci_port_priv *pp = ap->private_data;
1279 int is_atapi = is_atapi_taskfile(&qc->tf);
1282 const u32 cmd_fis_len = 5; /* five dwords */
1283 unsigned int n_elem;
1286 * Fill in command table information. First, the header,
1287 * a SATA Register - Host to Device command FIS.
1289 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1291 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1293 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1294 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1298 if (qc->flags & ATA_QCFLAG_DMAMAP)
1299 n_elem = ahci_fill_sg(qc, cmd_tbl);
1302 * Fill in command slot information.
1304 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1305 if (qc->tf.flags & ATA_TFLAG_WRITE)
1306 opts |= AHCI_CMD_WRITE;
1308 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1310 ahci_fill_cmd_slot(pp, qc->tag, opts);
1313 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1315 struct ahci_host_priv *hpriv = ap->host->private_data;
1316 struct ahci_port_priv *pp = ap->private_data;
1317 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1318 struct ata_link *link = NULL;
1319 struct ata_queued_cmd *active_qc;
1320 struct ata_eh_info *active_ehi;
1323 /* determine active link */
1324 ata_port_for_each_link(link, ap)
1325 if (ata_link_active(link))
1330 active_qc = ata_qc_from_tag(ap, link->active_tag);
1331 active_ehi = &link->eh_info;
1333 /* record irq stat */
1334 ata_ehi_clear_desc(host_ehi);
1335 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1337 /* AHCI needs SError cleared; otherwise, it might lock up */
1338 ahci_scr_read(ap, SCR_ERROR, &serror);
1339 ahci_scr_write(ap, SCR_ERROR, serror);
1340 host_ehi->serror |= serror;
1342 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1343 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1344 irq_stat &= ~PORT_IRQ_IF_ERR;
1346 if (irq_stat & PORT_IRQ_TF_ERR) {
1347 /* If qc is active, charge it; otherwise, the active
1348 * link. There's no active qc on NCQ errors. It will
1349 * be determined by EH by reading log page 10h.
1352 active_qc->err_mask |= AC_ERR_DEV;
1354 active_ehi->err_mask |= AC_ERR_DEV;
1356 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1357 host_ehi->serror &= ~SERR_INTERNAL;
1360 if (irq_stat & PORT_IRQ_UNK_FIS) {
1361 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1363 active_ehi->err_mask |= AC_ERR_HSM;
1364 active_ehi->action |= ATA_EH_SOFTRESET;
1365 ata_ehi_push_desc(active_ehi,
1366 "unknown FIS %08x %08x %08x %08x" ,
1367 unk[0], unk[1], unk[2], unk[3]);
1370 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1371 active_ehi->err_mask |= AC_ERR_HSM;
1372 active_ehi->action |= ATA_EH_SOFTRESET;
1373 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1376 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1377 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1378 host_ehi->action |= ATA_EH_SOFTRESET;
1379 ata_ehi_push_desc(host_ehi, "host bus error");
1382 if (irq_stat & PORT_IRQ_IF_ERR) {
1383 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1384 host_ehi->action |= ATA_EH_SOFTRESET;
1385 ata_ehi_push_desc(host_ehi, "interface fatal error");
1388 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1389 ata_ehi_hotplugged(host_ehi);
1390 ata_ehi_push_desc(host_ehi, "%s",
1391 irq_stat & PORT_IRQ_CONNECT ?
1392 "connection status changed" : "PHY RDY changed");
1395 /* okay, let's hand over to EH */
1397 if (irq_stat & PORT_IRQ_FREEZE)
1398 ata_port_freeze(ap);
1403 static void ahci_port_intr(struct ata_port *ap)
1405 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1406 struct ata_eh_info *ehi = &ap->link.eh_info;
1407 struct ahci_port_priv *pp = ap->private_data;
1408 u32 status, qc_active;
1409 int rc, known_irq = 0;
1411 status = readl(port_mmio + PORT_IRQ_STAT);
1412 writel(status, port_mmio + PORT_IRQ_STAT);
1414 if (unlikely(status & PORT_IRQ_ERROR)) {
1415 ahci_error_intr(ap, status);
1419 if (status & PORT_IRQ_SDB_FIS) {
1420 /* If the 'N' bit in word 0 of the FIS is set, we just
1421 * received asynchronous notification. Tell libata
1422 * about it. Note that as the SDB FIS itself is
1423 * accessible, SNotification can be emulated by the
1424 * driver but don't bother for the time being.
1426 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1427 u32 f0 = le32_to_cpu(f[0]);
1430 sata_async_notification(ap);
1433 /* pp->active_link is valid iff any command is in flight */
1434 if (ap->qc_active && pp->active_link->sactive)
1435 qc_active = readl(port_mmio + PORT_SCR_ACT);
1437 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1439 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1443 ehi->err_mask |= AC_ERR_HSM;
1444 ehi->action |= ATA_EH_SOFTRESET;
1445 ata_port_freeze(ap);
1449 /* hmmm... a spurious interupt */
1451 /* if !NCQ, ignore. No modern ATA device has broken HSM
1452 * implementation for non-NCQ commands.
1454 if (!ap->link.sactive)
1457 if (status & PORT_IRQ_D2H_REG_FIS) {
1458 if (!pp->ncq_saw_d2h)
1459 ata_port_printk(ap, KERN_INFO,
1460 "D2H reg with I during NCQ, "
1461 "this message won't be printed again\n");
1462 pp->ncq_saw_d2h = 1;
1466 if (status & PORT_IRQ_DMAS_FIS) {
1467 if (!pp->ncq_saw_dmas)
1468 ata_port_printk(ap, KERN_INFO,
1469 "DMAS FIS during NCQ, "
1470 "this message won't be printed again\n");
1471 pp->ncq_saw_dmas = 1;
1475 if (status & PORT_IRQ_SDB_FIS) {
1476 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1478 if (le32_to_cpu(f[1])) {
1479 /* SDB FIS containing spurious completions
1480 * might be dangerous, whine and fail commands
1481 * with HSM violation. EH will turn off NCQ
1482 * after several such failures.
1484 ata_ehi_push_desc(ehi,
1485 "spurious completions during NCQ "
1486 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1487 readl(port_mmio + PORT_CMD_ISSUE),
1488 readl(port_mmio + PORT_SCR_ACT),
1489 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1490 ehi->err_mask |= AC_ERR_HSM;
1491 ehi->action |= ATA_EH_SOFTRESET;
1492 ata_port_freeze(ap);
1494 if (!pp->ncq_saw_sdb)
1495 ata_port_printk(ap, KERN_INFO,
1496 "spurious SDB FIS %08x:%08x during NCQ, "
1497 "this message won't be printed again\n",
1498 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1499 pp->ncq_saw_sdb = 1;
1505 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1506 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1507 status, ap->link.active_tag, ap->link.sactive);
1510 static void ahci_irq_clear(struct ata_port *ap)
1515 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1517 struct ata_host *host = dev_instance;
1518 struct ahci_host_priv *hpriv;
1519 unsigned int i, handled = 0;
1521 u32 irq_stat, irq_ack = 0;
1525 hpriv = host->private_data;
1526 mmio = host->iomap[AHCI_PCI_BAR];
1528 /* sigh. 0xffffffff is a valid return from h/w */
1529 irq_stat = readl(mmio + HOST_IRQ_STAT);
1530 irq_stat &= hpriv->port_map;
1534 spin_lock(&host->lock);
1536 for (i = 0; i < host->n_ports; i++) {
1537 struct ata_port *ap;
1539 if (!(irq_stat & (1 << i)))
1542 ap = host->ports[i];
1545 VPRINTK("port %u\n", i);
1547 VPRINTK("port %u (no irq)\n", i);
1548 if (ata_ratelimit())
1549 dev_printk(KERN_WARNING, host->dev,
1550 "interrupt on disabled port %u\n", i);
1553 irq_ack |= (1 << i);
1557 writel(irq_ack, mmio + HOST_IRQ_STAT);
1561 spin_unlock(&host->lock);
1565 return IRQ_RETVAL(handled);
1568 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1570 struct ata_port *ap = qc->ap;
1571 void __iomem *port_mmio = ahci_port_base(ap);
1572 struct ahci_port_priv *pp = ap->private_data;
1574 /* Keep track of the currently active link. It will be used
1575 * in completion path to determine whether NCQ phase is in
1578 pp->active_link = qc->dev->link;
1580 if (qc->tf.protocol == ATA_PROT_NCQ)
1581 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1582 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1583 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1588 static void ahci_freeze(struct ata_port *ap)
1590 void __iomem *port_mmio = ahci_port_base(ap);
1593 writel(0, port_mmio + PORT_IRQ_MASK);
1596 static void ahci_thaw(struct ata_port *ap)
1598 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1599 void __iomem *port_mmio = ahci_port_base(ap);
1601 struct ahci_port_priv *pp = ap->private_data;
1604 tmp = readl(port_mmio + PORT_IRQ_STAT);
1605 writel(tmp, port_mmio + PORT_IRQ_STAT);
1606 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1608 /* turn IRQ back on, ignore BAD_PMP if PMP isn't attached */
1609 tmp = pp->intr_mask;
1610 if (!ap->nr_pmp_links)
1611 tmp &= ~PORT_IRQ_BAD_PMP;
1612 writel(tmp, port_mmio + PORT_IRQ_MASK);
1615 static void ahci_error_handler(struct ata_port *ap)
1617 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1618 /* restart engine */
1619 ahci_stop_engine(ap);
1620 ahci_start_engine(ap);
1623 /* perform recovery */
1624 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1625 ahci_hardreset, ahci_postreset,
1626 sata_pmp_std_prereset, ahci_pmp_softreset,
1627 sata_pmp_std_hardreset, sata_pmp_std_postreset);
1630 static void ahci_vt8251_error_handler(struct ata_port *ap)
1632 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1633 /* restart engine */
1634 ahci_stop_engine(ap);
1635 ahci_start_engine(ap);
1638 /* perform recovery */
1639 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1643 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1645 struct ata_port *ap = qc->ap;
1647 /* make DMA engine forget about the failed command */
1648 if (qc->flags & ATA_QCFLAG_FAILED)
1649 ahci_kick_engine(ap, 1);
1652 static void ahci_pmp_attach(struct ata_port *ap)
1654 void __iomem *port_mmio = ahci_port_base(ap);
1657 cmd = readl(port_mmio + PORT_CMD);
1658 cmd |= PORT_CMD_PMP;
1659 writel(cmd, port_mmio + PORT_CMD);
1662 static void ahci_pmp_detach(struct ata_port *ap)
1664 void __iomem *port_mmio = ahci_port_base(ap);
1665 struct ahci_host_priv *hpriv = ap->host->private_data;
1666 unsigned long flags;
1669 cmd = readl(port_mmio + PORT_CMD);
1670 cmd &= ~PORT_CMD_PMP;
1671 writel(cmd, port_mmio + PORT_CMD);
1673 if (hpriv->cap & HOST_CAP_NCQ) {
1674 spin_lock_irqsave(ap->lock, flags);
1675 ap->flags |= ATA_FLAG_NCQ;
1676 spin_unlock_irqrestore(ap->lock, flags);
1680 static int ahci_pmp_read(struct ata_device *dev, int pmp, int reg, u32 *r_val)
1682 struct ata_port *ap = dev->link->ap;
1683 struct ata_taskfile tf;
1686 ahci_kick_engine(ap, 0);
1688 sata_pmp_read_init_tf(&tf, dev, pmp, reg);
1689 rc = ahci_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
1690 SATA_PMP_SCR_TIMEOUT);
1692 ahci_tf_read(ap, &tf);
1693 *r_val = sata_pmp_read_val(&tf);
1698 static int ahci_pmp_write(struct ata_device *dev, int pmp, int reg, u32 val)
1700 struct ata_port *ap = dev->link->ap;
1701 struct ata_taskfile tf;
1703 ahci_kick_engine(ap, 0);
1705 sata_pmp_write_init_tf(&tf, dev, pmp, reg, val);
1706 return ahci_exec_polled_cmd(ap, SATA_PMP_CTRL_PORT, &tf, 1, 0,
1707 SATA_PMP_SCR_TIMEOUT);
1710 static int ahci_port_resume(struct ata_port *ap)
1713 ahci_start_port(ap);
1715 if (ap->nr_pmp_links)
1716 ahci_pmp_attach(ap);
1718 ahci_pmp_detach(ap);
1724 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1726 const char *emsg = NULL;
1729 rc = ahci_deinit_port(ap, &emsg);
1731 ahci_power_down(ap);
1733 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1734 ahci_start_port(ap);
1740 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1742 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1743 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1746 if (mesg.event == PM_EVENT_SUSPEND) {
1747 /* AHCI spec rev1.1 section 8.3.3:
1748 * Software must disable interrupts prior to requesting a
1749 * transition of the HBA to D3 state.
1751 ctl = readl(mmio + HOST_CTL);
1752 ctl &= ~HOST_IRQ_EN;
1753 writel(ctl, mmio + HOST_CTL);
1754 readl(mmio + HOST_CTL); /* flush */
1757 return ata_pci_device_suspend(pdev, mesg);
1760 static int ahci_pci_device_resume(struct pci_dev *pdev)
1762 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1765 rc = ata_pci_device_do_resume(pdev);
1769 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1770 rc = ahci_reset_controller(host);
1774 ahci_init_controller(host);
1777 ata_host_resume(host);
1783 static int ahci_port_start(struct ata_port *ap)
1785 struct device *dev = ap->host->dev;
1786 struct ahci_port_priv *pp;
1791 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1795 rc = ata_pad_alloc(ap, dev);
1799 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1803 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1806 * First item in chunk of DMA memory: 32-slot command table,
1807 * 32 bytes each in size
1810 pp->cmd_slot_dma = mem_dma;
1812 mem += AHCI_CMD_SLOT_SZ;
1813 mem_dma += AHCI_CMD_SLOT_SZ;
1816 * Second item: Received-FIS area
1819 pp->rx_fis_dma = mem_dma;
1821 mem += AHCI_RX_FIS_SZ;
1822 mem_dma += AHCI_RX_FIS_SZ;
1825 * Third item: data area for storing a single command
1826 * and its scatter-gather table
1829 pp->cmd_tbl_dma = mem_dma;
1832 * Save off initial list of interrupts to be enabled.
1833 * This could be changed later
1835 pp->intr_mask = DEF_PORT_IRQ;
1837 ap->private_data = pp;
1839 /* engage engines, captain */
1840 return ahci_port_resume(ap);
1843 static void ahci_port_stop(struct ata_port *ap)
1845 const char *emsg = NULL;
1848 /* de-initialize port */
1849 rc = ahci_deinit_port(ap, &emsg);
1851 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1854 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1859 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1860 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1862 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1864 dev_printk(KERN_ERR, &pdev->dev,
1865 "64-bit DMA enable failed\n");
1870 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1872 dev_printk(KERN_ERR, &pdev->dev,
1873 "32-bit DMA enable failed\n");
1876 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1878 dev_printk(KERN_ERR, &pdev->dev,
1879 "32-bit consistent DMA enable failed\n");
1886 static void ahci_print_info(struct ata_host *host)
1888 struct ahci_host_priv *hpriv = host->private_data;
1889 struct pci_dev *pdev = to_pci_dev(host->dev);
1890 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1891 u32 vers, cap, impl, speed;
1892 const char *speed_s;
1896 vers = readl(mmio + HOST_VERSION);
1898 impl = hpriv->port_map;
1900 speed = (cap >> 20) & 0xf;
1903 else if (speed == 2)
1908 pci_read_config_word(pdev, 0x0a, &cc);
1909 if (cc == PCI_CLASS_STORAGE_IDE)
1911 else if (cc == PCI_CLASS_STORAGE_SATA)
1913 else if (cc == PCI_CLASS_STORAGE_RAID)
1918 dev_printk(KERN_INFO, &pdev->dev,
1919 "AHCI %02x%02x.%02x%02x "
1920 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1923 (vers >> 24) & 0xff,
1924 (vers >> 16) & 0xff,
1928 ((cap >> 8) & 0x1f) + 1,
1934 dev_printk(KERN_INFO, &pdev->dev,
1940 cap & (1 << 31) ? "64bit " : "",
1941 cap & (1 << 30) ? "ncq " : "",
1942 cap & (1 << 29) ? "sntf " : "",
1943 cap & (1 << 28) ? "ilck " : "",
1944 cap & (1 << 27) ? "stag " : "",
1945 cap & (1 << 26) ? "pm " : "",
1946 cap & (1 << 25) ? "led " : "",
1948 cap & (1 << 24) ? "clo " : "",
1949 cap & (1 << 19) ? "nz " : "",
1950 cap & (1 << 18) ? "only " : "",
1951 cap & (1 << 17) ? "pmp " : "",
1952 cap & (1 << 15) ? "pio " : "",
1953 cap & (1 << 14) ? "slum " : "",
1954 cap & (1 << 13) ? "part " : ""
1958 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1960 static int printed_version;
1961 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1962 const struct ata_port_info *ppi[] = { &pi, NULL };
1963 struct device *dev = &pdev->dev;
1964 struct ahci_host_priv *hpriv;
1965 struct ata_host *host;
1970 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1972 if (!printed_version++)
1973 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1975 /* acquire resources */
1976 rc = pcim_enable_device(pdev);
1980 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1982 pcim_pin_device(pdev);
1986 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1989 hpriv->flags |= (unsigned long)pi.private_data;
1991 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1994 /* save initial config */
1995 ahci_save_initial_config(pdev, hpriv);
1998 if (hpriv->cap & HOST_CAP_NCQ)
1999 pi.flags |= ATA_FLAG_NCQ;
2001 if (hpriv->cap & HOST_CAP_PMP)
2002 pi.flags |= ATA_FLAG_PMP;
2004 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
2007 host->iomap = pcim_iomap_table(pdev);
2008 host->private_data = hpriv;
2010 for (i = 0; i < host->n_ports; i++) {
2011 struct ata_port *ap = host->ports[i];
2012 void __iomem *port_mmio = ahci_port_base(ap);
2014 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2015 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2016 0x100 + ap->port_no * 0x80, "port");
2018 /* standard SATA port setup */
2019 if (hpriv->port_map & (1 << i))
2020 ap->ioaddr.cmd_addr = port_mmio;
2022 /* disabled/not-implemented port */
2024 ap->ops = &ata_dummy_port_ops;
2027 /* initialize adapter */
2028 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2032 rc = ahci_reset_controller(host);
2036 ahci_init_controller(host);
2037 ahci_print_info(host);
2039 pci_set_master(pdev);
2040 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2044 static int __init ahci_init(void)
2046 return pci_register_driver(&ahci_pci_driver);
2049 static void __exit ahci_exit(void)
2051 pci_unregister_driver(&ahci_pci_driver);
2055 MODULE_AUTHOR("Jeff Garzik");
2056 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2057 MODULE_LICENSE("GPL");
2058 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2059 MODULE_VERSION(DRV_VERSION);
2061 module_init(ahci_init);
2062 module_exit(ahci_exit);