2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
52 static int ahci_skip_host_reset;
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56 static int ahci_enable_alpm(struct ata_port *ap,
58 static void ahci_disable_alpm(struct ata_port *ap);
59 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
60 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
62 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
69 AHCI_MAX_SG = 168, /* hardware max is 64K */
70 AHCI_DMA_BOUNDARY = 0xffffffff,
73 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
75 AHCI_CMD_TBL_CDB = 0x40,
76 AHCI_CMD_TBL_HDR_SZ = 0x80,
77 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
78 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
79 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
81 AHCI_IRQ_ON_SG = (1 << 31),
82 AHCI_CMD_ATAPI = (1 << 5),
83 AHCI_CMD_WRITE = (1 << 6),
84 AHCI_CMD_PREFETCH = (1 << 7),
85 AHCI_CMD_RESET = (1 << 8),
86 AHCI_CMD_CLR_BUSY = (1 << 10),
88 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
89 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
90 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
93 board_ahci_vt8251 = 1,
94 board_ahci_ign_iferr = 2,
101 /* global controller registers */
102 HOST_CAP = 0x00, /* host capabilities */
103 HOST_CTL = 0x04, /* global host control */
104 HOST_IRQ_STAT = 0x08, /* interrupt status */
105 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
106 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
107 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
108 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
111 HOST_RESET = (1 << 0), /* reset controller; self-clear */
112 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
113 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
116 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
117 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
118 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
119 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
120 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
121 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
122 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
123 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
124 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
126 /* registers for each SATA port */
127 PORT_LST_ADDR = 0x00, /* command list DMA addr */
128 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
129 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
130 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
131 PORT_IRQ_STAT = 0x10, /* interrupt status */
132 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
133 PORT_CMD = 0x18, /* port command */
134 PORT_TFDATA = 0x20, /* taskfile data */
135 PORT_SIG = 0x24, /* device TF signature */
136 PORT_CMD_ISSUE = 0x38, /* command issue */
137 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
138 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
139 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
140 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
141 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
143 /* PORT_IRQ_{STAT,MASK} bits */
144 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
145 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
146 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
147 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
148 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
149 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
150 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
151 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
153 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
154 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
155 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
156 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
157 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
158 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
159 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
160 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
161 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
163 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
169 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
171 PORT_IRQ_HBUS_DATA_ERR,
172 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
173 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
174 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
177 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
178 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
179 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
180 PORT_CMD_PMP = (1 << 17), /* PMP attached */
181 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
182 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
183 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
184 PORT_CMD_CLO = (1 << 3), /* Command list override */
185 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
186 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
187 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
189 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
190 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
191 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
192 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
194 /* hpriv->flags bits */
195 AHCI_HFLAG_NO_NCQ = (1 << 0),
196 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
197 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
198 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
199 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
200 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
201 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
202 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
203 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
204 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
208 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
209 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
210 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
213 ICH_MAP = 0x90, /* ICH MAP register */
216 EM_CTL_RST = (1 << 9), /* Reset */
217 EM_CTL_TM = (1 << 8), /* Transmit Message */
218 EM_CTL_ALHD = (1 << 26), /* Activity LED */
221 struct ahci_cmd_hdr {
236 struct ahci_em_priv {
237 enum sw_activity blink_policy;
238 struct timer_list timer;
239 unsigned long saved_activity;
240 unsigned long activity;
241 unsigned long led_state;
244 struct ahci_host_priv {
245 unsigned int flags; /* AHCI_HFLAG_* */
246 u32 cap; /* cap to use */
247 u32 port_map; /* port map to use */
248 u32 saved_cap; /* saved initial cap */
249 u32 saved_port_map; /* saved initial port_map */
250 u32 em_loc; /* enclosure management location */
253 struct ahci_port_priv {
254 struct ata_link *active_link;
255 struct ahci_cmd_hdr *cmd_slot;
256 dma_addr_t cmd_slot_dma;
258 dma_addr_t cmd_tbl_dma;
260 dma_addr_t rx_fis_dma;
261 /* for NCQ spurious interrupt analysis */
262 unsigned int ncq_saw_d2h:1;
263 unsigned int ncq_saw_dmas:1;
264 unsigned int ncq_saw_sdb:1;
265 u32 intr_mask; /* interrupts to enable */
266 struct ahci_em_priv em_priv[MAX_SLOTS];/* enclosure management info
270 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
271 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
272 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
273 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
274 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
275 static int ahci_port_start(struct ata_port *ap);
276 static void ahci_port_stop(struct ata_port *ap);
277 static void ahci_qc_prep(struct ata_queued_cmd *qc);
278 static void ahci_freeze(struct ata_port *ap);
279 static void ahci_thaw(struct ata_port *ap);
280 static void ahci_pmp_attach(struct ata_port *ap);
281 static void ahci_pmp_detach(struct ata_port *ap);
282 static int ahci_softreset(struct ata_link *link, unsigned int *class,
283 unsigned long deadline);
284 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
285 unsigned long deadline);
286 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
287 unsigned long deadline);
288 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
289 unsigned long deadline);
290 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
291 unsigned long deadline);
292 static void ahci_postreset(struct ata_link *link, unsigned int *class);
293 static void ahci_error_handler(struct ata_port *ap);
294 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
295 static int ahci_port_resume(struct ata_port *ap);
296 static void ahci_dev_config(struct ata_device *dev);
297 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
298 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
301 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
302 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
303 static int ahci_pci_device_resume(struct pci_dev *pdev);
305 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
306 static ssize_t ahci_activity_store(struct ata_device *dev,
307 enum sw_activity val);
308 static void ahci_init_sw_activity(struct ata_link *link);
310 static struct device_attribute *ahci_shost_attrs[] = {
311 &dev_attr_link_power_management_policy,
312 &dev_attr_em_message_type,
313 &dev_attr_em_message,
317 static struct device_attribute *ahci_sdev_attrs[] = {
318 &dev_attr_sw_activity,
322 static struct scsi_host_template ahci_sht = {
323 ATA_NCQ_SHT(DRV_NAME),
324 .can_queue = AHCI_MAX_CMDS - 1,
325 .sg_tablesize = AHCI_MAX_SG,
326 .dma_boundary = AHCI_DMA_BOUNDARY,
327 .shost_attrs = ahci_shost_attrs,
328 .sdev_attrs = ahci_sdev_attrs,
331 static struct ata_port_operations ahci_ops = {
332 .inherits = &sata_pmp_port_ops,
334 .qc_defer = sata_pmp_qc_defer_cmd_switch,
335 .qc_prep = ahci_qc_prep,
336 .qc_issue = ahci_qc_issue,
337 .qc_fill_rtf = ahci_qc_fill_rtf,
339 .freeze = ahci_freeze,
341 .softreset = ahci_softreset,
342 .hardreset = ahci_hardreset,
343 .postreset = ahci_postreset,
344 .pmp_softreset = ahci_softreset,
345 .error_handler = ahci_error_handler,
346 .post_internal_cmd = ahci_post_internal_cmd,
347 .dev_config = ahci_dev_config,
349 .scr_read = ahci_scr_read,
350 .scr_write = ahci_scr_write,
351 .pmp_attach = ahci_pmp_attach,
352 .pmp_detach = ahci_pmp_detach,
354 .enable_pm = ahci_enable_alpm,
355 .disable_pm = ahci_disable_alpm,
356 .em_show = ahci_led_show,
357 .em_store = ahci_led_store,
358 .sw_activity_show = ahci_activity_show,
359 .sw_activity_store = ahci_activity_store,
361 .port_suspend = ahci_port_suspend,
362 .port_resume = ahci_port_resume,
364 .port_start = ahci_port_start,
365 .port_stop = ahci_port_stop,
368 static struct ata_port_operations ahci_vt8251_ops = {
369 .inherits = &ahci_ops,
370 .hardreset = ahci_vt8251_hardreset,
373 static struct ata_port_operations ahci_p5wdh_ops = {
374 .inherits = &ahci_ops,
375 .hardreset = ahci_p5wdh_hardreset,
378 static struct ata_port_operations ahci_sb600_ops = {
379 .inherits = &ahci_ops,
380 .softreset = ahci_sb600_softreset,
381 .pmp_softreset = ahci_sb600_softreset,
384 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
386 static const struct ata_port_info ahci_port_info[] = {
389 .flags = AHCI_FLAG_COMMON,
390 .pio_mask = 0x1f, /* pio0-4 */
391 .udma_mask = ATA_UDMA6,
392 .port_ops = &ahci_ops,
394 /* board_ahci_vt8251 */
396 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
397 .flags = AHCI_FLAG_COMMON,
398 .pio_mask = 0x1f, /* pio0-4 */
399 .udma_mask = ATA_UDMA6,
400 .port_ops = &ahci_vt8251_ops,
402 /* board_ahci_ign_iferr */
404 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
405 .flags = AHCI_FLAG_COMMON,
406 .pio_mask = 0x1f, /* pio0-4 */
407 .udma_mask = ATA_UDMA6,
408 .port_ops = &ahci_ops,
410 /* board_ahci_sb600 */
412 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
413 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
415 .flags = AHCI_FLAG_COMMON,
416 .pio_mask = 0x1f, /* pio0-4 */
417 .udma_mask = ATA_UDMA6,
418 .port_ops = &ahci_sb600_ops,
422 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
423 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
424 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
425 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
426 .pio_mask = 0x1f, /* pio0-4 */
427 .udma_mask = ATA_UDMA6,
428 .port_ops = &ahci_ops,
430 /* board_ahci_sb700 */
432 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
433 .flags = AHCI_FLAG_COMMON,
434 .pio_mask = 0x1f, /* pio0-4 */
435 .udma_mask = ATA_UDMA6,
436 .port_ops = &ahci_sb600_ops,
438 /* board_ahci_mcp65 */
440 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
441 .flags = AHCI_FLAG_COMMON,
442 .pio_mask = 0x1f, /* pio0-4 */
443 .udma_mask = ATA_UDMA6,
444 .port_ops = &ahci_ops,
446 /* board_ahci_nopmp */
448 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
449 .flags = AHCI_FLAG_COMMON,
450 .pio_mask = 0x1f, /* pio0-4 */
451 .udma_mask = ATA_UDMA6,
452 .port_ops = &ahci_ops,
456 static const struct pci_device_id ahci_pci_tbl[] = {
458 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
459 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
460 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
461 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
462 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
463 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
464 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
465 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
466 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
467 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
468 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
469 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
470 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
471 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
472 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
473 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
474 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
476 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
477 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
478 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
479 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
480 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
481 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
482 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
483 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
484 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
485 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
486 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
487 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
488 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
489 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
490 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
492 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
493 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
494 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
497 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
498 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
499 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
500 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
501 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
502 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
503 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
506 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
507 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
510 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
511 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
512 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
513 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
514 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
515 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
516 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
517 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
518 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
519 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
520 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
521 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
522 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
523 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
524 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
525 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
526 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
527 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
528 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
529 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
530 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
531 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
532 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
533 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
534 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
535 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
536 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
537 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
538 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
539 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
540 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
541 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
542 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
543 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
544 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
545 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
546 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
547 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
548 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
549 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
550 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
551 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
552 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
553 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
554 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
555 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
556 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
557 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
558 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
559 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
560 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
561 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
562 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
563 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
564 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
565 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
566 { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */
567 { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */
568 { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */
569 { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */
570 { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */
571 { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */
572 { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */
573 { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */
574 { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */
575 { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */
576 { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */
577 { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */
580 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
581 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
582 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
585 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
586 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
588 /* Generic, PCI class code for AHCI */
589 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
590 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
592 { } /* terminate list */
596 static struct pci_driver ahci_pci_driver = {
598 .id_table = ahci_pci_tbl,
599 .probe = ahci_init_one,
600 .remove = ata_pci_remove_one,
602 .suspend = ahci_pci_device_suspend,
603 .resume = ahci_pci_device_resume,
607 static int ahci_em_messages = 1;
608 module_param(ahci_em_messages, int, 0444);
609 /* add other LED protocol types when they become supported */
610 MODULE_PARM_DESC(ahci_em_messages,
611 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
613 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
614 static int marvell_enable;
616 static int marvell_enable = 1;
618 module_param(marvell_enable, int, 0644);
619 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
622 static inline int ahci_nr_ports(u32 cap)
624 return (cap & 0x1f) + 1;
627 static inline void __iomem *__ahci_port_base(struct ata_host *host,
628 unsigned int port_no)
630 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
632 return mmio + 0x100 + (port_no * 0x80);
635 static inline void __iomem *ahci_port_base(struct ata_port *ap)
637 return __ahci_port_base(ap->host, ap->port_no);
640 static void ahci_enable_ahci(void __iomem *mmio)
645 /* turn on AHCI_EN */
646 tmp = readl(mmio + HOST_CTL);
647 if (tmp & HOST_AHCI_EN)
650 /* Some controllers need AHCI_EN to be written multiple times.
651 * Try a few times before giving up.
653 for (i = 0; i < 5; i++) {
655 writel(tmp, mmio + HOST_CTL);
656 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
657 if (tmp & HOST_AHCI_EN)
666 * ahci_save_initial_config - Save and fixup initial config values
667 * @pdev: target PCI device
668 * @hpriv: host private area to store config values
670 * Some registers containing configuration info might be setup by
671 * BIOS and might be cleared on reset. This function saves the
672 * initial values of those registers into @hpriv such that they
673 * can be restored after controller reset.
675 * If inconsistent, config values are fixed up by this function.
680 static void ahci_save_initial_config(struct pci_dev *pdev,
681 struct ahci_host_priv *hpriv)
683 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
688 /* make sure AHCI mode is enabled before accessing CAP */
689 ahci_enable_ahci(mmio);
691 /* Values prefixed with saved_ are written back to host after
692 * reset. Values without are used for driver operation.
694 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
695 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
697 /* some chips have errata preventing 64bit use */
698 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
699 dev_printk(KERN_INFO, &pdev->dev,
700 "controller can't do 64bit DMA, forcing 32bit\n");
704 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
705 dev_printk(KERN_INFO, &pdev->dev,
706 "controller can't do NCQ, turning off CAP_NCQ\n");
707 cap &= ~HOST_CAP_NCQ;
710 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
711 dev_printk(KERN_INFO, &pdev->dev,
712 "controller can do NCQ, turning on CAP_NCQ\n");
716 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
717 dev_printk(KERN_INFO, &pdev->dev,
718 "controller can't do PMP, turning off CAP_PMP\n");
719 cap &= ~HOST_CAP_PMP;
722 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
724 dev_printk(KERN_INFO, &pdev->dev,
725 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
731 * Temporary Marvell 6145 hack: PATA port presence
732 * is asserted through the standard AHCI port
733 * presence register, as bit 4 (counting from 0)
735 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
736 if (pdev->device == 0x6121)
740 dev_printk(KERN_ERR, &pdev->dev,
741 "MV_AHCI HACK: port_map %x -> %x\n",
744 dev_printk(KERN_ERR, &pdev->dev,
745 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
750 /* cross check port_map and cap.n_ports */
754 for (i = 0; i < AHCI_MAX_PORTS; i++)
755 if (port_map & (1 << i))
758 /* If PI has more ports than n_ports, whine, clear
759 * port_map and let it be generated from n_ports.
761 if (map_ports > ahci_nr_ports(cap)) {
762 dev_printk(KERN_WARNING, &pdev->dev,
763 "implemented port map (0x%x) contains more "
764 "ports than nr_ports (%u), using nr_ports\n",
765 port_map, ahci_nr_ports(cap));
770 /* fabricate port_map from cap.nr_ports */
772 port_map = (1 << ahci_nr_ports(cap)) - 1;
773 dev_printk(KERN_WARNING, &pdev->dev,
774 "forcing PORTS_IMPL to 0x%x\n", port_map);
776 /* write the fixed up value to the PI register */
777 hpriv->saved_port_map = port_map;
780 /* record values to use during operation */
782 hpriv->port_map = port_map;
786 * ahci_restore_initial_config - Restore initial config
787 * @host: target ATA host
789 * Restore initial config stored by ahci_save_initial_config().
794 static void ahci_restore_initial_config(struct ata_host *host)
796 struct ahci_host_priv *hpriv = host->private_data;
797 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
799 writel(hpriv->saved_cap, mmio + HOST_CAP);
800 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
801 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
804 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
806 static const int offset[] = {
807 [SCR_STATUS] = PORT_SCR_STAT,
808 [SCR_CONTROL] = PORT_SCR_CTL,
809 [SCR_ERROR] = PORT_SCR_ERR,
810 [SCR_ACTIVE] = PORT_SCR_ACT,
811 [SCR_NOTIFICATION] = PORT_SCR_NTF,
813 struct ahci_host_priv *hpriv = ap->host->private_data;
815 if (sc_reg < ARRAY_SIZE(offset) &&
816 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
817 return offset[sc_reg];
821 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
823 void __iomem *port_mmio = ahci_port_base(ap);
824 int offset = ahci_scr_offset(ap, sc_reg);
827 *val = readl(port_mmio + offset);
833 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
835 void __iomem *port_mmio = ahci_port_base(ap);
836 int offset = ahci_scr_offset(ap, sc_reg);
839 writel(val, port_mmio + offset);
845 static void ahci_start_engine(struct ata_port *ap)
847 void __iomem *port_mmio = ahci_port_base(ap);
851 tmp = readl(port_mmio + PORT_CMD);
852 tmp |= PORT_CMD_START;
853 writel(tmp, port_mmio + PORT_CMD);
854 readl(port_mmio + PORT_CMD); /* flush */
857 static int ahci_stop_engine(struct ata_port *ap)
859 void __iomem *port_mmio = ahci_port_base(ap);
862 tmp = readl(port_mmio + PORT_CMD);
864 /* check if the HBA is idle */
865 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
868 /* setting HBA to idle */
869 tmp &= ~PORT_CMD_START;
870 writel(tmp, port_mmio + PORT_CMD);
872 /* wait for engine to stop. This could be as long as 500 msec */
873 tmp = ata_wait_register(port_mmio + PORT_CMD,
874 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
875 if (tmp & PORT_CMD_LIST_ON)
881 static void ahci_start_fis_rx(struct ata_port *ap)
883 void __iomem *port_mmio = ahci_port_base(ap);
884 struct ahci_host_priv *hpriv = ap->host->private_data;
885 struct ahci_port_priv *pp = ap->private_data;
888 /* set FIS registers */
889 if (hpriv->cap & HOST_CAP_64)
890 writel((pp->cmd_slot_dma >> 16) >> 16,
891 port_mmio + PORT_LST_ADDR_HI);
892 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
894 if (hpriv->cap & HOST_CAP_64)
895 writel((pp->rx_fis_dma >> 16) >> 16,
896 port_mmio + PORT_FIS_ADDR_HI);
897 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
899 /* enable FIS reception */
900 tmp = readl(port_mmio + PORT_CMD);
901 tmp |= PORT_CMD_FIS_RX;
902 writel(tmp, port_mmio + PORT_CMD);
905 readl(port_mmio + PORT_CMD);
908 static int ahci_stop_fis_rx(struct ata_port *ap)
910 void __iomem *port_mmio = ahci_port_base(ap);
913 /* disable FIS reception */
914 tmp = readl(port_mmio + PORT_CMD);
915 tmp &= ~PORT_CMD_FIS_RX;
916 writel(tmp, port_mmio + PORT_CMD);
918 /* wait for completion, spec says 500ms, give it 1000 */
919 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
920 PORT_CMD_FIS_ON, 10, 1000);
921 if (tmp & PORT_CMD_FIS_ON)
927 static void ahci_power_up(struct ata_port *ap)
929 struct ahci_host_priv *hpriv = ap->host->private_data;
930 void __iomem *port_mmio = ahci_port_base(ap);
933 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
936 if (hpriv->cap & HOST_CAP_SSS) {
937 cmd |= PORT_CMD_SPIN_UP;
938 writel(cmd, port_mmio + PORT_CMD);
942 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
945 static void ahci_disable_alpm(struct ata_port *ap)
947 struct ahci_host_priv *hpriv = ap->host->private_data;
948 void __iomem *port_mmio = ahci_port_base(ap);
950 struct ahci_port_priv *pp = ap->private_data;
952 /* IPM bits should be disabled by libata-core */
953 /* get the existing command bits */
954 cmd = readl(port_mmio + PORT_CMD);
956 /* disable ALPM and ASP */
957 cmd &= ~PORT_CMD_ASP;
958 cmd &= ~PORT_CMD_ALPE;
960 /* force the interface back to active */
961 cmd |= PORT_CMD_ICC_ACTIVE;
963 /* write out new cmd value */
964 writel(cmd, port_mmio + PORT_CMD);
965 cmd = readl(port_mmio + PORT_CMD);
967 /* wait 10ms to be sure we've come out of any low power state */
970 /* clear out any PhyRdy stuff from interrupt status */
971 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
973 /* go ahead and clean out PhyRdy Change from Serror too */
974 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
977 * Clear flag to indicate that we should ignore all PhyRdy
980 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
983 * Enable interrupts on Phy Ready.
985 pp->intr_mask |= PORT_IRQ_PHYRDY;
986 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
989 * don't change the link pm policy - we can be called
990 * just to turn of link pm temporarily
994 static int ahci_enable_alpm(struct ata_port *ap,
997 struct ahci_host_priv *hpriv = ap->host->private_data;
998 void __iomem *port_mmio = ahci_port_base(ap);
1000 struct ahci_port_priv *pp = ap->private_data;
1003 /* Make sure the host is capable of link power management */
1004 if (!(hpriv->cap & HOST_CAP_ALPM))
1008 case MAX_PERFORMANCE:
1011 * if we came here with NOT_AVAILABLE,
1012 * it just means this is the first time we
1013 * have tried to enable - default to max performance,
1014 * and let the user go to lower power modes on request.
1016 ahci_disable_alpm(ap);
1019 /* configure HBA to enter SLUMBER */
1023 /* configure HBA to enter PARTIAL */
1031 * Disable interrupts on Phy Ready. This keeps us from
1032 * getting woken up due to spurious phy ready interrupts
1033 * TBD - Hot plug should be done via polling now, is
1034 * that even supported?
1036 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1037 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1040 * Set a flag to indicate that we should ignore all PhyRdy
1041 * state changes since these can happen now whenever we
1044 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1046 /* get the existing command bits */
1047 cmd = readl(port_mmio + PORT_CMD);
1050 * Set ASP based on Policy
1055 * Setting this bit will instruct the HBA to aggressively
1056 * enter a lower power link state when it's appropriate and
1057 * based on the value set above for ASP
1059 cmd |= PORT_CMD_ALPE;
1061 /* write out new cmd value */
1062 writel(cmd, port_mmio + PORT_CMD);
1063 cmd = readl(port_mmio + PORT_CMD);
1065 /* IPM bits should be set by libata-core */
1070 static void ahci_power_down(struct ata_port *ap)
1072 struct ahci_host_priv *hpriv = ap->host->private_data;
1073 void __iomem *port_mmio = ahci_port_base(ap);
1076 if (!(hpriv->cap & HOST_CAP_SSS))
1079 /* put device into listen mode, first set PxSCTL.DET to 0 */
1080 scontrol = readl(port_mmio + PORT_SCR_CTL);
1082 writel(scontrol, port_mmio + PORT_SCR_CTL);
1084 /* then set PxCMD.SUD to 0 */
1085 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1086 cmd &= ~PORT_CMD_SPIN_UP;
1087 writel(cmd, port_mmio + PORT_CMD);
1091 static void ahci_start_port(struct ata_port *ap)
1093 struct ahci_port_priv *pp = ap->private_data;
1094 struct ata_link *link;
1095 struct ahci_em_priv *emp;
1097 /* enable FIS reception */
1098 ahci_start_fis_rx(ap);
1101 ahci_start_engine(ap);
1104 if (ap->flags & ATA_FLAG_EM) {
1105 ata_port_for_each_link(link, ap) {
1106 emp = &pp->em_priv[link->pmp];
1107 ahci_transmit_led_message(ap, emp->led_state, 4);
1111 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1112 ata_port_for_each_link(link, ap)
1113 ahci_init_sw_activity(link);
1117 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1122 rc = ahci_stop_engine(ap);
1124 *emsg = "failed to stop engine";
1128 /* disable FIS reception */
1129 rc = ahci_stop_fis_rx(ap);
1131 *emsg = "failed stop FIS RX";
1138 static int ahci_reset_controller(struct ata_host *host)
1140 struct pci_dev *pdev = to_pci_dev(host->dev);
1141 struct ahci_host_priv *hpriv = host->private_data;
1142 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1145 /* we must be in AHCI mode, before using anything
1146 * AHCI-specific, such as HOST_RESET.
1148 ahci_enable_ahci(mmio);
1150 /* global controller reset */
1151 if (!ahci_skip_host_reset) {
1152 tmp = readl(mmio + HOST_CTL);
1153 if ((tmp & HOST_RESET) == 0) {
1154 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1155 readl(mmio + HOST_CTL); /* flush */
1159 * to perform host reset, OS should set HOST_RESET
1160 * and poll until this bit is read to be "0".
1161 * reset must complete within 1 second, or
1162 * the hardware should be considered fried.
1164 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1165 HOST_RESET, 10, 1000);
1167 if (tmp & HOST_RESET) {
1168 dev_printk(KERN_ERR, host->dev,
1169 "controller reset failed (0x%x)\n", tmp);
1173 /* turn on AHCI mode */
1174 ahci_enable_ahci(mmio);
1176 /* Some registers might be cleared on reset. Restore
1179 ahci_restore_initial_config(host);
1181 dev_printk(KERN_INFO, host->dev,
1182 "skipping global host reset\n");
1184 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1188 pci_read_config_word(pdev, 0x92, &tmp16);
1189 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1190 tmp16 |= hpriv->port_map;
1191 pci_write_config_word(pdev, 0x92, tmp16);
1198 static void ahci_sw_activity(struct ata_link *link)
1200 struct ata_port *ap = link->ap;
1201 struct ahci_port_priv *pp = ap->private_data;
1202 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1204 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1208 if (!timer_pending(&emp->timer))
1209 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1212 static void ahci_sw_activity_blink(unsigned long arg)
1214 struct ata_link *link = (struct ata_link *)arg;
1215 struct ata_port *ap = link->ap;
1216 struct ahci_port_priv *pp = ap->private_data;
1217 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1218 unsigned long led_message = emp->led_state;
1219 u32 activity_led_state;
1221 led_message &= 0xffff0000;
1222 led_message |= ap->port_no | (link->pmp << 8);
1224 /* check to see if we've had activity. If so,
1225 * toggle state of LED and reset timer. If not,
1226 * turn LED to desired idle state.
1228 if (emp->saved_activity != emp->activity) {
1229 emp->saved_activity = emp->activity;
1230 /* get the current LED state */
1231 activity_led_state = led_message & 0x00010000;
1233 if (activity_led_state)
1234 activity_led_state = 0;
1236 activity_led_state = 1;
1238 /* clear old state */
1239 led_message &= 0xfff8ffff;
1242 led_message |= (activity_led_state << 16);
1243 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1245 /* switch to idle */
1246 led_message &= 0xfff8ffff;
1247 if (emp->blink_policy == BLINK_OFF)
1248 led_message |= (1 << 16);
1250 ahci_transmit_led_message(ap, led_message, 4);
1253 static void ahci_init_sw_activity(struct ata_link *link)
1255 struct ata_port *ap = link->ap;
1256 struct ahci_port_priv *pp = ap->private_data;
1257 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1259 /* init activity stats, setup timer */
1260 emp->saved_activity = emp->activity = 0;
1261 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1263 /* check our blink policy and set flag for link if it's enabled */
1264 if (emp->blink_policy)
1265 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1268 static int ahci_reset_em(struct ata_host *host)
1270 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1273 em_ctl = readl(mmio + HOST_EM_CTL);
1274 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1277 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1281 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1284 struct ahci_host_priv *hpriv = ap->host->private_data;
1285 struct ahci_port_priv *pp = ap->private_data;
1286 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1288 u32 message[] = {0, 0};
1289 unsigned long flags;
1291 struct ahci_em_priv *emp;
1293 /* get the slot number from the message */
1294 pmp = (state & 0x0000ff00) >> 8;
1295 if (pmp < MAX_SLOTS)
1296 emp = &pp->em_priv[pmp];
1300 spin_lock_irqsave(ap->lock, flags);
1303 * if we are still busy transmitting a previous message,
1306 em_ctl = readl(mmio + HOST_EM_CTL);
1307 if (em_ctl & EM_CTL_TM) {
1308 spin_unlock_irqrestore(ap->lock, flags);
1313 * create message header - this is all zero except for
1314 * the message size, which is 4 bytes.
1316 message[0] |= (4 << 8);
1318 /* ignore 0:4 of byte zero, fill in port info yourself */
1319 message[1] = ((state & 0xfffffff0) | ap->port_no);
1321 /* write message to EM_LOC */
1322 writel(message[0], mmio + hpriv->em_loc);
1323 writel(message[1], mmio + hpriv->em_loc+4);
1325 /* save off new led state for port/slot */
1326 emp->led_state = message[1];
1329 * tell hardware to transmit the message
1331 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1333 spin_unlock_irqrestore(ap->lock, flags);
1337 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1339 struct ahci_port_priv *pp = ap->private_data;
1340 struct ata_link *link;
1341 struct ahci_em_priv *emp;
1344 ata_port_for_each_link(link, ap) {
1345 emp = &pp->em_priv[link->pmp];
1346 rc += sprintf(buf, "%lx\n", emp->led_state);
1351 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1356 struct ahci_port_priv *pp = ap->private_data;
1357 struct ahci_em_priv *emp;
1359 state = simple_strtoul(buf, NULL, 0);
1361 /* get the slot number from the message */
1362 pmp = (state & 0x0000ff00) >> 8;
1363 if (pmp < MAX_SLOTS)
1364 emp = &pp->em_priv[pmp];
1368 /* mask off the activity bits if we are in sw_activity
1369 * mode, user should turn off sw_activity before setting
1370 * activity led through em_message
1372 if (emp->blink_policy)
1373 state &= 0xfff8ffff;
1375 return ahci_transmit_led_message(ap, state, size);
1378 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1380 struct ata_link *link = dev->link;
1381 struct ata_port *ap = link->ap;
1382 struct ahci_port_priv *pp = ap->private_data;
1383 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1384 u32 port_led_state = emp->led_state;
1386 /* save the desired Activity LED behavior */
1389 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1391 /* set the LED to OFF */
1392 port_led_state &= 0xfff80000;
1393 port_led_state |= (ap->port_no | (link->pmp << 8));
1394 ahci_transmit_led_message(ap, port_led_state, 4);
1396 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1397 if (val == BLINK_OFF) {
1398 /* set LED to ON for idle */
1399 port_led_state &= 0xfff80000;
1400 port_led_state |= (ap->port_no | (link->pmp << 8));
1401 port_led_state |= 0x00010000; /* check this */
1402 ahci_transmit_led_message(ap, port_led_state, 4);
1405 emp->blink_policy = val;
1409 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1411 struct ata_link *link = dev->link;
1412 struct ata_port *ap = link->ap;
1413 struct ahci_port_priv *pp = ap->private_data;
1414 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1416 /* display the saved value of activity behavior for this
1419 return sprintf(buf, "%d\n", emp->blink_policy);
1422 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1423 int port_no, void __iomem *mmio,
1424 void __iomem *port_mmio)
1426 const char *emsg = NULL;
1430 /* make sure port is not active */
1431 rc = ahci_deinit_port(ap, &emsg);
1433 dev_printk(KERN_WARNING, &pdev->dev,
1434 "%s (%d)\n", emsg, rc);
1437 tmp = readl(port_mmio + PORT_SCR_ERR);
1438 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1439 writel(tmp, port_mmio + PORT_SCR_ERR);
1441 /* clear port IRQ */
1442 tmp = readl(port_mmio + PORT_IRQ_STAT);
1443 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1445 writel(tmp, port_mmio + PORT_IRQ_STAT);
1447 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1450 static void ahci_init_controller(struct ata_host *host)
1452 struct ahci_host_priv *hpriv = host->private_data;
1453 struct pci_dev *pdev = to_pci_dev(host->dev);
1454 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1456 void __iomem *port_mmio;
1460 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1461 if (pdev->device == 0x6121)
1465 port_mmio = __ahci_port_base(host, mv);
1467 writel(0, port_mmio + PORT_IRQ_MASK);
1469 /* clear port IRQ */
1470 tmp = readl(port_mmio + PORT_IRQ_STAT);
1471 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1473 writel(tmp, port_mmio + PORT_IRQ_STAT);
1476 for (i = 0; i < host->n_ports; i++) {
1477 struct ata_port *ap = host->ports[i];
1479 port_mmio = ahci_port_base(ap);
1480 if (ata_port_is_dummy(ap))
1483 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1486 tmp = readl(mmio + HOST_CTL);
1487 VPRINTK("HOST_CTL 0x%x\n", tmp);
1488 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1489 tmp = readl(mmio + HOST_CTL);
1490 VPRINTK("HOST_CTL 0x%x\n", tmp);
1493 static void ahci_dev_config(struct ata_device *dev)
1495 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1497 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1498 dev->max_sectors = 255;
1499 ata_dev_printk(dev, KERN_INFO,
1500 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1504 static unsigned int ahci_dev_classify(struct ata_port *ap)
1506 void __iomem *port_mmio = ahci_port_base(ap);
1507 struct ata_taskfile tf;
1510 tmp = readl(port_mmio + PORT_SIG);
1511 tf.lbah = (tmp >> 24) & 0xff;
1512 tf.lbam = (tmp >> 16) & 0xff;
1513 tf.lbal = (tmp >> 8) & 0xff;
1514 tf.nsect = (tmp) & 0xff;
1516 return ata_dev_classify(&tf);
1519 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1522 dma_addr_t cmd_tbl_dma;
1524 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1526 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1527 pp->cmd_slot[tag].status = 0;
1528 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1529 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1532 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1534 void __iomem *port_mmio = ahci_port_base(ap);
1535 struct ahci_host_priv *hpriv = ap->host->private_data;
1536 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1540 /* do we need to kick the port? */
1541 busy = status & (ATA_BUSY | ATA_DRQ);
1542 if (!busy && !force_restart)
1546 rc = ahci_stop_engine(ap);
1550 /* need to do CLO? */
1556 if (!(hpriv->cap & HOST_CAP_CLO)) {
1562 tmp = readl(port_mmio + PORT_CMD);
1563 tmp |= PORT_CMD_CLO;
1564 writel(tmp, port_mmio + PORT_CMD);
1567 tmp = ata_wait_register(port_mmio + PORT_CMD,
1568 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1569 if (tmp & PORT_CMD_CLO)
1572 /* restart engine */
1574 ahci_start_engine(ap);
1578 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1579 struct ata_taskfile *tf, int is_cmd, u16 flags,
1580 unsigned long timeout_msec)
1582 const u32 cmd_fis_len = 5; /* five dwords */
1583 struct ahci_port_priv *pp = ap->private_data;
1584 void __iomem *port_mmio = ahci_port_base(ap);
1585 u8 *fis = pp->cmd_tbl;
1588 /* prep the command */
1589 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1590 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1593 writel(1, port_mmio + PORT_CMD_ISSUE);
1596 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1599 ahci_kick_engine(ap, 1);
1603 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1608 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1609 int pmp, unsigned long deadline,
1610 int (*check_ready)(struct ata_link *link))
1612 struct ata_port *ap = link->ap;
1613 const char *reason = NULL;
1614 unsigned long now, msecs;
1615 struct ata_taskfile tf;
1620 /* prepare for SRST (AHCI-1.1 10.4.1) */
1621 rc = ahci_kick_engine(ap, 1);
1622 if (rc && rc != -EOPNOTSUPP)
1623 ata_link_printk(link, KERN_WARNING,
1624 "failed to reset engine (errno=%d)\n", rc);
1626 ata_tf_init(link->device, &tf);
1628 /* issue the first D2H Register FIS */
1631 if (time_after(now, deadline))
1632 msecs = jiffies_to_msecs(deadline - now);
1635 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1636 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1638 reason = "1st FIS failed";
1642 /* spec says at least 5us, but be generous and sleep for 1ms */
1645 /* issue the second D2H Register FIS */
1646 tf.ctl &= ~ATA_SRST;
1647 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1649 /* wait for link to become ready */
1650 rc = ata_wait_after_reset(link, deadline, check_ready);
1651 /* link occupied, -ENODEV too is an error */
1653 reason = "device not ready";
1656 *class = ahci_dev_classify(ap);
1658 DPRINTK("EXIT, class=%u\n", *class);
1662 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1666 static int ahci_check_ready(struct ata_link *link)
1668 void __iomem *port_mmio = ahci_port_base(link->ap);
1669 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1671 return ata_check_ready(status);
1674 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1675 unsigned long deadline)
1677 int pmp = sata_srst_pmp(link);
1681 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1684 static int ahci_sb600_check_ready(struct ata_link *link)
1686 void __iomem *port_mmio = ahci_port_base(link->ap);
1687 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1688 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1691 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1692 * which can save timeout delay.
1694 if (irq_status & PORT_IRQ_BAD_PMP)
1697 return ata_check_ready(status);
1700 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1701 unsigned long deadline)
1703 struct ata_port *ap = link->ap;
1704 void __iomem *port_mmio = ahci_port_base(ap);
1705 int pmp = sata_srst_pmp(link);
1711 rc = ahci_do_softreset(link, class, pmp, deadline,
1712 ahci_sb600_check_ready);
1715 * Soft reset fails on some ATI chips with IPMS set when PMP
1716 * is enabled but SATA HDD/ODD is connected to SATA port,
1717 * do soft reset again to port 0.
1720 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1721 if (irq_sts & PORT_IRQ_BAD_PMP) {
1722 ata_link_printk(link, KERN_WARNING,
1723 "failed due to HW bug, retry pmp=0\n");
1724 rc = ahci_do_softreset(link, class, 0, deadline,
1732 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1733 unsigned long deadline)
1735 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1736 struct ata_port *ap = link->ap;
1737 struct ahci_port_priv *pp = ap->private_data;
1738 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1739 struct ata_taskfile tf;
1745 ahci_stop_engine(ap);
1747 /* clear D2H reception area to properly wait for D2H FIS */
1748 ata_tf_init(link->device, &tf);
1750 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1752 rc = sata_link_hardreset(link, timing, deadline, &online,
1755 ahci_start_engine(ap);
1758 *class = ahci_dev_classify(ap);
1760 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1764 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1765 unsigned long deadline)
1767 struct ata_port *ap = link->ap;
1773 ahci_stop_engine(ap);
1775 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1776 deadline, &online, NULL);
1778 ahci_start_engine(ap);
1780 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1782 /* vt8251 doesn't clear BSY on signature FIS reception,
1783 * request follow-up softreset.
1785 return online ? -EAGAIN : rc;
1788 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1789 unsigned long deadline)
1791 struct ata_port *ap = link->ap;
1792 struct ahci_port_priv *pp = ap->private_data;
1793 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1794 struct ata_taskfile tf;
1798 ahci_stop_engine(ap);
1800 /* clear D2H reception area to properly wait for D2H FIS */
1801 ata_tf_init(link->device, &tf);
1803 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1805 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1806 deadline, &online, NULL);
1808 ahci_start_engine(ap);
1810 /* The pseudo configuration device on SIMG4726 attached to
1811 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1812 * hardreset if no device is attached to the first downstream
1813 * port && the pseudo device locks up on SRST w/ PMP==0. To
1814 * work around this, wait for !BSY only briefly. If BSY isn't
1815 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1816 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1818 * Wait for two seconds. Devices attached to downstream port
1819 * which can't process the following IDENTIFY after this will
1820 * have to be reset again. For most cases, this should
1821 * suffice while making probing snappish enough.
1824 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1827 ahci_kick_engine(ap, 0);
1832 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1834 struct ata_port *ap = link->ap;
1835 void __iomem *port_mmio = ahci_port_base(ap);
1838 ata_std_postreset(link, class);
1840 /* Make sure port's ATAPI bit is set appropriately */
1841 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1842 if (*class == ATA_DEV_ATAPI)
1843 new_tmp |= PORT_CMD_ATAPI;
1845 new_tmp &= ~PORT_CMD_ATAPI;
1846 if (new_tmp != tmp) {
1847 writel(new_tmp, port_mmio + PORT_CMD);
1848 readl(port_mmio + PORT_CMD); /* flush */
1852 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1854 struct scatterlist *sg;
1855 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1861 * Next, the S/G list.
1863 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1864 dma_addr_t addr = sg_dma_address(sg);
1865 u32 sg_len = sg_dma_len(sg);
1867 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1868 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1869 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1875 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1877 struct ata_port *ap = qc->ap;
1878 struct ahci_port_priv *pp = ap->private_data;
1879 int is_atapi = ata_is_atapi(qc->tf.protocol);
1882 const u32 cmd_fis_len = 5; /* five dwords */
1883 unsigned int n_elem;
1886 * Fill in command table information. First, the header,
1887 * a SATA Register - Host to Device command FIS.
1889 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1891 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1893 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1894 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1898 if (qc->flags & ATA_QCFLAG_DMAMAP)
1899 n_elem = ahci_fill_sg(qc, cmd_tbl);
1902 * Fill in command slot information.
1904 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1905 if (qc->tf.flags & ATA_TFLAG_WRITE)
1906 opts |= AHCI_CMD_WRITE;
1908 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1910 ahci_fill_cmd_slot(pp, qc->tag, opts);
1913 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1915 struct ahci_host_priv *hpriv = ap->host->private_data;
1916 struct ahci_port_priv *pp = ap->private_data;
1917 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1918 struct ata_link *link = NULL;
1919 struct ata_queued_cmd *active_qc;
1920 struct ata_eh_info *active_ehi;
1923 /* determine active link */
1924 ata_port_for_each_link(link, ap)
1925 if (ata_link_active(link))
1930 active_qc = ata_qc_from_tag(ap, link->active_tag);
1931 active_ehi = &link->eh_info;
1933 /* record irq stat */
1934 ata_ehi_clear_desc(host_ehi);
1935 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1937 /* AHCI needs SError cleared; otherwise, it might lock up */
1938 ahci_scr_read(ap, SCR_ERROR, &serror);
1939 ahci_scr_write(ap, SCR_ERROR, serror);
1940 host_ehi->serror |= serror;
1942 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1943 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1944 irq_stat &= ~PORT_IRQ_IF_ERR;
1946 if (irq_stat & PORT_IRQ_TF_ERR) {
1947 /* If qc is active, charge it; otherwise, the active
1948 * link. There's no active qc on NCQ errors. It will
1949 * be determined by EH by reading log page 10h.
1952 active_qc->err_mask |= AC_ERR_DEV;
1954 active_ehi->err_mask |= AC_ERR_DEV;
1956 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1957 host_ehi->serror &= ~SERR_INTERNAL;
1960 if (irq_stat & PORT_IRQ_UNK_FIS) {
1961 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1963 active_ehi->err_mask |= AC_ERR_HSM;
1964 active_ehi->action |= ATA_EH_RESET;
1965 ata_ehi_push_desc(active_ehi,
1966 "unknown FIS %08x %08x %08x %08x" ,
1967 unk[0], unk[1], unk[2], unk[3]);
1970 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1971 active_ehi->err_mask |= AC_ERR_HSM;
1972 active_ehi->action |= ATA_EH_RESET;
1973 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1976 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1977 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1978 host_ehi->action |= ATA_EH_RESET;
1979 ata_ehi_push_desc(host_ehi, "host bus error");
1982 if (irq_stat & PORT_IRQ_IF_ERR) {
1983 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1984 host_ehi->action |= ATA_EH_RESET;
1985 ata_ehi_push_desc(host_ehi, "interface fatal error");
1988 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1989 ata_ehi_hotplugged(host_ehi);
1990 ata_ehi_push_desc(host_ehi, "%s",
1991 irq_stat & PORT_IRQ_CONNECT ?
1992 "connection status changed" : "PHY RDY changed");
1995 /* okay, let's hand over to EH */
1997 if (irq_stat & PORT_IRQ_FREEZE)
1998 ata_port_freeze(ap);
2003 static void ahci_port_intr(struct ata_port *ap)
2005 void __iomem *port_mmio = ahci_port_base(ap);
2006 struct ata_eh_info *ehi = &ap->link.eh_info;
2007 struct ahci_port_priv *pp = ap->private_data;
2008 struct ahci_host_priv *hpriv = ap->host->private_data;
2009 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
2010 u32 status, qc_active;
2013 status = readl(port_mmio + PORT_IRQ_STAT);
2014 writel(status, port_mmio + PORT_IRQ_STAT);
2016 /* ignore BAD_PMP while resetting */
2017 if (unlikely(resetting))
2018 status &= ~PORT_IRQ_BAD_PMP;
2020 /* If we are getting PhyRdy, this is
2021 * just a power state change, we should
2022 * clear out this, plus the PhyRdy/Comm
2023 * Wake bits from Serror
2025 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2026 (status & PORT_IRQ_PHYRDY)) {
2027 status &= ~PORT_IRQ_PHYRDY;
2028 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
2031 if (unlikely(status & PORT_IRQ_ERROR)) {
2032 ahci_error_intr(ap, status);
2036 if (status & PORT_IRQ_SDB_FIS) {
2037 /* If SNotification is available, leave notification
2038 * handling to sata_async_notification(). If not,
2039 * emulate it by snooping SDB FIS RX area.
2041 * Snooping FIS RX area is probably cheaper than
2042 * poking SNotification but some constrollers which
2043 * implement SNotification, ICH9 for example, don't
2044 * store AN SDB FIS into receive area.
2046 if (hpriv->cap & HOST_CAP_SNTF)
2047 sata_async_notification(ap);
2049 /* If the 'N' bit in word 0 of the FIS is set,
2050 * we just received asynchronous notification.
2051 * Tell libata about it.
2053 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2054 u32 f0 = le32_to_cpu(f[0]);
2057 sata_async_notification(ap);
2061 /* pp->active_link is valid iff any command is in flight */
2062 if (ap->qc_active && pp->active_link->sactive)
2063 qc_active = readl(port_mmio + PORT_SCR_ACT);
2065 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2067 rc = ata_qc_complete_multiple(ap, qc_active);
2069 /* while resetting, invalid completions are expected */
2070 if (unlikely(rc < 0 && !resetting)) {
2071 ehi->err_mask |= AC_ERR_HSM;
2072 ehi->action |= ATA_EH_RESET;
2073 ata_port_freeze(ap);
2077 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
2079 struct ata_host *host = dev_instance;
2080 struct ahci_host_priv *hpriv;
2081 unsigned int i, handled = 0;
2083 u32 irq_stat, irq_masked;
2087 hpriv = host->private_data;
2088 mmio = host->iomap[AHCI_PCI_BAR];
2090 /* sigh. 0xffffffff is a valid return from h/w */
2091 irq_stat = readl(mmio + HOST_IRQ_STAT);
2095 irq_masked = irq_stat & hpriv->port_map;
2097 spin_lock(&host->lock);
2099 for (i = 0; i < host->n_ports; i++) {
2100 struct ata_port *ap;
2102 if (!(irq_masked & (1 << i)))
2105 ap = host->ports[i];
2108 VPRINTK("port %u\n", i);
2110 VPRINTK("port %u (no irq)\n", i);
2111 if (ata_ratelimit())
2112 dev_printk(KERN_WARNING, host->dev,
2113 "interrupt on disabled port %u\n", i);
2119 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2120 * it should be cleared after all the port events are cleared;
2121 * otherwise, it will raise a spurious interrupt after each
2122 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2125 * Also, use the unmasked value to clear interrupt as spurious
2126 * pending event on a dummy port might cause screaming IRQ.
2128 writel(irq_stat, mmio + HOST_IRQ_STAT);
2130 spin_unlock(&host->lock);
2134 return IRQ_RETVAL(handled);
2137 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2139 struct ata_port *ap = qc->ap;
2140 void __iomem *port_mmio = ahci_port_base(ap);
2141 struct ahci_port_priv *pp = ap->private_data;
2143 /* Keep track of the currently active link. It will be used
2144 * in completion path to determine whether NCQ phase is in
2147 pp->active_link = qc->dev->link;
2149 if (qc->tf.protocol == ATA_PROT_NCQ)
2150 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2151 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2153 ahci_sw_activity(qc->dev->link);
2158 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2160 struct ahci_port_priv *pp = qc->ap->private_data;
2161 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2163 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2167 static void ahci_freeze(struct ata_port *ap)
2169 void __iomem *port_mmio = ahci_port_base(ap);
2172 writel(0, port_mmio + PORT_IRQ_MASK);
2175 static void ahci_thaw(struct ata_port *ap)
2177 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
2178 void __iomem *port_mmio = ahci_port_base(ap);
2180 struct ahci_port_priv *pp = ap->private_data;
2183 tmp = readl(port_mmio + PORT_IRQ_STAT);
2184 writel(tmp, port_mmio + PORT_IRQ_STAT);
2185 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2187 /* turn IRQ back on */
2188 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2191 static void ahci_error_handler(struct ata_port *ap)
2193 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2194 /* restart engine */
2195 ahci_stop_engine(ap);
2196 ahci_start_engine(ap);
2199 sata_pmp_error_handler(ap);
2202 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2204 struct ata_port *ap = qc->ap;
2206 /* make DMA engine forget about the failed command */
2207 if (qc->flags & ATA_QCFLAG_FAILED)
2208 ahci_kick_engine(ap, 1);
2211 static void ahci_pmp_attach(struct ata_port *ap)
2213 void __iomem *port_mmio = ahci_port_base(ap);
2214 struct ahci_port_priv *pp = ap->private_data;
2217 cmd = readl(port_mmio + PORT_CMD);
2218 cmd |= PORT_CMD_PMP;
2219 writel(cmd, port_mmio + PORT_CMD);
2221 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2222 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2225 static void ahci_pmp_detach(struct ata_port *ap)
2227 void __iomem *port_mmio = ahci_port_base(ap);
2228 struct ahci_port_priv *pp = ap->private_data;
2231 cmd = readl(port_mmio + PORT_CMD);
2232 cmd &= ~PORT_CMD_PMP;
2233 writel(cmd, port_mmio + PORT_CMD);
2235 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2236 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2239 static int ahci_port_resume(struct ata_port *ap)
2242 ahci_start_port(ap);
2244 if (sata_pmp_attached(ap))
2245 ahci_pmp_attach(ap);
2247 ahci_pmp_detach(ap);
2253 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2255 const char *emsg = NULL;
2258 rc = ahci_deinit_port(ap, &emsg);
2260 ahci_power_down(ap);
2262 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2263 ahci_start_port(ap);
2269 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2271 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2272 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2275 if (mesg.event & PM_EVENT_SLEEP) {
2276 /* AHCI spec rev1.1 section 8.3.3:
2277 * Software must disable interrupts prior to requesting a
2278 * transition of the HBA to D3 state.
2280 ctl = readl(mmio + HOST_CTL);
2281 ctl &= ~HOST_IRQ_EN;
2282 writel(ctl, mmio + HOST_CTL);
2283 readl(mmio + HOST_CTL); /* flush */
2286 return ata_pci_device_suspend(pdev, mesg);
2289 static int ahci_pci_device_resume(struct pci_dev *pdev)
2291 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2294 rc = ata_pci_device_do_resume(pdev);
2298 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2299 rc = ahci_reset_controller(host);
2303 ahci_init_controller(host);
2306 ata_host_resume(host);
2312 static int ahci_port_start(struct ata_port *ap)
2314 struct device *dev = ap->host->dev;
2315 struct ahci_port_priv *pp;
2319 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2323 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2327 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2330 * First item in chunk of DMA memory: 32-slot command table,
2331 * 32 bytes each in size
2334 pp->cmd_slot_dma = mem_dma;
2336 mem += AHCI_CMD_SLOT_SZ;
2337 mem_dma += AHCI_CMD_SLOT_SZ;
2340 * Second item: Received-FIS area
2343 pp->rx_fis_dma = mem_dma;
2345 mem += AHCI_RX_FIS_SZ;
2346 mem_dma += AHCI_RX_FIS_SZ;
2349 * Third item: data area for storing a single command
2350 * and its scatter-gather table
2353 pp->cmd_tbl_dma = mem_dma;
2356 * Save off initial list of interrupts to be enabled.
2357 * This could be changed later
2359 pp->intr_mask = DEF_PORT_IRQ;
2361 ap->private_data = pp;
2363 /* engage engines, captain */
2364 return ahci_port_resume(ap);
2367 static void ahci_port_stop(struct ata_port *ap)
2369 const char *emsg = NULL;
2372 /* de-initialize port */
2373 rc = ahci_deinit_port(ap, &emsg);
2375 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2378 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2383 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2384 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2386 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2388 dev_printk(KERN_ERR, &pdev->dev,
2389 "64-bit DMA enable failed\n");
2394 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2396 dev_printk(KERN_ERR, &pdev->dev,
2397 "32-bit DMA enable failed\n");
2400 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2402 dev_printk(KERN_ERR, &pdev->dev,
2403 "32-bit consistent DMA enable failed\n");
2410 static void ahci_print_info(struct ata_host *host)
2412 struct ahci_host_priv *hpriv = host->private_data;
2413 struct pci_dev *pdev = to_pci_dev(host->dev);
2414 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2415 u32 vers, cap, impl, speed;
2416 const char *speed_s;
2420 vers = readl(mmio + HOST_VERSION);
2422 impl = hpriv->port_map;
2424 speed = (cap >> 20) & 0xf;
2427 else if (speed == 2)
2432 pci_read_config_word(pdev, 0x0a, &cc);
2433 if (cc == PCI_CLASS_STORAGE_IDE)
2435 else if (cc == PCI_CLASS_STORAGE_SATA)
2437 else if (cc == PCI_CLASS_STORAGE_RAID)
2442 dev_printk(KERN_INFO, &pdev->dev,
2443 "AHCI %02x%02x.%02x%02x "
2444 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2447 (vers >> 24) & 0xff,
2448 (vers >> 16) & 0xff,
2452 ((cap >> 8) & 0x1f) + 1,
2458 dev_printk(KERN_INFO, &pdev->dev,
2465 cap & (1 << 31) ? "64bit " : "",
2466 cap & (1 << 30) ? "ncq " : "",
2467 cap & (1 << 29) ? "sntf " : "",
2468 cap & (1 << 28) ? "ilck " : "",
2469 cap & (1 << 27) ? "stag " : "",
2470 cap & (1 << 26) ? "pm " : "",
2471 cap & (1 << 25) ? "led " : "",
2473 cap & (1 << 24) ? "clo " : "",
2474 cap & (1 << 19) ? "nz " : "",
2475 cap & (1 << 18) ? "only " : "",
2476 cap & (1 << 17) ? "pmp " : "",
2477 cap & (1 << 15) ? "pio " : "",
2478 cap & (1 << 14) ? "slum " : "",
2479 cap & (1 << 13) ? "part " : "",
2480 cap & (1 << 6) ? "ems ": ""
2484 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2485 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2486 * support PMP and the 4726 either directly exports the device
2487 * attached to the first downstream port or acts as a hardware storage
2488 * controller and emulate a single ATA device (can be RAID 0/1 or some
2489 * other configuration).
2491 * When there's no device attached to the first downstream port of the
2492 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2493 * configure the 4726. However, ATA emulation of the device is very
2494 * lame. It doesn't send signature D2H Reg FIS after the initial
2495 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2497 * The following function works around the problem by always using
2498 * hardreset on the port and not depending on receiving signature FIS
2499 * afterward. If signature FIS isn't received soon, ATA class is
2500 * assumed without follow-up softreset.
2502 static void ahci_p5wdh_workaround(struct ata_host *host)
2504 static struct dmi_system_id sysids[] = {
2506 .ident = "P5W DH Deluxe",
2508 DMI_MATCH(DMI_SYS_VENDOR,
2509 "ASUSTEK COMPUTER INC"),
2510 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2515 struct pci_dev *pdev = to_pci_dev(host->dev);
2517 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2518 dmi_check_system(sysids)) {
2519 struct ata_port *ap = host->ports[1];
2521 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2522 "Deluxe on-board SIMG4726 workaround\n");
2524 ap->ops = &ahci_p5wdh_ops;
2525 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2529 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2531 static int printed_version;
2532 unsigned int board_id = ent->driver_data;
2533 struct ata_port_info pi = ahci_port_info[board_id];
2534 const struct ata_port_info *ppi[] = { &pi, NULL };
2535 struct device *dev = &pdev->dev;
2536 struct ahci_host_priv *hpriv;
2537 struct ata_host *host;
2542 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2544 if (!printed_version++)
2545 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2547 /* The AHCI driver can only drive the SATA ports, the PATA driver
2548 can drive them all so if both drivers are selected make sure
2549 AHCI stays out of the way */
2550 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2553 /* acquire resources */
2554 rc = pcim_enable_device(pdev);
2558 /* AHCI controllers often implement SFF compatible interface.
2559 * Grab all PCI BARs just in case.
2561 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2563 pcim_pin_device(pdev);
2567 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2568 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2571 /* ICH6s share the same PCI ID for both piix and ahci
2572 * modes. Enabling ahci mode while MAP indicates
2573 * combined mode is a bad idea. Yield to ata_piix.
2575 pci_read_config_byte(pdev, ICH_MAP, &map);
2577 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2578 "combined mode, can't enable AHCI mode\n");
2583 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2586 hpriv->flags |= (unsigned long)pi.private_data;
2588 /* MCP65 revision A1 and A2 can't do MSI */
2589 if (board_id == board_ahci_mcp65 &&
2590 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2591 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2593 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2596 /* save initial config */
2597 ahci_save_initial_config(pdev, hpriv);
2600 if (hpriv->cap & HOST_CAP_NCQ)
2601 pi.flags |= ATA_FLAG_NCQ;
2603 if (hpriv->cap & HOST_CAP_PMP)
2604 pi.flags |= ATA_FLAG_PMP;
2606 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2608 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2609 u32 em_loc = readl(mmio + HOST_EM_LOC);
2610 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2612 messages = (em_ctl & 0x000f0000) >> 16;
2614 /* we only support LED message type right now */
2615 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2617 hpriv->em_loc = ((em_loc >> 16) * 4);
2618 pi.flags |= ATA_FLAG_EM;
2619 if (!(em_ctl & EM_CTL_ALHD))
2620 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2624 /* CAP.NP sometimes indicate the index of the last enabled
2625 * port, at other times, that of the last possible port, so
2626 * determining the maximum port number requires looking at
2627 * both CAP.NP and port_map.
2629 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2631 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2634 host->iomap = pcim_iomap_table(pdev);
2635 host->private_data = hpriv;
2637 if (pi.flags & ATA_FLAG_EM)
2638 ahci_reset_em(host);
2640 for (i = 0; i < host->n_ports; i++) {
2641 struct ata_port *ap = host->ports[i];
2643 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2644 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2645 0x100 + ap->port_no * 0x80, "port");
2647 /* set initial link pm policy */
2648 ap->pm_policy = NOT_AVAILABLE;
2650 /* set enclosure management message type */
2651 if (ap->flags & ATA_FLAG_EM)
2652 ap->em_message_type = ahci_em_messages;
2655 /* disabled/not-implemented port */
2656 if (!(hpriv->port_map & (1 << i)))
2657 ap->ops = &ata_dummy_port_ops;
2660 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2661 ahci_p5wdh_workaround(host);
2663 /* initialize adapter */
2664 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2668 rc = ahci_reset_controller(host);
2672 ahci_init_controller(host);
2673 ahci_print_info(host);
2675 pci_set_master(pdev);
2676 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2680 static int __init ahci_init(void)
2682 return pci_register_driver(&ahci_pci_driver);
2685 static void __exit ahci_exit(void)
2687 pci_unregister_driver(&ahci_pci_driver);
2691 MODULE_AUTHOR("Jeff Garzik");
2692 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2693 MODULE_LICENSE("GPL");
2694 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2695 MODULE_VERSION(DRV_VERSION);
2697 module_init(ahci_init);
2698 module_exit(ahci_exit);