2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.3"
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 1,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
80 board_ahci_vt8251 = 1,
81 board_ahci_ign_iferr = 2,
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
101 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
102 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
103 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
105 /* registers for each SATA port */
106 PORT_LST_ADDR = 0x00, /* command list DMA addr */
107 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
108 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
109 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
110 PORT_IRQ_STAT = 0x10, /* interrupt status */
111 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
112 PORT_CMD = 0x18, /* port command */
113 PORT_TFDATA = 0x20, /* taskfile data */
114 PORT_SIG = 0x24, /* device TF signature */
115 PORT_CMD_ISSUE = 0x38, /* command issue */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
120 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
122 /* PORT_IRQ_{STAT,MASK} bits */
123 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
124 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
125 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
126 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
127 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
128 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
129 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
130 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
132 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
133 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
134 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
135 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
136 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
137 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
138 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
139 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
140 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
142 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
147 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
149 PORT_IRQ_HBUS_DATA_ERR,
150 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
151 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
152 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
155 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
156 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
157 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
158 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
159 PORT_CMD_CLO = (1 << 3), /* Command list override */
160 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
161 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
162 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
164 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
165 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
166 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
167 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
170 AHCI_FLAG_NO_NCQ = (1 << 24),
171 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
172 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
173 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
174 AHCI_FLAG_MV_PATA = (1 << 29), /* PATA port */
175 AHCI_FLAG_NO_MSI = (1 << 30), /* no PCI MSI */
176 AHCI_FLAG_NO_HOTPLUG = (1 << 31), /* ignore PxSERR.DIAG.N */
178 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
179 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
180 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
181 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
184 struct ahci_cmd_hdr {
199 struct ahci_host_priv {
200 u32 cap; /* cap to use */
201 u32 port_map; /* port map to use */
202 u32 saved_cap; /* saved initial cap */
203 u32 saved_port_map; /* saved initial port_map */
206 struct ahci_port_priv {
207 struct ahci_cmd_hdr *cmd_slot;
208 dma_addr_t cmd_slot_dma;
210 dma_addr_t cmd_tbl_dma;
212 dma_addr_t rx_fis_dma;
213 /* for NCQ spurious interrupt analysis */
214 unsigned int ncq_saw_d2h:1;
215 unsigned int ncq_saw_dmas:1;
216 unsigned int ncq_saw_sdb:1;
217 u32 intr_mask; /* interrupts to enable */
220 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
221 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
222 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
223 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
224 static void ahci_irq_clear(struct ata_port *ap);
225 static int ahci_port_start(struct ata_port *ap);
226 static void ahci_port_stop(struct ata_port *ap);
227 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
228 static void ahci_qc_prep(struct ata_queued_cmd *qc);
229 static u8 ahci_check_status(struct ata_port *ap);
230 static void ahci_freeze(struct ata_port *ap);
231 static void ahci_thaw(struct ata_port *ap);
232 static void ahci_error_handler(struct ata_port *ap);
233 static void ahci_vt8251_error_handler(struct ata_port *ap);
234 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
235 static int ahci_port_resume(struct ata_port *ap);
236 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
237 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
240 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
241 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
242 static int ahci_pci_device_resume(struct pci_dev *pdev);
245 static struct scsi_host_template ahci_sht = {
246 .module = THIS_MODULE,
248 .ioctl = ata_scsi_ioctl,
249 .queuecommand = ata_scsi_queuecmd,
250 .change_queue_depth = ata_scsi_change_queue_depth,
251 .can_queue = AHCI_MAX_CMDS - 1,
252 .this_id = ATA_SHT_THIS_ID,
253 .sg_tablesize = AHCI_MAX_SG,
254 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
255 .emulated = ATA_SHT_EMULATED,
256 .use_clustering = AHCI_USE_CLUSTERING,
257 .proc_name = DRV_NAME,
258 .dma_boundary = AHCI_DMA_BOUNDARY,
259 .slave_configure = ata_scsi_slave_config,
260 .slave_destroy = ata_scsi_slave_destroy,
261 .bios_param = ata_std_bios_param,
264 static const struct ata_port_operations ahci_ops = {
265 .check_status = ahci_check_status,
266 .check_altstatus = ahci_check_status,
267 .dev_select = ata_noop_dev_select,
269 .tf_read = ahci_tf_read,
271 .qc_defer = ata_std_qc_defer,
272 .qc_prep = ahci_qc_prep,
273 .qc_issue = ahci_qc_issue,
275 .irq_clear = ahci_irq_clear,
277 .scr_read = ahci_scr_read,
278 .scr_write = ahci_scr_write,
280 .freeze = ahci_freeze,
283 .error_handler = ahci_error_handler,
284 .post_internal_cmd = ahci_post_internal_cmd,
287 .port_suspend = ahci_port_suspend,
288 .port_resume = ahci_port_resume,
291 .port_start = ahci_port_start,
292 .port_stop = ahci_port_stop,
295 static const struct ata_port_operations ahci_vt8251_ops = {
296 .check_status = ahci_check_status,
297 .check_altstatus = ahci_check_status,
298 .dev_select = ata_noop_dev_select,
300 .tf_read = ahci_tf_read,
302 .qc_defer = ata_std_qc_defer,
303 .qc_prep = ahci_qc_prep,
304 .qc_issue = ahci_qc_issue,
306 .irq_clear = ahci_irq_clear,
308 .scr_read = ahci_scr_read,
309 .scr_write = ahci_scr_write,
311 .freeze = ahci_freeze,
314 .error_handler = ahci_vt8251_error_handler,
315 .post_internal_cmd = ahci_post_internal_cmd,
318 .port_suspend = ahci_port_suspend,
319 .port_resume = ahci_port_resume,
322 .port_start = ahci_port_start,
323 .port_stop = ahci_port_stop,
326 static const struct ata_port_info ahci_port_info[] = {
329 .flags = AHCI_FLAG_COMMON,
330 .link_flags = AHCI_LFLAG_COMMON,
331 .pio_mask = 0x1f, /* pio0-4 */
332 .udma_mask = ATA_UDMA6,
333 .port_ops = &ahci_ops,
335 /* board_ahci_vt8251 */
337 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_NO_NCQ,
338 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
339 .pio_mask = 0x1f, /* pio0-4 */
340 .udma_mask = ATA_UDMA6,
341 .port_ops = &ahci_vt8251_ops,
343 /* board_ahci_ign_iferr */
345 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
346 .link_flags = AHCI_LFLAG_COMMON,
347 .pio_mask = 0x1f, /* pio0-4 */
348 .udma_mask = ATA_UDMA6,
349 .port_ops = &ahci_ops,
351 /* board_ahci_sb600 */
353 .flags = AHCI_FLAG_COMMON |
354 AHCI_FLAG_IGN_SERR_INTERNAL |
355 AHCI_FLAG_32BIT_ONLY,
356 .link_flags = AHCI_LFLAG_COMMON,
357 .pio_mask = 0x1f, /* pio0-4 */
358 .udma_mask = ATA_UDMA6,
359 .port_ops = &ahci_ops,
364 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
365 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
366 AHCI_FLAG_NO_NCQ | AHCI_FLAG_NO_MSI |
368 .link_flags = AHCI_LFLAG_COMMON,
369 .pio_mask = 0x1f, /* pio0-4 */
370 .udma_mask = ATA_UDMA6,
371 .port_ops = &ahci_ops,
375 static const struct pci_device_id ahci_pci_tbl[] = {
377 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
378 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
379 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
380 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
381 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
382 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
383 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
384 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
385 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
386 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
387 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
388 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
389 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
390 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
391 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
392 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
393 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
394 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
395 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
396 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
397 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
398 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
399 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
400 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
401 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
402 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
403 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
404 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
405 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
407 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
408 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
409 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
412 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
413 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
414 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
415 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
416 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
417 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
418 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
421 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
422 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
425 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
427 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
428 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
429 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
430 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
431 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
432 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
433 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
439 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
440 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
441 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
442 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
443 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
444 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
445 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
446 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
447 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
448 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
449 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
450 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
451 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
452 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
453 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
454 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
458 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
459 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
460 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
461 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
462 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
463 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
464 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
465 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
471 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
472 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
473 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
476 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
478 /* Generic, PCI class code for AHCI */
479 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
480 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
482 { } /* terminate list */
486 static struct pci_driver ahci_pci_driver = {
488 .id_table = ahci_pci_tbl,
489 .probe = ahci_init_one,
490 .remove = ata_pci_remove_one,
492 .suspend = ahci_pci_device_suspend,
493 .resume = ahci_pci_device_resume,
498 static inline int ahci_nr_ports(u32 cap)
500 return (cap & 0x1f) + 1;
503 static inline void __iomem *__ahci_port_base(struct ata_host *host,
504 unsigned int port_no)
506 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
508 return mmio + 0x100 + (port_no * 0x80);
511 static inline void __iomem *ahci_port_base(struct ata_port *ap)
513 return __ahci_port_base(ap->host, ap->port_no);
517 * ahci_save_initial_config - Save and fixup initial config values
518 * @pdev: target PCI device
519 * @pi: associated ATA port info
520 * @hpriv: host private area to store config values
522 * Some registers containing configuration info might be setup by
523 * BIOS and might be cleared on reset. This function saves the
524 * initial values of those registers into @hpriv such that they
525 * can be restored after controller reset.
527 * If inconsistent, config values are fixed up by this function.
532 static void ahci_save_initial_config(struct pci_dev *pdev,
533 const struct ata_port_info *pi,
534 struct ahci_host_priv *hpriv)
536 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
540 /* Values prefixed with saved_ are written back to host after
541 * reset. Values without are used for driver operation.
543 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
544 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
546 /* some chips have errata preventing 64bit use */
547 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
548 dev_printk(KERN_INFO, &pdev->dev,
549 "controller can't do 64bit DMA, forcing 32bit\n");
553 if ((cap & HOST_CAP_NCQ) && (pi->flags & AHCI_FLAG_NO_NCQ)) {
554 dev_printk(KERN_INFO, &pdev->dev,
555 "controller can't do NCQ, turning off CAP_NCQ\n");
556 cap &= ~HOST_CAP_NCQ;
560 * Temporary Marvell 6145 hack: PATA port presence
561 * is asserted through the standard AHCI port
562 * presence register, as bit 4 (counting from 0)
564 if (pi->flags & AHCI_FLAG_MV_PATA) {
565 dev_printk(KERN_ERR, &pdev->dev,
566 "MV_AHCI HACK: port_map %x -> %x\n",
568 hpriv->port_map & 0xf);
573 /* cross check port_map and cap.n_ports */
575 u32 tmp_port_map = port_map;
576 int n_ports = ahci_nr_ports(cap);
578 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
579 if (tmp_port_map & (1 << i)) {
581 tmp_port_map &= ~(1 << i);
585 /* If n_ports and port_map are inconsistent, whine and
586 * clear port_map and let it be generated from n_ports.
588 if (n_ports || tmp_port_map) {
589 dev_printk(KERN_WARNING, &pdev->dev,
590 "nr_ports (%u) and implemented port map "
591 "(0x%x) don't match, using nr_ports\n",
592 ahci_nr_ports(cap), port_map);
597 /* fabricate port_map from cap.nr_ports */
599 port_map = (1 << ahci_nr_ports(cap)) - 1;
600 dev_printk(KERN_WARNING, &pdev->dev,
601 "forcing PORTS_IMPL to 0x%x\n", port_map);
603 /* write the fixed up value to the PI register */
604 hpriv->saved_port_map = port_map;
607 /* record values to use during operation */
609 hpriv->port_map = port_map;
613 * ahci_restore_initial_config - Restore initial config
614 * @host: target ATA host
616 * Restore initial config stored by ahci_save_initial_config().
621 static void ahci_restore_initial_config(struct ata_host *host)
623 struct ahci_host_priv *hpriv = host->private_data;
624 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
626 writel(hpriv->saved_cap, mmio + HOST_CAP);
627 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
628 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
631 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
633 static const int offset[] = {
634 [SCR_STATUS] = PORT_SCR_STAT,
635 [SCR_CONTROL] = PORT_SCR_CTL,
636 [SCR_ERROR] = PORT_SCR_ERR,
637 [SCR_ACTIVE] = PORT_SCR_ACT,
638 [SCR_NOTIFICATION] = PORT_SCR_NTF,
640 struct ahci_host_priv *hpriv = ap->host->private_data;
642 if (sc_reg < ARRAY_SIZE(offset) &&
643 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
644 return offset[sc_reg];
648 static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
650 void __iomem *port_mmio = ahci_port_base(ap);
651 int offset = ahci_scr_offset(ap, sc_reg);
654 *val = readl(port_mmio + offset);
660 static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
662 void __iomem *port_mmio = ahci_port_base(ap);
663 int offset = ahci_scr_offset(ap, sc_reg);
666 writel(val, port_mmio + offset);
672 static void ahci_start_engine(struct ata_port *ap)
674 void __iomem *port_mmio = ahci_port_base(ap);
678 tmp = readl(port_mmio + PORT_CMD);
679 tmp |= PORT_CMD_START;
680 writel(tmp, port_mmio + PORT_CMD);
681 readl(port_mmio + PORT_CMD); /* flush */
684 static int ahci_stop_engine(struct ata_port *ap)
686 void __iomem *port_mmio = ahci_port_base(ap);
689 tmp = readl(port_mmio + PORT_CMD);
691 /* check if the HBA is idle */
692 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
695 /* setting HBA to idle */
696 tmp &= ~PORT_CMD_START;
697 writel(tmp, port_mmio + PORT_CMD);
699 /* wait for engine to stop. This could be as long as 500 msec */
700 tmp = ata_wait_register(port_mmio + PORT_CMD,
701 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
702 if (tmp & PORT_CMD_LIST_ON)
708 static void ahci_start_fis_rx(struct ata_port *ap)
710 void __iomem *port_mmio = ahci_port_base(ap);
711 struct ahci_host_priv *hpriv = ap->host->private_data;
712 struct ahci_port_priv *pp = ap->private_data;
715 /* set FIS registers */
716 if (hpriv->cap & HOST_CAP_64)
717 writel((pp->cmd_slot_dma >> 16) >> 16,
718 port_mmio + PORT_LST_ADDR_HI);
719 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
721 if (hpriv->cap & HOST_CAP_64)
722 writel((pp->rx_fis_dma >> 16) >> 16,
723 port_mmio + PORT_FIS_ADDR_HI);
724 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
726 /* enable FIS reception */
727 tmp = readl(port_mmio + PORT_CMD);
728 tmp |= PORT_CMD_FIS_RX;
729 writel(tmp, port_mmio + PORT_CMD);
732 readl(port_mmio + PORT_CMD);
735 static int ahci_stop_fis_rx(struct ata_port *ap)
737 void __iomem *port_mmio = ahci_port_base(ap);
740 /* disable FIS reception */
741 tmp = readl(port_mmio + PORT_CMD);
742 tmp &= ~PORT_CMD_FIS_RX;
743 writel(tmp, port_mmio + PORT_CMD);
745 /* wait for completion, spec says 500ms, give it 1000 */
746 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
747 PORT_CMD_FIS_ON, 10, 1000);
748 if (tmp & PORT_CMD_FIS_ON)
754 static void ahci_power_up(struct ata_port *ap)
756 struct ahci_host_priv *hpriv = ap->host->private_data;
757 void __iomem *port_mmio = ahci_port_base(ap);
760 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
763 if (hpriv->cap & HOST_CAP_SSS) {
764 cmd |= PORT_CMD_SPIN_UP;
765 writel(cmd, port_mmio + PORT_CMD);
769 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
773 static void ahci_power_down(struct ata_port *ap)
775 struct ahci_host_priv *hpriv = ap->host->private_data;
776 void __iomem *port_mmio = ahci_port_base(ap);
779 if (!(hpriv->cap & HOST_CAP_SSS))
782 /* put device into listen mode, first set PxSCTL.DET to 0 */
783 scontrol = readl(port_mmio + PORT_SCR_CTL);
785 writel(scontrol, port_mmio + PORT_SCR_CTL);
787 /* then set PxCMD.SUD to 0 */
788 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
789 cmd &= ~PORT_CMD_SPIN_UP;
790 writel(cmd, port_mmio + PORT_CMD);
794 static void ahci_start_port(struct ata_port *ap)
796 /* enable FIS reception */
797 ahci_start_fis_rx(ap);
800 ahci_start_engine(ap);
803 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
808 rc = ahci_stop_engine(ap);
810 *emsg = "failed to stop engine";
814 /* disable FIS reception */
815 rc = ahci_stop_fis_rx(ap);
817 *emsg = "failed stop FIS RX";
824 static int ahci_reset_controller(struct ata_host *host)
826 struct pci_dev *pdev = to_pci_dev(host->dev);
827 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
830 /* we must be in AHCI mode, before using anything
831 * AHCI-specific, such as HOST_RESET.
833 tmp = readl(mmio + HOST_CTL);
834 if (!(tmp & HOST_AHCI_EN))
835 writel(tmp | HOST_AHCI_EN, mmio + HOST_CTL);
837 /* global controller reset */
838 if ((tmp & HOST_RESET) == 0) {
839 writel(tmp | HOST_RESET, mmio + HOST_CTL);
840 readl(mmio + HOST_CTL); /* flush */
843 /* reset must complete within 1 second, or
844 * the hardware should be considered fried.
848 tmp = readl(mmio + HOST_CTL);
849 if (tmp & HOST_RESET) {
850 dev_printk(KERN_ERR, host->dev,
851 "controller reset failed (0x%x)\n", tmp);
855 /* turn on AHCI mode */
856 writel(HOST_AHCI_EN, mmio + HOST_CTL);
857 (void) readl(mmio + HOST_CTL); /* flush */
859 /* some registers might be cleared on reset. restore initial values */
860 ahci_restore_initial_config(host);
862 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
866 pci_read_config_word(pdev, 0x92, &tmp16);
868 pci_write_config_word(pdev, 0x92, tmp16);
874 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
875 int port_no, void __iomem *mmio,
876 void __iomem *port_mmio)
878 const char *emsg = NULL;
882 /* make sure port is not active */
883 rc = ahci_deinit_port(ap, &emsg);
885 dev_printk(KERN_WARNING, &pdev->dev,
886 "%s (%d)\n", emsg, rc);
889 tmp = readl(port_mmio + PORT_SCR_ERR);
890 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
891 writel(tmp, port_mmio + PORT_SCR_ERR);
894 tmp = readl(port_mmio + PORT_IRQ_STAT);
895 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
897 writel(tmp, port_mmio + PORT_IRQ_STAT);
899 writel(1 << port_no, mmio + HOST_IRQ_STAT);
902 static void ahci_init_controller(struct ata_host *host)
904 struct pci_dev *pdev = to_pci_dev(host->dev);
905 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
907 void __iomem *port_mmio;
910 if (host->ports[0]->flags & AHCI_FLAG_MV_PATA) {
911 port_mmio = __ahci_port_base(host, 4);
913 writel(0, port_mmio + PORT_IRQ_MASK);
916 tmp = readl(port_mmio + PORT_IRQ_STAT);
917 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
919 writel(tmp, port_mmio + PORT_IRQ_STAT);
922 for (i = 0; i < host->n_ports; i++) {
923 struct ata_port *ap = host->ports[i];
925 port_mmio = ahci_port_base(ap);
926 if (ata_port_is_dummy(ap))
929 ahci_port_init(pdev, ap, i, mmio, port_mmio);
932 tmp = readl(mmio + HOST_CTL);
933 VPRINTK("HOST_CTL 0x%x\n", tmp);
934 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
935 tmp = readl(mmio + HOST_CTL);
936 VPRINTK("HOST_CTL 0x%x\n", tmp);
939 static unsigned int ahci_dev_classify(struct ata_port *ap)
941 void __iomem *port_mmio = ahci_port_base(ap);
942 struct ata_taskfile tf;
945 tmp = readl(port_mmio + PORT_SIG);
946 tf.lbah = (tmp >> 24) & 0xff;
947 tf.lbam = (tmp >> 16) & 0xff;
948 tf.lbal = (tmp >> 8) & 0xff;
949 tf.nsect = (tmp) & 0xff;
951 return ata_dev_classify(&tf);
954 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
957 dma_addr_t cmd_tbl_dma;
959 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
961 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
962 pp->cmd_slot[tag].status = 0;
963 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
964 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
967 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
969 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
970 struct ahci_host_priv *hpriv = ap->host->private_data;
974 /* do we need to kick the port? */
975 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
976 if (!busy && !force_restart)
980 rc = ahci_stop_engine(ap);
984 /* need to do CLO? */
990 if (!(hpriv->cap & HOST_CAP_CLO)) {
996 tmp = readl(port_mmio + PORT_CMD);
998 writel(tmp, port_mmio + PORT_CMD);
1001 tmp = ata_wait_register(port_mmio + PORT_CMD,
1002 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1003 if (tmp & PORT_CMD_CLO)
1006 /* restart engine */
1008 ahci_start_engine(ap);
1012 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1013 struct ata_taskfile *tf, int is_cmd, u16 flags,
1014 unsigned long timeout_msec)
1016 const u32 cmd_fis_len = 5; /* five dwords */
1017 struct ahci_port_priv *pp = ap->private_data;
1018 void __iomem *port_mmio = ahci_port_base(ap);
1019 u8 *fis = pp->cmd_tbl;
1022 /* prep the command */
1023 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1024 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1027 writel(1, port_mmio + PORT_CMD_ISSUE);
1030 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1033 ahci_kick_engine(ap, 1);
1037 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1042 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1043 int pmp, unsigned long deadline)
1045 struct ata_port *ap = link->ap;
1046 const char *reason = NULL;
1047 unsigned long now, msecs;
1048 struct ata_taskfile tf;
1053 if (ata_link_offline(link)) {
1054 DPRINTK("PHY reports no device\n");
1055 *class = ATA_DEV_NONE;
1059 /* prepare for SRST (AHCI-1.1 10.4.1) */
1060 rc = ahci_kick_engine(ap, 1);
1062 ata_link_printk(link, KERN_WARNING,
1063 "failed to reset engine (errno=%d)", rc);
1065 ata_tf_init(link->device, &tf);
1067 /* issue the first D2H Register FIS */
1070 if (time_after(now, deadline))
1071 msecs = jiffies_to_msecs(deadline - now);
1074 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1075 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1077 reason = "1st FIS failed";
1081 /* spec says at least 5us, but be generous and sleep for 1ms */
1084 /* issue the second D2H Register FIS */
1085 tf.ctl &= ~ATA_SRST;
1086 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1088 /* spec mandates ">= 2ms" before checking status.
1089 * We wait 150ms, because that was the magic delay used for
1090 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1091 * between when the ATA command register is written, and then
1092 * status is checked. Because waiting for "a while" before
1093 * checking status is fine, post SRST, we perform this magic
1094 * delay here as well.
1098 rc = ata_wait_ready(ap, deadline);
1099 /* link occupied, -ENODEV too is an error */
1101 reason = "device not ready";
1104 *class = ahci_dev_classify(ap);
1106 DPRINTK("EXIT, class=%u\n", *class);
1110 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1114 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1115 unsigned long deadline)
1117 return ahci_do_softreset(link, class, 0, deadline);
1120 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1121 unsigned long deadline)
1123 struct ata_port *ap = link->ap;
1124 struct ahci_port_priv *pp = ap->private_data;
1125 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1126 struct ata_taskfile tf;
1131 ahci_stop_engine(ap);
1133 /* clear D2H reception area to properly wait for D2H FIS */
1134 ata_tf_init(link->device, &tf);
1136 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1138 rc = sata_std_hardreset(link, class, deadline);
1140 ahci_start_engine(ap);
1142 if (rc == 0 && ata_link_online(link))
1143 *class = ahci_dev_classify(ap);
1144 if (*class == ATA_DEV_UNKNOWN)
1145 *class = ATA_DEV_NONE;
1147 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1151 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1152 unsigned long deadline)
1154 struct ata_port *ap = link->ap;
1160 ahci_stop_engine(ap);
1162 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1165 /* vt8251 needs SError cleared for the port to operate */
1166 ahci_scr_read(ap, SCR_ERROR, &serror);
1167 ahci_scr_write(ap, SCR_ERROR, serror);
1169 ahci_start_engine(ap);
1171 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1173 /* vt8251 doesn't clear BSY on signature FIS reception,
1174 * request follow-up softreset.
1176 return rc ?: -EAGAIN;
1179 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1181 struct ata_port *ap = link->ap;
1182 void __iomem *port_mmio = ahci_port_base(ap);
1185 ata_std_postreset(link, class);
1187 /* Make sure port's ATAPI bit is set appropriately */
1188 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1189 if (*class == ATA_DEV_ATAPI)
1190 new_tmp |= PORT_CMD_ATAPI;
1192 new_tmp &= ~PORT_CMD_ATAPI;
1193 if (new_tmp != tmp) {
1194 writel(new_tmp, port_mmio + PORT_CMD);
1195 readl(port_mmio + PORT_CMD); /* flush */
1199 static u8 ahci_check_status(struct ata_port *ap)
1201 void __iomem *mmio = ap->ioaddr.cmd_addr;
1203 return readl(mmio + PORT_TFDATA) & 0xFF;
1206 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1208 struct ahci_port_priv *pp = ap->private_data;
1209 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1211 ata_tf_from_fis(d2h_fis, tf);
1214 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1216 struct scatterlist *sg;
1217 struct ahci_sg *ahci_sg;
1218 unsigned int n_sg = 0;
1223 * Next, the S/G list.
1225 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1226 ata_for_each_sg(sg, qc) {
1227 dma_addr_t addr = sg_dma_address(sg);
1228 u32 sg_len = sg_dma_len(sg);
1230 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1231 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1232 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1241 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1243 struct ata_port *ap = qc->ap;
1244 struct ahci_port_priv *pp = ap->private_data;
1245 int is_atapi = is_atapi_taskfile(&qc->tf);
1248 const u32 cmd_fis_len = 5; /* five dwords */
1249 unsigned int n_elem;
1252 * Fill in command table information. First, the header,
1253 * a SATA Register - Host to Device command FIS.
1255 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1257 ata_tf_to_fis(&qc->tf, 0, 1, cmd_tbl);
1259 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1260 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1264 if (qc->flags & ATA_QCFLAG_DMAMAP)
1265 n_elem = ahci_fill_sg(qc, cmd_tbl);
1268 * Fill in command slot information.
1270 opts = cmd_fis_len | n_elem << 16;
1271 if (qc->tf.flags & ATA_TFLAG_WRITE)
1272 opts |= AHCI_CMD_WRITE;
1274 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1276 ahci_fill_cmd_slot(pp, qc->tag, opts);
1279 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1281 struct ahci_port_priv *pp = ap->private_data;
1282 struct ata_eh_info *ehi = &ap->link.eh_info;
1283 unsigned int err_mask = 0, action = 0;
1284 struct ata_queued_cmd *qc;
1287 ata_ehi_clear_desc(ehi);
1289 /* AHCI needs SError cleared; otherwise, it might lock up */
1290 ahci_scr_read(ap, SCR_ERROR, &serror);
1291 ahci_scr_write(ap, SCR_ERROR, serror);
1293 /* analyze @irq_stat */
1294 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1296 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1297 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1298 irq_stat &= ~PORT_IRQ_IF_ERR;
1300 if (irq_stat & PORT_IRQ_TF_ERR) {
1301 err_mask |= AC_ERR_DEV;
1302 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1303 serror &= ~SERR_INTERNAL;
1306 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1307 err_mask |= AC_ERR_HOST_BUS;
1308 action |= ATA_EH_SOFTRESET;
1311 if (irq_stat & PORT_IRQ_IF_ERR) {
1312 err_mask |= AC_ERR_ATA_BUS;
1313 action |= ATA_EH_SOFTRESET;
1314 ata_ehi_push_desc(ehi, "interface fatal error");
1317 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1318 ata_ehi_hotplugged(ehi);
1319 ata_ehi_push_desc(ehi, "%s", irq_stat & PORT_IRQ_CONNECT ?
1320 "connection status changed" : "PHY RDY changed");
1323 if (irq_stat & PORT_IRQ_UNK_FIS) {
1324 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1326 err_mask |= AC_ERR_HSM;
1327 action |= ATA_EH_SOFTRESET;
1328 ata_ehi_push_desc(ehi, "unknown FIS %08x %08x %08x %08x",
1329 unk[0], unk[1], unk[2], unk[3]);
1332 /* okay, let's hand over to EH */
1333 ehi->serror |= serror;
1334 ehi->action |= action;
1336 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1338 qc->err_mask |= err_mask;
1340 ehi->err_mask |= err_mask;
1342 if (irq_stat & PORT_IRQ_FREEZE)
1343 ata_port_freeze(ap);
1348 static void ahci_port_intr(struct ata_port *ap)
1350 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1351 struct ata_eh_info *ehi = &ap->link.eh_info;
1352 struct ahci_port_priv *pp = ap->private_data;
1353 u32 status, qc_active;
1354 int rc, known_irq = 0;
1356 status = readl(port_mmio + PORT_IRQ_STAT);
1357 writel(status, port_mmio + PORT_IRQ_STAT);
1359 if (unlikely(status & PORT_IRQ_ERROR)) {
1360 ahci_error_intr(ap, status);
1364 if (status & PORT_IRQ_SDB_FIS) {
1365 /* If the 'N' bit in word 0 of the FIS is set, we just
1366 * received asynchronous notification. Tell libata
1367 * about it. Note that as the SDB FIS itself is
1368 * accessible, SNotification can be emulated by the
1369 * driver but don't bother for the time being.
1371 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1372 u32 f0 = le32_to_cpu(f[0]);
1375 sata_async_notification(ap);
1378 if (ap->link.sactive)
1379 qc_active = readl(port_mmio + PORT_SCR_ACT);
1381 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1383 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1387 ehi->err_mask |= AC_ERR_HSM;
1388 ehi->action |= ATA_EH_SOFTRESET;
1389 ata_port_freeze(ap);
1393 /* hmmm... a spurious interupt */
1395 /* if !NCQ, ignore. No modern ATA device has broken HSM
1396 * implementation for non-NCQ commands.
1398 if (!ap->link.sactive)
1401 if (status & PORT_IRQ_D2H_REG_FIS) {
1402 if (!pp->ncq_saw_d2h)
1403 ata_port_printk(ap, KERN_INFO,
1404 "D2H reg with I during NCQ, "
1405 "this message won't be printed again\n");
1406 pp->ncq_saw_d2h = 1;
1410 if (status & PORT_IRQ_DMAS_FIS) {
1411 if (!pp->ncq_saw_dmas)
1412 ata_port_printk(ap, KERN_INFO,
1413 "DMAS FIS during NCQ, "
1414 "this message won't be printed again\n");
1415 pp->ncq_saw_dmas = 1;
1419 if (status & PORT_IRQ_SDB_FIS) {
1420 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1422 if (le32_to_cpu(f[1])) {
1423 /* SDB FIS containing spurious completions
1424 * might be dangerous, whine and fail commands
1425 * with HSM violation. EH will turn off NCQ
1426 * after several such failures.
1428 ata_ehi_push_desc(ehi,
1429 "spurious completions during NCQ "
1430 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1431 readl(port_mmio + PORT_CMD_ISSUE),
1432 readl(port_mmio + PORT_SCR_ACT),
1433 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1434 ehi->err_mask |= AC_ERR_HSM;
1435 ehi->action |= ATA_EH_SOFTRESET;
1436 ata_port_freeze(ap);
1438 if (!pp->ncq_saw_sdb)
1439 ata_port_printk(ap, KERN_INFO,
1440 "spurious SDB FIS %08x:%08x during NCQ, "
1441 "this message won't be printed again\n",
1442 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1443 pp->ncq_saw_sdb = 1;
1449 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1450 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1451 status, ap->link.active_tag, ap->link.sactive);
1454 static void ahci_irq_clear(struct ata_port *ap)
1459 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1461 struct ata_host *host = dev_instance;
1462 struct ahci_host_priv *hpriv;
1463 unsigned int i, handled = 0;
1465 u32 irq_stat, irq_ack = 0;
1469 hpriv = host->private_data;
1470 mmio = host->iomap[AHCI_PCI_BAR];
1472 /* sigh. 0xffffffff is a valid return from h/w */
1473 irq_stat = readl(mmio + HOST_IRQ_STAT);
1474 irq_stat &= hpriv->port_map;
1478 spin_lock(&host->lock);
1480 for (i = 0; i < host->n_ports; i++) {
1481 struct ata_port *ap;
1483 if (!(irq_stat & (1 << i)))
1486 ap = host->ports[i];
1489 VPRINTK("port %u\n", i);
1491 VPRINTK("port %u (no irq)\n", i);
1492 if (ata_ratelimit())
1493 dev_printk(KERN_WARNING, host->dev,
1494 "interrupt on disabled port %u\n", i);
1497 irq_ack |= (1 << i);
1501 writel(irq_ack, mmio + HOST_IRQ_STAT);
1505 spin_unlock(&host->lock);
1509 return IRQ_RETVAL(handled);
1512 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1514 struct ata_port *ap = qc->ap;
1515 void __iomem *port_mmio = ahci_port_base(ap);
1517 if (qc->tf.protocol == ATA_PROT_NCQ)
1518 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1519 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1520 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1525 static void ahci_freeze(struct ata_port *ap)
1527 void __iomem *port_mmio = ahci_port_base(ap);
1530 writel(0, port_mmio + PORT_IRQ_MASK);
1533 static void ahci_thaw(struct ata_port *ap)
1535 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1536 void __iomem *port_mmio = ahci_port_base(ap);
1538 struct ahci_port_priv *pp = ap->private_data;
1541 tmp = readl(port_mmio + PORT_IRQ_STAT);
1542 writel(tmp, port_mmio + PORT_IRQ_STAT);
1543 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1545 /* turn IRQ back on */
1546 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1549 static void ahci_error_handler(struct ata_port *ap)
1551 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1552 /* restart engine */
1553 ahci_stop_engine(ap);
1554 ahci_start_engine(ap);
1557 /* perform recovery */
1558 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1562 static void ahci_vt8251_error_handler(struct ata_port *ap)
1564 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1565 /* restart engine */
1566 ahci_stop_engine(ap);
1567 ahci_start_engine(ap);
1570 /* perform recovery */
1571 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1575 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1577 struct ata_port *ap = qc->ap;
1579 /* make DMA engine forget about the failed command */
1580 if (qc->flags & ATA_QCFLAG_FAILED)
1581 ahci_kick_engine(ap, 1);
1584 static int ahci_port_resume(struct ata_port *ap)
1587 ahci_start_port(ap);
1593 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1595 const char *emsg = NULL;
1598 rc = ahci_deinit_port(ap, &emsg);
1600 ahci_power_down(ap);
1602 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1603 ahci_start_port(ap);
1609 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1611 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1612 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1615 if (mesg.event == PM_EVENT_SUSPEND) {
1616 /* AHCI spec rev1.1 section 8.3.3:
1617 * Software must disable interrupts prior to requesting a
1618 * transition of the HBA to D3 state.
1620 ctl = readl(mmio + HOST_CTL);
1621 ctl &= ~HOST_IRQ_EN;
1622 writel(ctl, mmio + HOST_CTL);
1623 readl(mmio + HOST_CTL); /* flush */
1626 return ata_pci_device_suspend(pdev, mesg);
1629 static int ahci_pci_device_resume(struct pci_dev *pdev)
1631 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1634 rc = ata_pci_device_do_resume(pdev);
1638 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1639 rc = ahci_reset_controller(host);
1643 ahci_init_controller(host);
1646 ata_host_resume(host);
1652 static int ahci_port_start(struct ata_port *ap)
1654 struct device *dev = ap->host->dev;
1655 struct ahci_port_priv *pp;
1660 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1664 rc = ata_pad_alloc(ap, dev);
1668 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1672 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1675 * First item in chunk of DMA memory: 32-slot command table,
1676 * 32 bytes each in size
1679 pp->cmd_slot_dma = mem_dma;
1681 mem += AHCI_CMD_SLOT_SZ;
1682 mem_dma += AHCI_CMD_SLOT_SZ;
1685 * Second item: Received-FIS area
1688 pp->rx_fis_dma = mem_dma;
1690 mem += AHCI_RX_FIS_SZ;
1691 mem_dma += AHCI_RX_FIS_SZ;
1694 * Third item: data area for storing a single command
1695 * and its scatter-gather table
1698 pp->cmd_tbl_dma = mem_dma;
1701 * Save off initial list of interrupts to be enabled.
1702 * This could be changed later
1704 pp->intr_mask = DEF_PORT_IRQ;
1706 ap->private_data = pp;
1708 /* engage engines, captain */
1709 return ahci_port_resume(ap);
1712 static void ahci_port_stop(struct ata_port *ap)
1714 const char *emsg = NULL;
1717 /* de-initialize port */
1718 rc = ahci_deinit_port(ap, &emsg);
1720 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1723 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1728 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1729 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1731 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1733 dev_printk(KERN_ERR, &pdev->dev,
1734 "64-bit DMA enable failed\n");
1739 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1741 dev_printk(KERN_ERR, &pdev->dev,
1742 "32-bit DMA enable failed\n");
1745 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1747 dev_printk(KERN_ERR, &pdev->dev,
1748 "32-bit consistent DMA enable failed\n");
1755 static void ahci_print_info(struct ata_host *host)
1757 struct ahci_host_priv *hpriv = host->private_data;
1758 struct pci_dev *pdev = to_pci_dev(host->dev);
1759 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1760 u32 vers, cap, impl, speed;
1761 const char *speed_s;
1765 vers = readl(mmio + HOST_VERSION);
1767 impl = hpriv->port_map;
1769 speed = (cap >> 20) & 0xf;
1772 else if (speed == 2)
1777 pci_read_config_word(pdev, 0x0a, &cc);
1778 if (cc == PCI_CLASS_STORAGE_IDE)
1780 else if (cc == PCI_CLASS_STORAGE_SATA)
1782 else if (cc == PCI_CLASS_STORAGE_RAID)
1787 dev_printk(KERN_INFO, &pdev->dev,
1788 "AHCI %02x%02x.%02x%02x "
1789 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1792 (vers >> 24) & 0xff,
1793 (vers >> 16) & 0xff,
1797 ((cap >> 8) & 0x1f) + 1,
1803 dev_printk(KERN_INFO, &pdev->dev,
1809 cap & (1 << 31) ? "64bit " : "",
1810 cap & (1 << 30) ? "ncq " : "",
1811 cap & (1 << 29) ? "sntf " : "",
1812 cap & (1 << 28) ? "ilck " : "",
1813 cap & (1 << 27) ? "stag " : "",
1814 cap & (1 << 26) ? "pm " : "",
1815 cap & (1 << 25) ? "led " : "",
1817 cap & (1 << 24) ? "clo " : "",
1818 cap & (1 << 19) ? "nz " : "",
1819 cap & (1 << 18) ? "only " : "",
1820 cap & (1 << 17) ? "pmp " : "",
1821 cap & (1 << 15) ? "pio " : "",
1822 cap & (1 << 14) ? "slum " : "",
1823 cap & (1 << 13) ? "part " : ""
1827 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1829 static int printed_version;
1830 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1831 const struct ata_port_info *ppi[] = { &pi, NULL };
1832 struct device *dev = &pdev->dev;
1833 struct ahci_host_priv *hpriv;
1834 struct ata_host *host;
1839 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1841 if (!printed_version++)
1842 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1844 /* acquire resources */
1845 rc = pcim_enable_device(pdev);
1849 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1851 pcim_pin_device(pdev);
1855 if ((pi.flags & AHCI_FLAG_NO_MSI) || pci_enable_msi(pdev))
1858 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1862 /* save initial config */
1863 ahci_save_initial_config(pdev, &pi, hpriv);
1866 if (hpriv->cap & HOST_CAP_NCQ)
1867 pi.flags |= ATA_FLAG_NCQ;
1869 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1872 host->iomap = pcim_iomap_table(pdev);
1873 host->private_data = hpriv;
1875 for (i = 0; i < host->n_ports; i++) {
1876 struct ata_port *ap = host->ports[i];
1877 void __iomem *port_mmio = ahci_port_base(ap);
1879 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1880 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1881 0x100 + ap->port_no * 0x80, "port");
1883 /* standard SATA port setup */
1884 if (hpriv->port_map & (1 << i))
1885 ap->ioaddr.cmd_addr = port_mmio;
1887 /* disabled/not-implemented port */
1889 ap->ops = &ata_dummy_port_ops;
1892 /* initialize adapter */
1893 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1897 rc = ahci_reset_controller(host);
1901 ahci_init_controller(host);
1902 ahci_print_info(host);
1904 pci_set_master(pdev);
1905 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1909 static int __init ahci_init(void)
1911 return pci_register_driver(&ahci_pci_driver);
1914 static void __exit ahci_exit(void)
1916 pci_unregister_driver(&ahci_pci_driver);
1920 MODULE_AUTHOR("Jeff Garzik");
1921 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1922 MODULE_LICENSE("GPL");
1923 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1924 MODULE_VERSION(DRV_VERSION);
1926 module_init(ahci_init);
1927 module_exit(ahci_exit);