2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.2"
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 1,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
85 /* global controller registers */
86 HOST_CAP = 0x00, /* host capabilities */
87 HOST_CTL = 0x04, /* global host control */
88 HOST_IRQ_STAT = 0x08, /* interrupt status */
89 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
90 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
93 HOST_RESET = (1 << 0), /* reset controller; self-clear */
94 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
95 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
98 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
99 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
100 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
101 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
102 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
104 /* registers for each SATA port */
105 PORT_LST_ADDR = 0x00, /* command list DMA addr */
106 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
107 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
108 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
109 PORT_IRQ_STAT = 0x10, /* interrupt status */
110 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
111 PORT_CMD = 0x18, /* port command */
112 PORT_TFDATA = 0x20, /* taskfile data */
113 PORT_SIG = 0x24, /* device TF signature */
114 PORT_CMD_ISSUE = 0x38, /* command issue */
115 PORT_SCR = 0x28, /* SATA phy register block */
116 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
117 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
118 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
119 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
121 /* PORT_IRQ_{STAT,MASK} bits */
122 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
123 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
124 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
125 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
126 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
127 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
128 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
129 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
131 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
132 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
133 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
134 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
135 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
136 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
137 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
138 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
139 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
141 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
146 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
148 PORT_IRQ_HBUS_DATA_ERR,
149 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
150 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
151 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
154 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
155 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
156 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
157 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
158 PORT_CMD_CLO = (1 << 3), /* Command list override */
159 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
160 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
161 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
163 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
164 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
165 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
166 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
169 AHCI_FLAG_NO_NCQ = (1 << 24),
170 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
171 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
172 AHCI_FLAG_IGN_SERR_INTERNAL = (1 << 27), /* ignore SERR_INTERNAL */
173 AHCI_FLAG_32BIT_ONLY = (1 << 28), /* force 32bit */
175 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
176 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
177 ATA_FLAG_SKIP_D2H_BSY |
181 struct ahci_cmd_hdr {
196 struct ahci_host_priv {
197 u32 cap; /* cap to use */
198 u32 port_map; /* port map to use */
199 u32 saved_cap; /* saved initial cap */
200 u32 saved_port_map; /* saved initial port_map */
203 struct ahci_port_priv {
204 struct ahci_cmd_hdr *cmd_slot;
205 dma_addr_t cmd_slot_dma;
207 dma_addr_t cmd_tbl_dma;
209 dma_addr_t rx_fis_dma;
210 /* for NCQ spurious interrupt analysis */
211 unsigned int ncq_saw_d2h:1;
212 unsigned int ncq_saw_dmas:1;
213 unsigned int ncq_saw_sdb:1;
216 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
217 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
218 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
219 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
220 static void ahci_irq_clear(struct ata_port *ap);
221 static int ahci_port_start(struct ata_port *ap);
222 static void ahci_port_stop(struct ata_port *ap);
223 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
224 static void ahci_qc_prep(struct ata_queued_cmd *qc);
225 static u8 ahci_check_status(struct ata_port *ap);
226 static void ahci_freeze(struct ata_port *ap);
227 static void ahci_thaw(struct ata_port *ap);
228 static void ahci_error_handler(struct ata_port *ap);
229 static void ahci_vt8251_error_handler(struct ata_port *ap);
230 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
231 static int ahci_port_resume(struct ata_port *ap);
232 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
233 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
236 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
237 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
238 static int ahci_pci_device_resume(struct pci_dev *pdev);
241 static struct scsi_host_template ahci_sht = {
242 .module = THIS_MODULE,
244 .ioctl = ata_scsi_ioctl,
245 .queuecommand = ata_scsi_queuecmd,
246 .change_queue_depth = ata_scsi_change_queue_depth,
247 .can_queue = AHCI_MAX_CMDS - 1,
248 .this_id = ATA_SHT_THIS_ID,
249 .sg_tablesize = AHCI_MAX_SG,
250 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
251 .emulated = ATA_SHT_EMULATED,
252 .use_clustering = AHCI_USE_CLUSTERING,
253 .proc_name = DRV_NAME,
254 .dma_boundary = AHCI_DMA_BOUNDARY,
255 .slave_configure = ata_scsi_slave_config,
256 .slave_destroy = ata_scsi_slave_destroy,
257 .bios_param = ata_std_bios_param,
260 static const struct ata_port_operations ahci_ops = {
261 .port_disable = ata_port_disable,
263 .check_status = ahci_check_status,
264 .check_altstatus = ahci_check_status,
265 .dev_select = ata_noop_dev_select,
267 .tf_read = ahci_tf_read,
269 .qc_prep = ahci_qc_prep,
270 .qc_issue = ahci_qc_issue,
272 .irq_clear = ahci_irq_clear,
273 .irq_on = ata_dummy_irq_on,
274 .irq_ack = ata_dummy_irq_ack,
276 .scr_read = ahci_scr_read,
277 .scr_write = ahci_scr_write,
279 .freeze = ahci_freeze,
282 .error_handler = ahci_error_handler,
283 .post_internal_cmd = ahci_post_internal_cmd,
286 .port_suspend = ahci_port_suspend,
287 .port_resume = ahci_port_resume,
290 .port_start = ahci_port_start,
291 .port_stop = ahci_port_stop,
294 static const struct ata_port_operations ahci_vt8251_ops = {
295 .port_disable = ata_port_disable,
297 .check_status = ahci_check_status,
298 .check_altstatus = ahci_check_status,
299 .dev_select = ata_noop_dev_select,
301 .tf_read = ahci_tf_read,
303 .qc_prep = ahci_qc_prep,
304 .qc_issue = ahci_qc_issue,
306 .irq_clear = ahci_irq_clear,
307 .irq_on = ata_dummy_irq_on,
308 .irq_ack = ata_dummy_irq_ack,
310 .scr_read = ahci_scr_read,
311 .scr_write = ahci_scr_write,
313 .freeze = ahci_freeze,
316 .error_handler = ahci_vt8251_error_handler,
317 .post_internal_cmd = ahci_post_internal_cmd,
320 .port_suspend = ahci_port_suspend,
321 .port_resume = ahci_port_resume,
324 .port_start = ahci_port_start,
325 .port_stop = ahci_port_stop,
328 static const struct ata_port_info ahci_port_info[] = {
331 .flags = AHCI_FLAG_COMMON,
332 .pio_mask = 0x1f, /* pio0-4 */
333 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
334 .port_ops = &ahci_ops,
338 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_HONOR_PI,
339 .pio_mask = 0x1f, /* pio0-4 */
340 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
341 .port_ops = &ahci_ops,
343 /* board_ahci_vt8251 */
345 .flags = AHCI_FLAG_COMMON | ATA_FLAG_HRST_TO_RESUME |
347 .pio_mask = 0x1f, /* pio0-4 */
348 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
349 .port_ops = &ahci_vt8251_ops,
351 /* board_ahci_ign_iferr */
353 .flags = AHCI_FLAG_COMMON | AHCI_FLAG_IGN_IRQ_IF_ERR,
354 .pio_mask = 0x1f, /* pio0-4 */
355 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
356 .port_ops = &ahci_ops,
358 /* board_ahci_sb600 */
360 .flags = AHCI_FLAG_COMMON |
361 AHCI_FLAG_IGN_SERR_INTERNAL |
362 AHCI_FLAG_32BIT_ONLY,
363 .pio_mask = 0x1f, /* pio0-4 */
364 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
365 .port_ops = &ahci_ops,
369 static const struct pci_device_id ahci_pci_tbl[] = {
371 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
372 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
373 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
374 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
375 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
376 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
377 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
378 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
379 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
380 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
381 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
382 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
383 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
384 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
385 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
386 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
387 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
388 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
389 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
390 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
391 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
392 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
393 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
394 { PCI_VDEVICE(INTEL, 0x292c), board_ahci_pi }, /* ICH9M */
395 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
396 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
397 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
399 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
400 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
401 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
404 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
405 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700 */
408 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
409 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
412 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
413 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
414 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
415 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
416 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
417 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
418 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
419 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
420 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
421 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
422 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
423 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
424 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
426 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
433 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
434 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
435 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
436 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
437 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
438 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
439 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
440 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
441 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
442 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
443 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
444 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
445 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
446 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
447 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
448 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
449 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
450 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
451 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
452 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
453 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
454 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
455 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
458 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
459 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
460 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
462 /* Generic, PCI class code for AHCI */
463 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
464 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
466 { } /* terminate list */
470 static struct pci_driver ahci_pci_driver = {
472 .id_table = ahci_pci_tbl,
473 .probe = ahci_init_one,
474 .remove = ata_pci_remove_one,
476 .suspend = ahci_pci_device_suspend,
477 .resume = ahci_pci_device_resume,
482 static inline int ahci_nr_ports(u32 cap)
484 return (cap & 0x1f) + 1;
487 static inline void __iomem *__ahci_port_base(struct ata_host *host,
488 unsigned int port_no)
490 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
492 return mmio + 0x100 + (port_no * 0x80);
495 static inline void __iomem *ahci_port_base(struct ata_port *ap)
497 return __ahci_port_base(ap->host, ap->port_no);
501 * ahci_save_initial_config - Save and fixup initial config values
502 * @pdev: target PCI device
503 * @pi: associated ATA port info
504 * @hpriv: host private area to store config values
506 * Some registers containing configuration info might be setup by
507 * BIOS and might be cleared on reset. This function saves the
508 * initial values of those registers into @hpriv such that they
509 * can be restored after controller reset.
511 * If inconsistent, config values are fixed up by this function.
516 static void ahci_save_initial_config(struct pci_dev *pdev,
517 const struct ata_port_info *pi,
518 struct ahci_host_priv *hpriv)
520 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
524 /* Values prefixed with saved_ are written back to host after
525 * reset. Values without are used for driver operation.
527 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
528 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
530 /* some chips lie about 64bit support */
531 if ((cap & HOST_CAP_64) && (pi->flags & AHCI_FLAG_32BIT_ONLY)) {
532 dev_printk(KERN_INFO, &pdev->dev,
533 "controller can't do 64bit DMA, forcing 32bit\n");
537 /* fixup zero port_map */
539 port_map = (1 << ahci_nr_ports(cap)) - 1;
540 dev_printk(KERN_WARNING, &pdev->dev,
541 "PORTS_IMPL is zero, forcing 0x%x\n", port_map);
543 /* write the fixed up value to the PI register */
544 hpriv->saved_port_map = port_map;
547 /* cross check port_map and cap.n_ports */
548 if (pi->flags & AHCI_FLAG_HONOR_PI) {
549 u32 tmp_port_map = port_map;
550 int n_ports = ahci_nr_ports(cap);
552 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
553 if (tmp_port_map & (1 << i)) {
555 tmp_port_map &= ~(1 << i);
559 /* Whine if inconsistent. No need to update cap.
560 * port_map is used to determine number of ports.
562 if (n_ports || tmp_port_map)
563 dev_printk(KERN_WARNING, &pdev->dev,
564 "nr_ports (%u) and implemented port map "
565 "(0x%x) don't match\n",
566 ahci_nr_ports(cap), port_map);
568 /* fabricate port_map from cap.nr_ports */
569 port_map = (1 << ahci_nr_ports(cap)) - 1;
572 /* record values to use during operation */
574 hpriv->port_map = port_map;
578 * ahci_restore_initial_config - Restore initial config
579 * @host: target ATA host
581 * Restore initial config stored by ahci_save_initial_config().
586 static void ahci_restore_initial_config(struct ata_host *host)
588 struct ahci_host_priv *hpriv = host->private_data;
589 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
591 writel(hpriv->saved_cap, mmio + HOST_CAP);
592 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
593 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
596 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
601 case SCR_STATUS: sc_reg = 0; break;
602 case SCR_CONTROL: sc_reg = 1; break;
603 case SCR_ERROR: sc_reg = 2; break;
604 case SCR_ACTIVE: sc_reg = 3; break;
609 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
613 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
619 case SCR_STATUS: sc_reg = 0; break;
620 case SCR_CONTROL: sc_reg = 1; break;
621 case SCR_ERROR: sc_reg = 2; break;
622 case SCR_ACTIVE: sc_reg = 3; break;
627 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
630 static void ahci_start_engine(struct ata_port *ap)
632 void __iomem *port_mmio = ahci_port_base(ap);
636 tmp = readl(port_mmio + PORT_CMD);
637 tmp |= PORT_CMD_START;
638 writel(tmp, port_mmio + PORT_CMD);
639 readl(port_mmio + PORT_CMD); /* flush */
642 static int ahci_stop_engine(struct ata_port *ap)
644 void __iomem *port_mmio = ahci_port_base(ap);
647 tmp = readl(port_mmio + PORT_CMD);
649 /* check if the HBA is idle */
650 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
653 /* setting HBA to idle */
654 tmp &= ~PORT_CMD_START;
655 writel(tmp, port_mmio + PORT_CMD);
657 /* wait for engine to stop. This could be as long as 500 msec */
658 tmp = ata_wait_register(port_mmio + PORT_CMD,
659 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
660 if (tmp & PORT_CMD_LIST_ON)
666 static void ahci_start_fis_rx(struct ata_port *ap)
668 void __iomem *port_mmio = ahci_port_base(ap);
669 struct ahci_host_priv *hpriv = ap->host->private_data;
670 struct ahci_port_priv *pp = ap->private_data;
673 /* set FIS registers */
674 if (hpriv->cap & HOST_CAP_64)
675 writel((pp->cmd_slot_dma >> 16) >> 16,
676 port_mmio + PORT_LST_ADDR_HI);
677 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
679 if (hpriv->cap & HOST_CAP_64)
680 writel((pp->rx_fis_dma >> 16) >> 16,
681 port_mmio + PORT_FIS_ADDR_HI);
682 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
684 /* enable FIS reception */
685 tmp = readl(port_mmio + PORT_CMD);
686 tmp |= PORT_CMD_FIS_RX;
687 writel(tmp, port_mmio + PORT_CMD);
690 readl(port_mmio + PORT_CMD);
693 static int ahci_stop_fis_rx(struct ata_port *ap)
695 void __iomem *port_mmio = ahci_port_base(ap);
698 /* disable FIS reception */
699 tmp = readl(port_mmio + PORT_CMD);
700 tmp &= ~PORT_CMD_FIS_RX;
701 writel(tmp, port_mmio + PORT_CMD);
703 /* wait for completion, spec says 500ms, give it 1000 */
704 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
705 PORT_CMD_FIS_ON, 10, 1000);
706 if (tmp & PORT_CMD_FIS_ON)
712 static void ahci_power_up(struct ata_port *ap)
714 struct ahci_host_priv *hpriv = ap->host->private_data;
715 void __iomem *port_mmio = ahci_port_base(ap);
718 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
721 if (hpriv->cap & HOST_CAP_SSS) {
722 cmd |= PORT_CMD_SPIN_UP;
723 writel(cmd, port_mmio + PORT_CMD);
727 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
731 static void ahci_power_down(struct ata_port *ap)
733 struct ahci_host_priv *hpriv = ap->host->private_data;
734 void __iomem *port_mmio = ahci_port_base(ap);
737 if (!(hpriv->cap & HOST_CAP_SSS))
740 /* put device into listen mode, first set PxSCTL.DET to 0 */
741 scontrol = readl(port_mmio + PORT_SCR_CTL);
743 writel(scontrol, port_mmio + PORT_SCR_CTL);
745 /* then set PxCMD.SUD to 0 */
746 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
747 cmd &= ~PORT_CMD_SPIN_UP;
748 writel(cmd, port_mmio + PORT_CMD);
752 static void ahci_start_port(struct ata_port *ap)
754 /* enable FIS reception */
755 ahci_start_fis_rx(ap);
758 ahci_start_engine(ap);
761 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
766 rc = ahci_stop_engine(ap);
768 *emsg = "failed to stop engine";
772 /* disable FIS reception */
773 rc = ahci_stop_fis_rx(ap);
775 *emsg = "failed stop FIS RX";
782 static int ahci_reset_controller(struct ata_host *host)
784 struct pci_dev *pdev = to_pci_dev(host->dev);
785 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
788 /* global controller reset */
789 tmp = readl(mmio + HOST_CTL);
790 if ((tmp & HOST_RESET) == 0) {
791 writel(tmp | HOST_RESET, mmio + HOST_CTL);
792 readl(mmio + HOST_CTL); /* flush */
795 /* reset must complete within 1 second, or
796 * the hardware should be considered fried.
800 tmp = readl(mmio + HOST_CTL);
801 if (tmp & HOST_RESET) {
802 dev_printk(KERN_ERR, host->dev,
803 "controller reset failed (0x%x)\n", tmp);
807 /* turn on AHCI mode */
808 writel(HOST_AHCI_EN, mmio + HOST_CTL);
809 (void) readl(mmio + HOST_CTL); /* flush */
811 /* some registers might be cleared on reset. restore initial values */
812 ahci_restore_initial_config(host);
814 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
818 pci_read_config_word(pdev, 0x92, &tmp16);
820 pci_write_config_word(pdev, 0x92, tmp16);
826 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
827 int port_no, void __iomem *mmio,
828 void __iomem *port_mmio)
830 const char *emsg = NULL;
834 /* make sure port is not active */
835 rc = ahci_deinit_port(ap, &emsg);
837 dev_printk(KERN_WARNING, &pdev->dev,
838 "%s (%d)\n", emsg, rc);
841 tmp = readl(port_mmio + PORT_SCR_ERR);
842 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
843 writel(tmp, port_mmio + PORT_SCR_ERR);
846 tmp = readl(port_mmio + PORT_IRQ_STAT);
847 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
849 writel(tmp, port_mmio + PORT_IRQ_STAT);
851 writel(1 << port_no, mmio + HOST_IRQ_STAT);
854 static void ahci_init_controller(struct ata_host *host)
856 struct pci_dev *pdev = to_pci_dev(host->dev);
857 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
861 for (i = 0; i < host->n_ports; i++) {
862 struct ata_port *ap = host->ports[i];
863 void __iomem *port_mmio = ahci_port_base(ap);
865 if (ata_port_is_dummy(ap))
868 ahci_port_init(pdev, ap, i, mmio, port_mmio);
871 tmp = readl(mmio + HOST_CTL);
872 VPRINTK("HOST_CTL 0x%x\n", tmp);
873 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
874 tmp = readl(mmio + HOST_CTL);
875 VPRINTK("HOST_CTL 0x%x\n", tmp);
878 static unsigned int ahci_dev_classify(struct ata_port *ap)
880 void __iomem *port_mmio = ahci_port_base(ap);
881 struct ata_taskfile tf;
884 tmp = readl(port_mmio + PORT_SIG);
885 tf.lbah = (tmp >> 24) & 0xff;
886 tf.lbam = (tmp >> 16) & 0xff;
887 tf.lbal = (tmp >> 8) & 0xff;
888 tf.nsect = (tmp) & 0xff;
890 return ata_dev_classify(&tf);
893 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
896 dma_addr_t cmd_tbl_dma;
898 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
900 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
901 pp->cmd_slot[tag].status = 0;
902 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
903 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
906 static int ahci_clo(struct ata_port *ap)
908 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
909 struct ahci_host_priv *hpriv = ap->host->private_data;
912 if (!(hpriv->cap & HOST_CAP_CLO))
915 tmp = readl(port_mmio + PORT_CMD);
917 writel(tmp, port_mmio + PORT_CMD);
919 tmp = ata_wait_register(port_mmio + PORT_CMD,
920 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
921 if (tmp & PORT_CMD_CLO)
927 static int ahci_softreset(struct ata_port *ap, unsigned int *class,
928 unsigned long deadline)
930 struct ahci_port_priv *pp = ap->private_data;
931 void __iomem *port_mmio = ahci_port_base(ap);
932 const u32 cmd_fis_len = 5; /* five dwords */
933 const char *reason = NULL;
934 struct ata_taskfile tf;
941 if (ata_port_offline(ap)) {
942 DPRINTK("PHY reports no device\n");
943 *class = ATA_DEV_NONE;
947 /* prepare for SRST (AHCI-1.1 10.4.1) */
948 rc = ahci_stop_engine(ap);
950 reason = "failed to stop engine";
954 /* check BUSY/DRQ, perform Command List Override if necessary */
955 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
958 if (rc == -EOPNOTSUPP) {
959 reason = "port busy but CLO unavailable";
962 reason = "port busy but CLO failed";
968 ahci_start_engine(ap);
970 ata_tf_init(ap->device, &tf);
973 /* issue the first D2H Register FIS */
974 ahci_fill_cmd_slot(pp, 0,
975 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
978 ata_tf_to_fis(&tf, fis, 0);
979 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
981 writel(1, port_mmio + PORT_CMD_ISSUE);
983 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
986 reason = "1st FIS failed";
990 /* spec says at least 5us, but be generous and sleep for 1ms */
993 /* issue the second D2H Register FIS */
994 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
997 ata_tf_to_fis(&tf, fis, 0);
998 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
1000 writel(1, port_mmio + PORT_CMD_ISSUE);
1001 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1003 /* spec mandates ">= 2ms" before checking status.
1004 * We wait 150ms, because that was the magic delay used for
1005 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1006 * between when the ATA command register is written, and then
1007 * status is checked. Because waiting for "a while" before
1008 * checking status is fine, post SRST, we perform this magic
1009 * delay here as well.
1013 rc = ata_wait_ready(ap, deadline);
1014 /* link occupied, -ENODEV too is an error */
1016 reason = "device not ready";
1019 *class = ahci_dev_classify(ap);
1021 DPRINTK("EXIT, class=%u\n", *class);
1025 ahci_start_engine(ap);
1027 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
1031 static int ahci_hardreset(struct ata_port *ap, unsigned int *class,
1032 unsigned long deadline)
1034 struct ahci_port_priv *pp = ap->private_data;
1035 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1036 struct ata_taskfile tf;
1041 ahci_stop_engine(ap);
1043 /* clear D2H reception area to properly wait for D2H FIS */
1044 ata_tf_init(ap->device, &tf);
1046 ata_tf_to_fis(&tf, d2h_fis, 0);
1048 rc = sata_std_hardreset(ap, class, deadline);
1050 ahci_start_engine(ap);
1052 if (rc == 0 && ata_port_online(ap))
1053 *class = ahci_dev_classify(ap);
1054 if (*class == ATA_DEV_UNKNOWN)
1055 *class = ATA_DEV_NONE;
1057 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1061 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class,
1062 unsigned long deadline)
1068 ahci_stop_engine(ap);
1070 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context),
1073 /* vt8251 needs SError cleared for the port to operate */
1074 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
1076 ahci_start_engine(ap);
1078 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1080 /* vt8251 doesn't clear BSY on signature FIS reception,
1081 * request follow-up softreset.
1083 return rc ?: -EAGAIN;
1086 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
1088 void __iomem *port_mmio = ahci_port_base(ap);
1091 ata_std_postreset(ap, class);
1093 /* Make sure port's ATAPI bit is set appropriately */
1094 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1095 if (*class == ATA_DEV_ATAPI)
1096 new_tmp |= PORT_CMD_ATAPI;
1098 new_tmp &= ~PORT_CMD_ATAPI;
1099 if (new_tmp != tmp) {
1100 writel(new_tmp, port_mmio + PORT_CMD);
1101 readl(port_mmio + PORT_CMD); /* flush */
1105 static u8 ahci_check_status(struct ata_port *ap)
1107 void __iomem *mmio = ap->ioaddr.cmd_addr;
1109 return readl(mmio + PORT_TFDATA) & 0xFF;
1112 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1114 struct ahci_port_priv *pp = ap->private_data;
1115 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1117 ata_tf_from_fis(d2h_fis, tf);
1120 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1122 struct scatterlist *sg;
1123 struct ahci_sg *ahci_sg;
1124 unsigned int n_sg = 0;
1129 * Next, the S/G list.
1131 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1132 ata_for_each_sg(sg, qc) {
1133 dma_addr_t addr = sg_dma_address(sg);
1134 u32 sg_len = sg_dma_len(sg);
1136 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1137 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1138 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1147 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1149 struct ata_port *ap = qc->ap;
1150 struct ahci_port_priv *pp = ap->private_data;
1151 int is_atapi = is_atapi_taskfile(&qc->tf);
1154 const u32 cmd_fis_len = 5; /* five dwords */
1155 unsigned int n_elem;
1158 * Fill in command table information. First, the header,
1159 * a SATA Register - Host to Device command FIS.
1161 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1163 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
1165 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1166 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1170 if (qc->flags & ATA_QCFLAG_DMAMAP)
1171 n_elem = ahci_fill_sg(qc, cmd_tbl);
1174 * Fill in command slot information.
1176 opts = cmd_fis_len | n_elem << 16;
1177 if (qc->tf.flags & ATA_TFLAG_WRITE)
1178 opts |= AHCI_CMD_WRITE;
1180 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1182 ahci_fill_cmd_slot(pp, qc->tag, opts);
1185 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1187 struct ahci_port_priv *pp = ap->private_data;
1188 struct ata_eh_info *ehi = &ap->eh_info;
1189 unsigned int err_mask = 0, action = 0;
1190 struct ata_queued_cmd *qc;
1193 ata_ehi_clear_desc(ehi);
1195 /* AHCI needs SError cleared; otherwise, it might lock up */
1196 serror = ahci_scr_read(ap, SCR_ERROR);
1197 ahci_scr_write(ap, SCR_ERROR, serror);
1199 /* analyze @irq_stat */
1200 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1202 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1203 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1204 irq_stat &= ~PORT_IRQ_IF_ERR;
1206 if (irq_stat & PORT_IRQ_TF_ERR) {
1207 err_mask |= AC_ERR_DEV;
1208 if (ap->flags & AHCI_FLAG_IGN_SERR_INTERNAL)
1209 serror &= ~SERR_INTERNAL;
1212 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1213 err_mask |= AC_ERR_HOST_BUS;
1214 action |= ATA_EH_SOFTRESET;
1217 if (irq_stat & PORT_IRQ_IF_ERR) {
1218 err_mask |= AC_ERR_ATA_BUS;
1219 action |= ATA_EH_SOFTRESET;
1220 ata_ehi_push_desc(ehi, ", interface fatal error");
1223 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1224 ata_ehi_hotplugged(ehi);
1225 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1226 "connection status changed" : "PHY RDY changed");
1229 if (irq_stat & PORT_IRQ_UNK_FIS) {
1230 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1232 err_mask |= AC_ERR_HSM;
1233 action |= ATA_EH_SOFTRESET;
1234 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1235 unk[0], unk[1], unk[2], unk[3]);
1238 /* okay, let's hand over to EH */
1239 ehi->serror |= serror;
1240 ehi->action |= action;
1242 qc = ata_qc_from_tag(ap, ap->active_tag);
1244 qc->err_mask |= err_mask;
1246 ehi->err_mask |= err_mask;
1248 if (irq_stat & PORT_IRQ_FREEZE)
1249 ata_port_freeze(ap);
1254 static void ahci_port_intr(struct ata_port *ap)
1256 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1257 struct ata_eh_info *ehi = &ap->eh_info;
1258 struct ahci_port_priv *pp = ap->private_data;
1259 u32 status, qc_active;
1260 int rc, known_irq = 0;
1262 status = readl(port_mmio + PORT_IRQ_STAT);
1263 writel(status, port_mmio + PORT_IRQ_STAT);
1265 if (unlikely(status & PORT_IRQ_ERROR)) {
1266 ahci_error_intr(ap, status);
1271 qc_active = readl(port_mmio + PORT_SCR_ACT);
1273 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1275 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1279 ehi->err_mask |= AC_ERR_HSM;
1280 ehi->action |= ATA_EH_SOFTRESET;
1281 ata_port_freeze(ap);
1285 /* hmmm... a spurious interupt */
1287 /* if !NCQ, ignore. No modern ATA device has broken HSM
1288 * implementation for non-NCQ commands.
1293 if (status & PORT_IRQ_D2H_REG_FIS) {
1294 if (!pp->ncq_saw_d2h)
1295 ata_port_printk(ap, KERN_INFO,
1296 "D2H reg with I during NCQ, "
1297 "this message won't be printed again\n");
1298 pp->ncq_saw_d2h = 1;
1302 if (status & PORT_IRQ_DMAS_FIS) {
1303 if (!pp->ncq_saw_dmas)
1304 ata_port_printk(ap, KERN_INFO,
1305 "DMAS FIS during NCQ, "
1306 "this message won't be printed again\n");
1307 pp->ncq_saw_dmas = 1;
1311 if (status & PORT_IRQ_SDB_FIS) {
1312 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1314 if (le32_to_cpu(f[1])) {
1315 /* SDB FIS containing spurious completions
1316 * might be dangerous, whine and fail commands
1317 * with HSM violation. EH will turn off NCQ
1318 * after several such failures.
1320 ata_ehi_push_desc(ehi,
1321 "spurious completions during NCQ "
1322 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1323 readl(port_mmio + PORT_CMD_ISSUE),
1324 readl(port_mmio + PORT_SCR_ACT),
1325 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1326 ehi->err_mask |= AC_ERR_HSM;
1327 ehi->action |= ATA_EH_SOFTRESET;
1328 ata_port_freeze(ap);
1330 if (!pp->ncq_saw_sdb)
1331 ata_port_printk(ap, KERN_INFO,
1332 "spurious SDB FIS %08x:%08x during NCQ, "
1333 "this message won't be printed again\n",
1334 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1335 pp->ncq_saw_sdb = 1;
1341 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1342 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1343 status, ap->active_tag, ap->sactive);
1346 static void ahci_irq_clear(struct ata_port *ap)
1351 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1353 struct ata_host *host = dev_instance;
1354 struct ahci_host_priv *hpriv;
1355 unsigned int i, handled = 0;
1357 u32 irq_stat, irq_ack = 0;
1361 hpriv = host->private_data;
1362 mmio = host->iomap[AHCI_PCI_BAR];
1364 /* sigh. 0xffffffff is a valid return from h/w */
1365 irq_stat = readl(mmio + HOST_IRQ_STAT);
1366 irq_stat &= hpriv->port_map;
1370 spin_lock(&host->lock);
1372 for (i = 0; i < host->n_ports; i++) {
1373 struct ata_port *ap;
1375 if (!(irq_stat & (1 << i)))
1378 ap = host->ports[i];
1381 VPRINTK("port %u\n", i);
1383 VPRINTK("port %u (no irq)\n", i);
1384 if (ata_ratelimit())
1385 dev_printk(KERN_WARNING, host->dev,
1386 "interrupt on disabled port %u\n", i);
1389 irq_ack |= (1 << i);
1393 writel(irq_ack, mmio + HOST_IRQ_STAT);
1397 spin_unlock(&host->lock);
1401 return IRQ_RETVAL(handled);
1404 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1406 struct ata_port *ap = qc->ap;
1407 void __iomem *port_mmio = ahci_port_base(ap);
1409 if (qc->tf.protocol == ATA_PROT_NCQ)
1410 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1411 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1412 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1417 static void ahci_freeze(struct ata_port *ap)
1419 void __iomem *port_mmio = ahci_port_base(ap);
1422 writel(0, port_mmio + PORT_IRQ_MASK);
1425 static void ahci_thaw(struct ata_port *ap)
1427 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1428 void __iomem *port_mmio = ahci_port_base(ap);
1432 tmp = readl(port_mmio + PORT_IRQ_STAT);
1433 writel(tmp, port_mmio + PORT_IRQ_STAT);
1434 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1436 /* turn IRQ back on */
1437 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1440 static void ahci_error_handler(struct ata_port *ap)
1442 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1443 /* restart engine */
1444 ahci_stop_engine(ap);
1445 ahci_start_engine(ap);
1448 /* perform recovery */
1449 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1453 static void ahci_vt8251_error_handler(struct ata_port *ap)
1455 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1456 /* restart engine */
1457 ahci_stop_engine(ap);
1458 ahci_start_engine(ap);
1461 /* perform recovery */
1462 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1466 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1468 struct ata_port *ap = qc->ap;
1470 if (qc->flags & ATA_QCFLAG_FAILED) {
1471 /* make DMA engine forget about the failed command */
1472 ahci_stop_engine(ap);
1473 ahci_start_engine(ap);
1478 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1480 const char *emsg = NULL;
1483 rc = ahci_deinit_port(ap, &emsg);
1485 ahci_power_down(ap);
1487 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1488 ahci_start_port(ap);
1494 static int ahci_port_resume(struct ata_port *ap)
1497 ahci_start_port(ap);
1502 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1504 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1505 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1508 if (mesg.event == PM_EVENT_SUSPEND) {
1509 /* AHCI spec rev1.1 section 8.3.3:
1510 * Software must disable interrupts prior to requesting a
1511 * transition of the HBA to D3 state.
1513 ctl = readl(mmio + HOST_CTL);
1514 ctl &= ~HOST_IRQ_EN;
1515 writel(ctl, mmio + HOST_CTL);
1516 readl(mmio + HOST_CTL); /* flush */
1519 return ata_pci_device_suspend(pdev, mesg);
1522 static int ahci_pci_device_resume(struct pci_dev *pdev)
1524 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1527 rc = ata_pci_device_do_resume(pdev);
1531 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1532 rc = ahci_reset_controller(host);
1536 ahci_init_controller(host);
1539 ata_host_resume(host);
1545 static int ahci_port_start(struct ata_port *ap)
1547 struct device *dev = ap->host->dev;
1548 struct ahci_port_priv *pp;
1553 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1557 rc = ata_pad_alloc(ap, dev);
1561 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1565 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1568 * First item in chunk of DMA memory: 32-slot command table,
1569 * 32 bytes each in size
1572 pp->cmd_slot_dma = mem_dma;
1574 mem += AHCI_CMD_SLOT_SZ;
1575 mem_dma += AHCI_CMD_SLOT_SZ;
1578 * Second item: Received-FIS area
1581 pp->rx_fis_dma = mem_dma;
1583 mem += AHCI_RX_FIS_SZ;
1584 mem_dma += AHCI_RX_FIS_SZ;
1587 * Third item: data area for storing a single command
1588 * and its scatter-gather table
1591 pp->cmd_tbl_dma = mem_dma;
1593 ap->private_data = pp;
1595 /* engage engines, captain */
1596 return ahci_port_resume(ap);
1599 static void ahci_port_stop(struct ata_port *ap)
1601 const char *emsg = NULL;
1604 /* de-initialize port */
1605 rc = ahci_deinit_port(ap, &emsg);
1607 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1610 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
1615 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1616 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1618 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1620 dev_printk(KERN_ERR, &pdev->dev,
1621 "64-bit DMA enable failed\n");
1626 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1628 dev_printk(KERN_ERR, &pdev->dev,
1629 "32-bit DMA enable failed\n");
1632 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1634 dev_printk(KERN_ERR, &pdev->dev,
1635 "32-bit consistent DMA enable failed\n");
1642 static void ahci_print_info(struct ata_host *host)
1644 struct ahci_host_priv *hpriv = host->private_data;
1645 struct pci_dev *pdev = to_pci_dev(host->dev);
1646 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1647 u32 vers, cap, impl, speed;
1648 const char *speed_s;
1652 vers = readl(mmio + HOST_VERSION);
1654 impl = hpriv->port_map;
1656 speed = (cap >> 20) & 0xf;
1659 else if (speed == 2)
1664 pci_read_config_word(pdev, 0x0a, &cc);
1665 if (cc == PCI_CLASS_STORAGE_IDE)
1667 else if (cc == PCI_CLASS_STORAGE_SATA)
1669 else if (cc == PCI_CLASS_STORAGE_RAID)
1674 dev_printk(KERN_INFO, &pdev->dev,
1675 "AHCI %02x%02x.%02x%02x "
1676 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1679 (vers >> 24) & 0xff,
1680 (vers >> 16) & 0xff,
1684 ((cap >> 8) & 0x1f) + 1,
1690 dev_printk(KERN_INFO, &pdev->dev,
1696 cap & (1 << 31) ? "64bit " : "",
1697 cap & (1 << 30) ? "ncq " : "",
1698 cap & (1 << 28) ? "ilck " : "",
1699 cap & (1 << 27) ? "stag " : "",
1700 cap & (1 << 26) ? "pm " : "",
1701 cap & (1 << 25) ? "led " : "",
1703 cap & (1 << 24) ? "clo " : "",
1704 cap & (1 << 19) ? "nz " : "",
1705 cap & (1 << 18) ? "only " : "",
1706 cap & (1 << 17) ? "pmp " : "",
1707 cap & (1 << 15) ? "pio " : "",
1708 cap & (1 << 14) ? "slum " : "",
1709 cap & (1 << 13) ? "part " : ""
1713 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1715 static int printed_version;
1716 struct ata_port_info pi = ahci_port_info[ent->driver_data];
1717 const struct ata_port_info *ppi[] = { &pi, NULL };
1718 struct device *dev = &pdev->dev;
1719 struct ahci_host_priv *hpriv;
1720 struct ata_host *host;
1725 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1727 if (!printed_version++)
1728 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1730 /* acquire resources */
1731 rc = pcim_enable_device(pdev);
1735 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1737 pcim_pin_device(pdev);
1741 if (pci_enable_msi(pdev))
1744 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1748 /* save initial config */
1749 ahci_save_initial_config(pdev, &pi, hpriv);
1752 if (!(pi.flags & AHCI_FLAG_NO_NCQ) && (hpriv->cap & HOST_CAP_NCQ))
1753 pi.flags |= ATA_FLAG_NCQ;
1755 host = ata_host_alloc_pinfo(&pdev->dev, ppi, fls(hpriv->port_map));
1758 host->iomap = pcim_iomap_table(pdev);
1759 host->private_data = hpriv;
1761 for (i = 0; i < host->n_ports; i++) {
1762 struct ata_port *ap = host->ports[i];
1763 void __iomem *port_mmio = ahci_port_base(ap);
1765 /* standard SATA port setup */
1766 if (hpriv->port_map & (1 << i)) {
1767 ap->ioaddr.cmd_addr = port_mmio;
1768 ap->ioaddr.scr_addr = port_mmio + PORT_SCR;
1771 /* disabled/not-implemented port */
1773 ap->ops = &ata_dummy_port_ops;
1776 /* initialize adapter */
1777 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1781 rc = ahci_reset_controller(host);
1785 ahci_init_controller(host);
1786 ahci_print_info(host);
1788 pci_set_master(pdev);
1789 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1793 static int __init ahci_init(void)
1795 return pci_register_driver(&ahci_pci_driver);
1798 static void __exit ahci_exit(void)
1800 pci_unregister_driver(&ahci_pci_driver);
1804 MODULE_AUTHOR("Jeff Garzik");
1805 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1806 MODULE_LICENSE("GPL");
1807 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1808 MODULE_VERSION(DRV_VERSION);
1810 module_init(ahci_init);
1811 module_exit(ahci_exit);