2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "2.00ac6"
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
109 /* combined mode. if set, PATA is channel 0.
110 * if clear, PATA is channel 1.
112 PIIX_PORT_ENABLED = (1 << 0),
113 PIIX_PORT_PRESENT = (1 << 4),
115 PIIX_80C_PRI = (1 << 5) | (1 << 4),
116 PIIX_80C_SEC = (1 << 7) | (1 << 6),
119 piix_pata_33 = 0, /* PIIX3 or 4 at 33Mhz */
120 ich_pata_33 = 1, /* ICH up to UDMA 33 only */
121 ich_pata_66 = 2, /* ICH up to 66 Mhz */
122 ich_pata_100 = 3, /* ICH up to UDMA 100 */
123 ich_pata_133 = 4, /* ICH up to UDMA 133 */
129 ich7m_sata_ahci = 10,
132 /* constants for mapping table */
138 NA = -2, /* not avaliable */
139 RV = -3, /* reserved */
141 PIIX_AHCI_DEVICE = 6,
146 const u16 port_enable;
147 const int present_shift;
151 struct piix_host_priv {
153 const struct piix_map_db *map_db;
156 static int piix_init_one (struct pci_dev *pdev,
157 const struct pci_device_id *ent);
158 static void piix_host_stop(struct ata_host *host);
159 static void piix_pata_error_handler(struct ata_port *ap);
160 static void ich_pata_error_handler(struct ata_port *ap);
161 static void piix_sata_error_handler(struct ata_port *ap);
162 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
163 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
164 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev);
166 static unsigned int in_module_init = 1;
168 static const struct pci_device_id piix_pci_tbl[] = {
169 #ifdef ATA_ENABLE_PATA
170 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
171 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
172 { 0x8086, 0x7110, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
173 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
174 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
175 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
177 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
179 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
181 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
182 /* Intel ICH (i810, i815, i840) UDMA 66*/
183 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
184 /* Intel ICH0 : UDMA 33*/
185 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
187 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
188 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
189 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
192 /* Intel ICH3 (E7500/1) UDMA 100 */
193 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
194 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
195 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
196 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
198 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
200 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
201 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
202 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
203 /* ICH6 (and 6) (i915) UDMA 100 */
204 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
205 /* ICH7/7-R (i945, i975) UDMA 100*/
206 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_133 },
207 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* NOTE: The following PCI ids must be kept in sync with the
211 * list in drivers/pci/quirks.c.
215 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
217 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
218 /* 6300ESB (ICH5 variant with broken PCS present bits) */
219 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
220 /* 6300ESB pretending RAID */
221 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
222 /* 82801FB/FW (ICH6/ICH6W) */
223 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
224 /* 82801FR/FRW (ICH6R/ICH6RW) */
225 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
226 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
227 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
228 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
229 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
230 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
231 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7m_sata_ahci },
232 /* Enterprise Southbridge 2 (where's the datasheet?) */
233 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
234 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
235 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
236 /* SATA Controller 2 IDE (ICH8, ditto) */
237 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
238 /* Mobile SATA Controller IDE (ICH8M, ditto) */
239 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
241 { } /* terminate list */
244 static struct pci_driver piix_pci_driver = {
246 .id_table = piix_pci_tbl,
247 .probe = piix_init_one,
248 .remove = ata_pci_remove_one,
249 .suspend = ata_pci_device_suspend,
250 .resume = ata_pci_device_resume,
253 static struct scsi_host_template piix_sht = {
254 .module = THIS_MODULE,
256 .ioctl = ata_scsi_ioctl,
257 .queuecommand = ata_scsi_queuecmd,
258 .can_queue = ATA_DEF_QUEUE,
259 .this_id = ATA_SHT_THIS_ID,
260 .sg_tablesize = LIBATA_MAX_PRD,
261 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
262 .emulated = ATA_SHT_EMULATED,
263 .use_clustering = ATA_SHT_USE_CLUSTERING,
264 .proc_name = DRV_NAME,
265 .dma_boundary = ATA_DMA_BOUNDARY,
266 .slave_configure = ata_scsi_slave_config,
267 .slave_destroy = ata_scsi_slave_destroy,
268 .bios_param = ata_std_bios_param,
269 .resume = ata_scsi_device_resume,
270 .suspend = ata_scsi_device_suspend,
273 static const struct ata_port_operations piix_pata_ops = {
274 .port_disable = ata_port_disable,
275 .set_piomode = piix_set_piomode,
276 .set_dmamode = piix_set_dmamode,
277 .mode_filter = ata_pci_default_filter,
279 .tf_load = ata_tf_load,
280 .tf_read = ata_tf_read,
281 .check_status = ata_check_status,
282 .exec_command = ata_exec_command,
283 .dev_select = ata_std_dev_select,
285 .bmdma_setup = ata_bmdma_setup,
286 .bmdma_start = ata_bmdma_start,
287 .bmdma_stop = ata_bmdma_stop,
288 .bmdma_status = ata_bmdma_status,
289 .qc_prep = ata_qc_prep,
290 .qc_issue = ata_qc_issue_prot,
291 .data_xfer = ata_pio_data_xfer,
293 .freeze = ata_bmdma_freeze,
294 .thaw = ata_bmdma_thaw,
295 .error_handler = piix_pata_error_handler,
296 .post_internal_cmd = ata_bmdma_post_internal_cmd,
298 .irq_handler = ata_interrupt,
299 .irq_clear = ata_bmdma_irq_clear,
301 .port_start = ata_port_start,
302 .port_stop = ata_port_stop,
303 .host_stop = piix_host_stop,
306 static const struct ata_port_operations ich_pata_ops = {
307 .port_disable = ata_port_disable,
308 .set_piomode = piix_set_piomode,
309 .set_dmamode = ich_set_dmamode,
310 .mode_filter = ata_pci_default_filter,
312 .tf_load = ata_tf_load,
313 .tf_read = ata_tf_read,
314 .check_status = ata_check_status,
315 .exec_command = ata_exec_command,
316 .dev_select = ata_std_dev_select,
318 .bmdma_setup = ata_bmdma_setup,
319 .bmdma_start = ata_bmdma_start,
320 .bmdma_stop = ata_bmdma_stop,
321 .bmdma_status = ata_bmdma_status,
322 .qc_prep = ata_qc_prep,
323 .qc_issue = ata_qc_issue_prot,
324 .data_xfer = ata_pio_data_xfer,
326 .freeze = ata_bmdma_freeze,
327 .thaw = ata_bmdma_thaw,
328 .error_handler = ich_pata_error_handler,
329 .post_internal_cmd = ata_bmdma_post_internal_cmd,
331 .irq_handler = ata_interrupt,
332 .irq_clear = ata_bmdma_irq_clear,
334 .port_start = ata_port_start,
335 .port_stop = ata_port_stop,
336 .host_stop = ata_host_stop,
339 static const struct ata_port_operations piix_sata_ops = {
340 .port_disable = ata_port_disable,
342 .tf_load = ata_tf_load,
343 .tf_read = ata_tf_read,
344 .check_status = ata_check_status,
345 .exec_command = ata_exec_command,
346 .dev_select = ata_std_dev_select,
348 .bmdma_setup = ata_bmdma_setup,
349 .bmdma_start = ata_bmdma_start,
350 .bmdma_stop = ata_bmdma_stop,
351 .bmdma_status = ata_bmdma_status,
352 .qc_prep = ata_qc_prep,
353 .qc_issue = ata_qc_issue_prot,
354 .data_xfer = ata_pio_data_xfer,
356 .freeze = ata_bmdma_freeze,
357 .thaw = ata_bmdma_thaw,
358 .error_handler = piix_sata_error_handler,
359 .post_internal_cmd = ata_bmdma_post_internal_cmd,
361 .irq_handler = ata_interrupt,
362 .irq_clear = ata_bmdma_irq_clear,
364 .port_start = ata_port_start,
365 .port_stop = ata_port_stop,
366 .host_stop = piix_host_stop,
369 static const struct piix_map_db ich5_map_db = {
374 /* PM PS SM SS MAP */
375 { P0, NA, P1, NA }, /* 000b */
376 { P1, NA, P0, NA }, /* 001b */
379 { P0, P1, IDE, IDE }, /* 100b */
380 { P1, P0, IDE, IDE }, /* 101b */
381 { IDE, IDE, P0, P1 }, /* 110b */
382 { IDE, IDE, P1, P0 }, /* 111b */
386 static const struct piix_map_db ich6_map_db = {
391 /* PM PS SM SS MAP */
392 { P0, P2, P1, P3 }, /* 00b */
393 { IDE, IDE, P1, P3 }, /* 01b */
394 { P0, P2, IDE, IDE }, /* 10b */
399 static const struct piix_map_db ich6m_map_db = {
404 /* PM PS SM SS MAP */
405 { P0, P2, RV, RV }, /* 00b */
407 { P0, P2, IDE, IDE }, /* 10b */
412 static const struct piix_map_db ich7m_map_db = {
417 /* Map 01b isn't specified in the doc but some notebooks use
418 * it anyway. ATM, the only case spotted carries subsystem ID
419 * 1025:0107. This is the only difference from ich6m.
422 /* PM PS SM SS MAP */
423 { P0, P2, RV, RV }, /* 00b */
424 { IDE, IDE, P1, P3 }, /* 01b */
425 { P0, P2, IDE, IDE }, /* 10b */
430 static const struct piix_map_db ich8_map_db = {
435 /* PM PS SM SS MAP */
436 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
438 { IDE, IDE, NA, NA }, /* 10b (IDE mode) */
443 static const struct piix_map_db *piix_map_db_table[] = {
444 [ich5_sata] = &ich5_map_db,
445 [esb_sata] = &ich5_map_db,
446 [ich6_sata] = &ich6_map_db,
447 [ich6_sata_ahci] = &ich6_map_db,
448 [ich6m_sata_ahci] = &ich6m_map_db,
449 [ich7m_sata_ahci] = &ich7m_map_db,
450 [ich8_sata_ahci] = &ich8_map_db,
453 static struct ata_port_info piix_port_info[] = {
454 /* piix_pata_33: 0: PIIX3 or 4 at 33MHz */
457 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
458 .pio_mask = 0x1f, /* pio0-4 */
459 .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
460 .udma_mask = ATA_UDMA_MASK_40C,
461 .port_ops = &piix_pata_ops,
464 /* ich_pata_33: 1 ICH0 - ICH at 33Mhz*/
467 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
468 .pio_mask = 0x1f, /* pio 0-4 */
469 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
470 .udma_mask = ATA_UDMA2, /* UDMA33 */
471 .port_ops = &ich_pata_ops,
473 /* ich_pata_66: 2 ICH controllers up to 66MHz */
476 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
477 .pio_mask = 0x1f, /* pio 0-4 */
478 .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */
479 .udma_mask = ATA_UDMA4,
480 .port_ops = &ich_pata_ops,
483 /* ich_pata_100: 3 */
486 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
487 .pio_mask = 0x1f, /* pio0-4 */
488 .mwdma_mask = 0x06, /* mwdma1-2 */
489 .udma_mask = ATA_UDMA5, /* udma0-5 */
490 .port_ops = &ich_pata_ops,
493 /* ich_pata_133: 4 ICH with full UDMA6 */
496 .flags = ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
497 .pio_mask = 0x1f, /* pio 0-4 */
498 .mwdma_mask = 0x06, /* Check: maybe 0x07 */
499 .udma_mask = ATA_UDMA6, /* UDMA133 */
500 .port_ops = &ich_pata_ops,
506 .flags = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR |
507 PIIX_FLAG_IGNORE_PCS,
508 .pio_mask = 0x1f, /* pio0-4 */
509 .mwdma_mask = 0x07, /* mwdma0-2 */
510 .udma_mask = 0x7f, /* udma0-6 */
511 .port_ops = &piix_sata_ops,
514 /* i6300esb_sata: 6 */
517 .flags = ATA_FLAG_SATA |
518 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
519 .pio_mask = 0x1f, /* pio0-4 */
520 .mwdma_mask = 0x07, /* mwdma0-2 */
521 .udma_mask = 0x7f, /* udma0-6 */
522 .port_ops = &piix_sata_ops,
528 .flags = ATA_FLAG_SATA |
529 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
530 .pio_mask = 0x1f, /* pio0-4 */
531 .mwdma_mask = 0x07, /* mwdma0-2 */
532 .udma_mask = 0x7f, /* udma0-6 */
533 .port_ops = &piix_sata_ops,
536 /* ich6_sata_ahci: 8 */
539 .flags = ATA_FLAG_SATA |
540 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
542 .pio_mask = 0x1f, /* pio0-4 */
543 .mwdma_mask = 0x07, /* mwdma0-2 */
544 .udma_mask = 0x7f, /* udma0-6 */
545 .port_ops = &piix_sata_ops,
548 /* ich6m_sata_ahci: 9 */
551 .flags = ATA_FLAG_SATA |
552 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
554 .pio_mask = 0x1f, /* pio0-4 */
555 .mwdma_mask = 0x07, /* mwdma0-2 */
556 .udma_mask = 0x7f, /* udma0-6 */
557 .port_ops = &piix_sata_ops,
560 /* ich7m_sata_ahci: 10 */
563 .flags = ATA_FLAG_SATA |
564 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
566 .pio_mask = 0x1f, /* pio0-4 */
567 .mwdma_mask = 0x07, /* mwdma0-2 */
568 .udma_mask = 0x7f, /* udma0-6 */
569 .port_ops = &piix_sata_ops,
572 /* ich8_sata_ahci: 11 */
575 .flags = ATA_FLAG_SATA |
576 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
578 .pio_mask = 0x1f, /* pio0-4 */
579 .mwdma_mask = 0x07, /* mwdma0-2 */
580 .udma_mask = 0x7f, /* udma0-6 */
581 .port_ops = &piix_sata_ops,
586 static struct pci_bits piix_enable_bits[] = {
587 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
588 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
591 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
592 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
593 MODULE_LICENSE("GPL");
594 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
595 MODULE_VERSION(DRV_VERSION);
597 static int force_pcs = 0;
598 module_param(force_pcs, int, 0444);
599 MODULE_PARM_DESC(force_pcs, "force honoring or ignoring PCS to work around "
600 "device mis-detection (0=default, 1=ignore PCS, 2=honor PCS)");
603 * piix_pata_cbl_detect - Probe host controller cable detect info
604 * @ap: Port for which cable detect info is desired
606 * Read 80c cable indicator from ATA PCI device's PCI config
607 * register. This register is normally set by firmware (BIOS).
610 * None (inherited from caller).
613 static void ich_pata_cbl_detect(struct ata_port *ap)
615 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
618 /* no 80c support in host controller? */
619 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
622 /* check BIOS cable detect results */
623 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
624 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
625 if ((tmp & mask) == 0)
628 ap->cbl = ATA_CBL_PATA80;
632 ap->cbl = ATA_CBL_PATA40;
636 * piix_pata_prereset - prereset for PATA host controller
641 * None (inherited from caller).
643 static int piix_pata_prereset(struct ata_port *ap)
645 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
647 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
650 ap->cbl = ATA_CBL_PATA40;
651 return ata_std_prereset(ap);
654 static void piix_pata_error_handler(struct ata_port *ap)
656 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
662 * ich_pata_prereset - prereset for PATA host controller
667 * None (inherited from caller).
669 static int ich_pata_prereset(struct ata_port *ap)
671 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
673 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) {
674 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
675 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
679 ich_pata_cbl_detect(ap);
681 return ata_std_prereset(ap);
684 static void ich_pata_error_handler(struct ata_port *ap)
686 ata_bmdma_drive_eh(ap, ich_pata_prereset, ata_std_softreset, NULL,
691 * piix_sata_present_mask - determine present mask for SATA host controller
694 * Reads SATA PCI device's PCI config register Port Configuration
695 * and Status (PCS) to determine port and device availability.
698 * None (inherited from caller).
701 * determined present_mask
703 static unsigned int piix_sata_present_mask(struct ata_port *ap)
705 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
706 struct piix_host_priv *hpriv = ap->host->private_data;
707 const unsigned int *map = hpriv->map;
708 int base = 2 * ap->port_no;
709 unsigned int present_mask = 0;
713 pci_read_config_word(pdev, ICH5_PCS, &pcs);
714 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
716 for (i = 0; i < 2; i++) {
717 port = map[base + i];
720 if ((ap->flags & PIIX_FLAG_IGNORE_PCS) ||
721 (pcs & 1 << (hpriv->map_db->present_shift + port)))
722 present_mask |= 1 << i;
725 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
726 ap->id, pcs, present_mask);
732 * piix_sata_softreset - reset SATA host port via ATA SRST
734 * @classes: resulting classes of attached devices
736 * Reset SATA host port via ATA SRST. On controllers with
737 * reliable PCS present bits, the bits are used to determine
741 * Kernel thread context (may sleep)
744 * 0 on success, -errno otherwise.
746 static int piix_sata_softreset(struct ata_port *ap, unsigned int *classes)
748 unsigned int present_mask;
751 present_mask = piix_sata_present_mask(ap);
753 rc = ata_std_softreset(ap, classes);
757 for (i = 0; i < ATA_MAX_DEVICES; i++) {
758 if (!(present_mask & (1 << i)))
759 classes[i] = ATA_DEV_NONE;
765 static void piix_sata_error_handler(struct ata_port *ap)
767 ata_bmdma_drive_eh(ap, ata_std_prereset, piix_sata_softreset, NULL,
772 * piix_set_piomode - Initialize host controller PATA PIO timings
773 * @ap: Port whose timings we are configuring
776 * Set PIO mode for device, in host controller PCI config space.
779 * None (inherited from caller).
782 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
784 unsigned int pio = adev->pio_mode - XFER_PIO_0;
785 struct pci_dev *dev = to_pci_dev(ap->host->dev);
786 unsigned int is_slave = (adev->devno != 0);
787 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
788 unsigned int slave_port = 0x44;
795 * See Intel Document 298600-004 for the timing programing rules
796 * for ICH controllers.
799 static const /* ISP RTC */
800 u8 timings[][2] = { { 0, 0 },
807 control |= 1; /* TIME1 enable */
808 if (ata_pio_need_iordy(adev))
809 control |= 2; /* IE enable */
811 /* Intel specifies that the PPE functionality is for disk only */
812 if (adev->class == ATA_DEV_ATA)
813 control |= 4; /* PPE enable */
815 pci_read_config_word(dev, master_port, &master_data);
817 /* Enable SITRE (seperate slave timing register) */
818 master_data |= 0x4000;
819 /* enable PPE1, IE1 and TIME1 as needed */
820 master_data |= (control << 4);
821 pci_read_config_byte(dev, slave_port, &slave_data);
822 slave_data &= (ap->port_no ? 0x0f : 0xf0);
823 /* Load the timing nibble for this slave */
824 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
826 /* Master keeps the bits in a different format */
827 master_data &= 0xccf8;
828 /* Enable PPE, IE and TIME as appropriate */
829 master_data |= control;
831 (timings[pio][0] << 12) |
832 (timings[pio][1] << 8);
834 pci_write_config_word(dev, master_port, master_data);
836 pci_write_config_byte(dev, slave_port, slave_data);
838 /* Ensure the UDMA bit is off - it will be turned back on if
842 pci_read_config_byte(dev, 0x48, &udma_enable);
843 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
844 pci_write_config_byte(dev, 0x48, udma_enable);
849 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
850 * @ap: Port whose timings we are configuring
851 * @adev: Drive in question
852 * @udma: udma mode, 0 - 6
853 * @isich: set if the chip is an ICH device
855 * Set UDMA mode for device, in host controller PCI config space.
858 * None (inherited from caller).
861 static void do_pata_set_dmamode (struct ata_port *ap, struct ata_device *adev, int isich)
863 struct pci_dev *dev = to_pci_dev(ap->host->dev);
864 u8 master_port = ap->port_no ? 0x42 : 0x40;
866 u8 speed = adev->dma_mode;
867 int devid = adev->devno + 2 * ap->port_no;
870 static const /* ISP RTC */
871 u8 timings[][2] = { { 0, 0 },
877 pci_read_config_word(dev, master_port, &master_data);
878 pci_read_config_byte(dev, 0x48, &udma_enable);
880 if (speed >= XFER_UDMA_0) {
881 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
884 int u_clock, u_speed;
887 * UDMA is handled by a combination of clock switching and
888 * selection of dividers
890 * Handy rule: Odd modes are UDMATIMx 01, even are 02
891 * except UDMA0 which is 00
893 u_speed = min(2 - (udma & 1), udma);
895 u_clock = 0x1000; /* 100Mhz */
897 u_clock = 1; /* 66Mhz */
899 u_clock = 0; /* 33Mhz */
901 udma_enable |= (1 << devid);
903 /* Load the CT/RP selection */
904 pci_read_config_word(dev, 0x4A, &udma_timing);
905 udma_timing &= ~(3 << (4 * devid));
906 udma_timing |= u_speed << (4 * devid);
907 pci_write_config_word(dev, 0x4A, udma_timing);
910 /* Select a 33/66/100Mhz clock */
911 pci_read_config_word(dev, 0x54, &ideconf);
912 ideconf &= ~(0x1001 << devid);
913 ideconf |= u_clock << devid;
914 /* For ICH or later we should set bit 10 for better
915 performance (WR_PingPong_En) */
916 pci_write_config_word(dev, 0x54, ideconf);
920 * MWDMA is driven by the PIO timings. We must also enable
921 * IORDY unconditionally along with TIME1. PPE has already
922 * been set when the PIO timing was set.
924 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
925 unsigned int control;
927 const unsigned int needed_pio[3] = {
928 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
930 int pio = needed_pio[mwdma] - XFER_PIO_0;
932 control = 3; /* IORDY|TIME1 */
934 /* If the drive MWDMA is faster than it can do PIO then
935 we must force PIO into PIO0 */
937 if (adev->pio_mode < needed_pio[mwdma])
938 /* Enable DMA timing only */
939 control |= 8; /* PIO cycles in PIO0 */
941 if (adev->devno) { /* Slave */
942 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
943 master_data |= control << 4;
944 pci_read_config_byte(dev, 0x44, &slave_data);
945 slave_data &= (0x0F + 0xE1 * ap->port_no);
946 /* Load the matching timing */
947 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
948 pci_write_config_byte(dev, 0x44, slave_data);
949 } else { /* Master */
950 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
951 and master timing bits */
952 master_data |= control;
954 (timings[pio][0] << 12) |
955 (timings[pio][1] << 8);
957 udma_enable &= ~(1 << devid);
958 pci_write_config_word(dev, master_port, master_data);
960 /* Don't scribble on 0x48 if the controller does not support UDMA */
962 pci_write_config_byte(dev, 0x48, udma_enable);
966 * piix_set_dmamode - Initialize host controller PATA DMA timings
967 * @ap: Port whose timings we are configuring
970 * Set MW/UDMA mode for device, in host controller PCI config space.
973 * None (inherited from caller).
976 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
978 do_pata_set_dmamode(ap, adev, 0);
982 * ich_set_dmamode - Initialize host controller PATA DMA timings
983 * @ap: Port whose timings we are configuring
986 * Set MW/UDMA mode for device, in host controller PCI config space.
989 * None (inherited from caller).
992 static void ich_set_dmamode (struct ata_port *ap, struct ata_device *adev)
994 do_pata_set_dmamode(ap, adev, 1);
997 #define AHCI_PCI_BAR 5
998 #define AHCI_GLOBAL_CTL 0x04
999 #define AHCI_ENABLE (1 << 31)
1000 static int piix_disable_ahci(struct pci_dev *pdev)
1006 /* BUG: pci_enable_device has not yet been called. This
1007 * works because this device is usually set up by BIOS.
1010 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1011 !pci_resource_len(pdev, AHCI_PCI_BAR))
1014 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1018 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1019 if (tmp & AHCI_ENABLE) {
1020 tmp &= ~AHCI_ENABLE;
1021 writel(tmp, mmio + AHCI_GLOBAL_CTL);
1023 tmp = readl(mmio + AHCI_GLOBAL_CTL);
1024 if (tmp & AHCI_ENABLE)
1028 pci_iounmap(pdev, mmio);
1033 * piix_check_450nx_errata - Check for problem 450NX setup
1034 * @ata_dev: the PCI device to check
1036 * Check for the present of 450NX errata #19 and errata #25. If
1037 * they are found return an error code so we can turn off DMA
1040 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1042 struct pci_dev *pdev = NULL;
1045 int no_piix_dma = 0;
1047 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
1049 /* Look for 450NX PXB. Check for problem configurations
1050 A PCI quirk checks bit 6 already */
1051 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
1052 pci_read_config_word(pdev, 0x41, &cfg);
1053 /* Only on the original revision: IDE DMA can hang */
1056 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1057 else if (cfg & (1<<14) && rev < 5)
1061 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1062 if (no_piix_dma == 2)
1063 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1067 static void __devinit piix_init_pcs(struct pci_dev *pdev,
1068 struct ata_port_info *pinfo,
1069 const struct piix_map_db *map_db)
1073 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1075 new_pcs = pcs | map_db->port_enable;
1077 if (new_pcs != pcs) {
1078 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1079 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1083 if (force_pcs == 1) {
1084 dev_printk(KERN_INFO, &pdev->dev,
1085 "force ignoring PCS (0x%x)\n", new_pcs);
1086 pinfo[0].flags |= PIIX_FLAG_IGNORE_PCS;
1087 pinfo[1].flags |= PIIX_FLAG_IGNORE_PCS;
1088 } else if (force_pcs == 2) {
1089 dev_printk(KERN_INFO, &pdev->dev,
1090 "force honoring PCS (0x%x)\n", new_pcs);
1091 pinfo[0].flags &= ~PIIX_FLAG_IGNORE_PCS;
1092 pinfo[1].flags &= ~PIIX_FLAG_IGNORE_PCS;
1096 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
1097 struct ata_port_info *pinfo,
1098 const struct piix_map_db *map_db)
1100 struct piix_host_priv *hpriv = pinfo[0].private_data;
1101 const unsigned int *map;
1102 int i, invalid_map = 0;
1105 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1107 map = map_db->map[map_value & map_db->mask];
1109 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1110 for (i = 0; i < 4; i++) {
1122 WARN_ON((i & 1) || map[i + 1] != IDE);
1123 pinfo[i / 2] = piix_port_info[ich_pata_100];
1124 pinfo[i / 2].private_data = hpriv;
1130 printk(" P%d", map[i]);
1132 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1139 dev_printk(KERN_ERR, &pdev->dev,
1140 "invalid MAP value %u\n", map_value);
1143 hpriv->map_db = map_db;
1147 * piix_init_one - Register PIIX ATA PCI device with kernel services
1148 * @pdev: PCI device to register
1149 * @ent: Entry in piix_pci_tbl matching with @pdev
1151 * Called from kernel PCI layer. We probe for combined mode (sigh),
1152 * and then hand over control to libata, for it to do the rest.
1155 * Inherited from PCI layer (may sleep).
1158 * Zero on success, or -ERRNO value.
1161 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1163 static int printed_version;
1164 struct ata_port_info port_info[2];
1165 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
1166 struct piix_host_priv *hpriv;
1167 unsigned long port_flags;
1169 if (!printed_version++)
1170 dev_printk(KERN_DEBUG, &pdev->dev,
1171 "version " DRV_VERSION "\n");
1173 /* no hotplugging support (FIXME) */
1174 if (!in_module_init)
1177 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1181 port_info[0] = piix_port_info[ent->driver_data];
1182 port_info[1] = piix_port_info[ent->driver_data];
1183 port_info[0].private_data = hpriv;
1184 port_info[1].private_data = hpriv;
1186 port_flags = port_info[0].flags;
1188 if (port_flags & PIIX_FLAG_AHCI) {
1190 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
1191 if (tmp == PIIX_AHCI_DEVICE) {
1192 int rc = piix_disable_ahci(pdev);
1198 /* Initialize SATA map */
1199 if (port_flags & ATA_FLAG_SATA) {
1200 piix_init_sata_map(pdev, port_info,
1201 piix_map_db_table[ent->driver_data]);
1202 piix_init_pcs(pdev, port_info,
1203 piix_map_db_table[ent->driver_data]);
1206 /* On ICH5, some BIOSen disable the interrupt using the
1207 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1208 * On ICH6, this bit has the same effect, but only when
1209 * MSI is disabled (and it is disabled, as we don't use
1210 * message-signalled interrupts currently).
1212 if (port_flags & PIIX_FLAG_CHECKINTR)
1215 if (piix_check_450nx_errata(pdev)) {
1216 /* This writes into the master table but it does not
1217 really matter for this errata as we will apply it to
1218 all the PIIX devices on the board */
1219 port_info[0].mwdma_mask = 0;
1220 port_info[0].udma_mask = 0;
1221 port_info[1].mwdma_mask = 0;
1222 port_info[1].udma_mask = 0;
1224 return ata_pci_init_one(pdev, ppinfo, 2);
1227 static void piix_host_stop(struct ata_host *host)
1229 struct piix_host_priv *hpriv = host->private_data;
1231 ata_host_stop(host);
1236 static int __init piix_init(void)
1240 DPRINTK("pci_register_driver\n");
1241 rc = pci_register_driver(&piix_pci_driver);
1251 static void __exit piix_exit(void)
1253 pci_unregister_driver(&piix_pci_driver);
1256 module_init(piix_init);
1257 module_exit(piix_exit);