2 * sata_mv.c - Marvell SATA support
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/device.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
37 #define DRV_NAME "sata_mv"
38 #define DRV_VERSION "0.8"
41 /* BAR's are enumerated in terms of pci_resource_start() terms */
42 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
43 MV_IO_BAR = 2, /* offset 0x18: IO space */
44 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
46 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
47 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
51 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
52 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
53 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
54 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
55 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
57 MV_SATAHC0_REG_BASE = 0x20000,
58 MV_FLASH_CTL = 0x1046c,
59 MV_GPIO_PORT_CTL = 0x104f0,
60 MV_RESET_CFG = 0x180d8,
62 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
63 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
64 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
65 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
67 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
70 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
72 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
73 * CRPB needs alignment on a 256B boundary. Size == 256B
74 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
75 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
77 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
78 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
80 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
81 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
84 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
86 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
90 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
91 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
92 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
93 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
94 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING),
95 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
97 CRQB_FLAG_READ = (1 << 0),
99 CRQB_CMD_ADDR_SHIFT = 8,
100 CRQB_CMD_CS = (0x2 << 11),
101 CRQB_CMD_LAST = (1 << 15),
103 CRPB_FLAG_STATUS_SHIFT = 8,
105 EPRD_FLAG_END_OF_TBL = (1 << 31),
107 /* PCI interface registers */
109 PCI_COMMAND_OFS = 0xc00,
111 PCI_MAIN_CMD_STS_OFS = 0xd30,
112 STOP_PCI_MASTER = (1 << 2),
113 PCI_MASTER_EMPTY = (1 << 3),
114 GLOB_SFT_RST = (1 << 4),
117 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
118 MV_PCI_DISC_TIMER = 0xd04,
119 MV_PCI_MSI_TRIGGER = 0xc38,
120 MV_PCI_SERR_MASK = 0xc28,
121 MV_PCI_XBAR_TMOUT = 0x1d04,
122 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
123 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
124 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
125 MV_PCI_ERR_COMMAND = 0x1d50,
127 PCI_IRQ_CAUSE_OFS = 0x1d58,
128 PCI_IRQ_MASK_OFS = 0x1d5c,
129 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
131 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
132 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
133 PORT0_ERR = (1 << 0), /* shift by port # */
134 PORT0_DONE = (1 << 1), /* shift by port # */
135 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
136 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
138 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
139 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
140 PORTS_0_3_COAL_DONE = (1 << 8),
141 PORTS_4_7_COAL_DONE = (1 << 17),
142 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
143 GPIO_INT = (1 << 22),
144 SELF_INT = (1 << 23),
145 TWSI_INT = (1 << 24),
146 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
147 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
148 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
149 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
151 HC_MAIN_MASKED_IRQS_5 = (PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
154 /* SATAHC registers */
157 HC_IRQ_CAUSE_OFS = 0x14,
158 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
159 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
160 DEV_IRQ = (1 << 8), /* shift by port # */
162 /* Shadow block registers */
164 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
167 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
168 SATA_ACTIVE_OFS = 0x350,
175 SATA_INTERFACE_CTL = 0x050,
177 MV_M2_PREAMP_MASK = 0x7e0,
181 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
182 EDMA_CFG_NCQ = (1 << 5),
183 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
184 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
185 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
187 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
188 EDMA_ERR_IRQ_MASK_OFS = 0xc,
189 EDMA_ERR_D_PAR = (1 << 0),
190 EDMA_ERR_PRD_PAR = (1 << 1),
191 EDMA_ERR_DEV = (1 << 2),
192 EDMA_ERR_DEV_DCON = (1 << 3),
193 EDMA_ERR_DEV_CON = (1 << 4),
194 EDMA_ERR_SERR = (1 << 5),
195 EDMA_ERR_SELF_DIS = (1 << 7),
196 EDMA_ERR_BIST_ASYNC = (1 << 8),
197 EDMA_ERR_CRBQ_PAR = (1 << 9),
198 EDMA_ERR_CRPB_PAR = (1 << 10),
199 EDMA_ERR_INTRL_PAR = (1 << 11),
200 EDMA_ERR_IORDY = (1 << 12),
201 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
202 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
203 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
204 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
205 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
206 EDMA_ERR_TRANS_PROTO = (1 << 31),
207 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
208 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
209 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
210 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
211 EDMA_ERR_LNK_DATA_RX |
212 EDMA_ERR_LNK_DATA_TX |
213 EDMA_ERR_TRANS_PROTO),
215 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
216 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
218 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
219 EDMA_REQ_Q_PTR_SHIFT = 5,
221 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
222 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
223 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
224 EDMA_RSP_Q_PTR_SHIFT = 3,
231 EDMA_IORDY_TMOUT = 0x34,
234 /* Host private flags (hp_flags) */
235 MV_HP_FLAG_MSI = (1 << 0),
236 MV_HP_ERRATA_50XXB0 = (1 << 1),
237 MV_HP_ERRATA_50XXB2 = (1 << 2),
238 MV_HP_ERRATA_60X1B2 = (1 << 3),
239 MV_HP_ERRATA_60X1C0 = (1 << 4),
240 MV_HP_ERRATA_XX42A0 = (1 << 5),
241 MV_HP_50XX = (1 << 6),
242 MV_HP_GEN_IIE = (1 << 7),
244 /* Port private flags (pp_flags) */
245 MV_PP_FLAG_EDMA_EN = (1 << 0),
246 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
249 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
250 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
251 #define IS_GEN_I(hpriv) IS_50XX(hpriv)
252 #define IS_GEN_II(hpriv) IS_60XX(hpriv)
253 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
256 /* Our DMA boundary is determined by an ePRD being unable to handle
257 * anything larger than 64KB
259 MV_DMA_BOUNDARY = 0xffffU,
261 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
263 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
276 /* Command ReQuest Block: 32B */
292 /* Command ResPonse Block: 8B */
299 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
307 struct mv_port_priv {
308 struct mv_crqb *crqb;
310 struct mv_crpb *crpb;
312 struct mv_sg *sg_tbl;
313 dma_addr_t sg_tbl_dma;
317 struct mv_port_signal {
324 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
326 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
327 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
329 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
331 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
332 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
335 struct mv_host_priv {
337 struct mv_port_signal signal[8];
338 const struct mv_hw_ops *ops;
341 static void mv_irq_clear(struct ata_port *ap);
342 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
343 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
344 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
345 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
346 static void mv_phy_reset(struct ata_port *ap);
347 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
348 static int mv_port_start(struct ata_port *ap);
349 static void mv_port_stop(struct ata_port *ap);
350 static void mv_qc_prep(struct ata_queued_cmd *qc);
351 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
352 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
353 static irqreturn_t mv_interrupt(int irq, void *dev_instance);
354 static void mv_eng_timeout(struct ata_port *ap);
355 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
357 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
359 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
360 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
362 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
364 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
365 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
367 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
369 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
370 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
372 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
374 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
375 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
376 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
377 unsigned int port_no);
378 static void mv_stop_and_reset(struct ata_port *ap);
380 static struct scsi_host_template mv_sht = {
381 .module = THIS_MODULE,
383 .ioctl = ata_scsi_ioctl,
384 .queuecommand = ata_scsi_queuecmd,
385 .can_queue = MV_USE_Q_DEPTH,
386 .this_id = ATA_SHT_THIS_ID,
387 .sg_tablesize = MV_MAX_SG_CT / 2,
388 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
389 .emulated = ATA_SHT_EMULATED,
390 .use_clustering = ATA_SHT_USE_CLUSTERING,
391 .proc_name = DRV_NAME,
392 .dma_boundary = MV_DMA_BOUNDARY,
393 .slave_configure = ata_scsi_slave_config,
394 .slave_destroy = ata_scsi_slave_destroy,
395 .bios_param = ata_std_bios_param,
398 static const struct ata_port_operations mv5_ops = {
399 .port_disable = ata_port_disable,
401 .tf_load = ata_tf_load,
402 .tf_read = ata_tf_read,
403 .check_status = ata_check_status,
404 .exec_command = ata_exec_command,
405 .dev_select = ata_std_dev_select,
407 .phy_reset = mv_phy_reset,
409 .qc_prep = mv_qc_prep,
410 .qc_issue = mv_qc_issue,
411 .data_xfer = ata_data_xfer,
413 .eng_timeout = mv_eng_timeout,
415 .irq_handler = mv_interrupt,
416 .irq_clear = mv_irq_clear,
417 .irq_on = ata_irq_on,
418 .irq_ack = ata_irq_ack,
420 .scr_read = mv5_scr_read,
421 .scr_write = mv5_scr_write,
423 .port_start = mv_port_start,
424 .port_stop = mv_port_stop,
427 static const struct ata_port_operations mv6_ops = {
428 .port_disable = ata_port_disable,
430 .tf_load = ata_tf_load,
431 .tf_read = ata_tf_read,
432 .check_status = ata_check_status,
433 .exec_command = ata_exec_command,
434 .dev_select = ata_std_dev_select,
436 .phy_reset = mv_phy_reset,
438 .qc_prep = mv_qc_prep,
439 .qc_issue = mv_qc_issue,
440 .data_xfer = ata_data_xfer,
442 .eng_timeout = mv_eng_timeout,
444 .irq_handler = mv_interrupt,
445 .irq_clear = mv_irq_clear,
446 .irq_on = ata_irq_on,
447 .irq_ack = ata_irq_ack,
449 .scr_read = mv_scr_read,
450 .scr_write = mv_scr_write,
452 .port_start = mv_port_start,
453 .port_stop = mv_port_stop,
456 static const struct ata_port_operations mv_iie_ops = {
457 .port_disable = ata_port_disable,
459 .tf_load = ata_tf_load,
460 .tf_read = ata_tf_read,
461 .check_status = ata_check_status,
462 .exec_command = ata_exec_command,
463 .dev_select = ata_std_dev_select,
465 .phy_reset = mv_phy_reset,
467 .qc_prep = mv_qc_prep_iie,
468 .qc_issue = mv_qc_issue,
469 .data_xfer = ata_data_xfer,
471 .eng_timeout = mv_eng_timeout,
473 .irq_handler = mv_interrupt,
474 .irq_clear = mv_irq_clear,
475 .irq_on = ata_irq_on,
476 .irq_ack = ata_irq_ack,
478 .scr_read = mv_scr_read,
479 .scr_write = mv_scr_write,
481 .port_start = mv_port_start,
482 .port_stop = mv_port_stop,
485 static const struct ata_port_info mv_port_info[] = {
488 .flags = MV_COMMON_FLAGS,
489 .pio_mask = 0x1f, /* pio0-4 */
490 .udma_mask = 0x7f, /* udma0-6 */
491 .port_ops = &mv5_ops,
495 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
496 .pio_mask = 0x1f, /* pio0-4 */
497 .udma_mask = 0x7f, /* udma0-6 */
498 .port_ops = &mv5_ops,
502 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
503 .pio_mask = 0x1f, /* pio0-4 */
504 .udma_mask = 0x7f, /* udma0-6 */
505 .port_ops = &mv5_ops,
509 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
510 .pio_mask = 0x1f, /* pio0-4 */
511 .udma_mask = 0x7f, /* udma0-6 */
512 .port_ops = &mv6_ops,
516 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
518 .pio_mask = 0x1f, /* pio0-4 */
519 .udma_mask = 0x7f, /* udma0-6 */
520 .port_ops = &mv6_ops,
524 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
525 .pio_mask = 0x1f, /* pio0-4 */
526 .udma_mask = 0x7f, /* udma0-6 */
527 .port_ops = &mv_iie_ops,
531 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
532 .pio_mask = 0x1f, /* pio0-4 */
533 .udma_mask = 0x7f, /* udma0-6 */
534 .port_ops = &mv_iie_ops,
538 static const struct pci_device_id mv_pci_tbl[] = {
539 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
540 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
541 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
542 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
544 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
545 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
546 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
547 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
548 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
550 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
552 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
554 { } /* terminate list */
557 static struct pci_driver mv_pci_driver = {
559 .id_table = mv_pci_tbl,
560 .probe = mv_init_one,
561 .remove = ata_pci_remove_one,
564 static const struct mv_hw_ops mv5xxx_ops = {
565 .phy_errata = mv5_phy_errata,
566 .enable_leds = mv5_enable_leds,
567 .read_preamp = mv5_read_preamp,
568 .reset_hc = mv5_reset_hc,
569 .reset_flash = mv5_reset_flash,
570 .reset_bus = mv5_reset_bus,
573 static const struct mv_hw_ops mv6xxx_ops = {
574 .phy_errata = mv6_phy_errata,
575 .enable_leds = mv6_enable_leds,
576 .read_preamp = mv6_read_preamp,
577 .reset_hc = mv6_reset_hc,
578 .reset_flash = mv6_reset_flash,
579 .reset_bus = mv_reset_pci_bus,
585 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
592 static inline void writelfl(unsigned long data, void __iomem *addr)
595 (void) readl(addr); /* flush to avoid PCI posted write */
598 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
600 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
603 static inline unsigned int mv_hc_from_port(unsigned int port)
605 return port >> MV_PORT_HC_SHIFT;
608 static inline unsigned int mv_hardport_from_port(unsigned int port)
610 return port & MV_PORT_MASK;
613 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
616 return mv_hc_base(base, mv_hc_from_port(port));
619 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
621 return mv_hc_base_from_port(base, port) +
622 MV_SATAHC_ARBTR_REG_SZ +
623 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
626 static inline void __iomem *mv_ap_base(struct ata_port *ap)
628 return mv_port_base(ap->host->iomap[MV_PRIMARY_BAR], ap->port_no);
631 static inline int mv_get_hc_count(unsigned long port_flags)
633 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
636 static void mv_irq_clear(struct ata_port *ap)
641 * mv_start_dma - Enable eDMA engine
642 * @base: port base address
643 * @pp: port private data
645 * Verify the local cache of the eDMA state is accurate with a
649 * Inherited from caller.
651 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
653 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
654 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
655 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
657 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
661 * mv_stop_dma - Disable eDMA engine
662 * @ap: ATA channel to manipulate
664 * Verify the local cache of the eDMA state is accurate with a
668 * Inherited from caller.
670 static void mv_stop_dma(struct ata_port *ap)
672 void __iomem *port_mmio = mv_ap_base(ap);
673 struct mv_port_priv *pp = ap->private_data;
677 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
678 /* Disable EDMA if active. The disable bit auto clears.
680 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
681 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
683 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
686 /* now properly wait for the eDMA to stop */
687 for (i = 1000; i > 0; i--) {
688 reg = readl(port_mmio + EDMA_CMD_OFS);
689 if (!(EDMA_EN & reg)) {
696 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
697 /* FIXME: Consider doing a reset here to recover */
702 static void mv_dump_mem(void __iomem *start, unsigned bytes)
705 for (b = 0; b < bytes; ) {
706 DPRINTK("%p: ", start + b);
707 for (w = 0; b < bytes && w < 4; w++) {
708 printk("%08x ",readl(start + b));
716 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
721 for (b = 0; b < bytes; ) {
722 DPRINTK("%02x: ", b);
723 for (w = 0; b < bytes && w < 4; w++) {
724 (void) pci_read_config_dword(pdev,b,&dw);
732 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
733 struct pci_dev *pdev)
736 void __iomem *hc_base = mv_hc_base(mmio_base,
737 port >> MV_PORT_HC_SHIFT);
738 void __iomem *port_base;
739 int start_port, num_ports, p, start_hc, num_hcs, hc;
742 start_hc = start_port = 0;
743 num_ports = 8; /* shld be benign for 4 port devs */
746 start_hc = port >> MV_PORT_HC_SHIFT;
748 num_ports = num_hcs = 1;
750 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
751 num_ports > 1 ? num_ports - 1 : start_port);
754 DPRINTK("PCI config space regs:\n");
755 mv_dump_pci_cfg(pdev, 0x68);
757 DPRINTK("PCI regs:\n");
758 mv_dump_mem(mmio_base+0xc00, 0x3c);
759 mv_dump_mem(mmio_base+0xd00, 0x34);
760 mv_dump_mem(mmio_base+0xf00, 0x4);
761 mv_dump_mem(mmio_base+0x1d00, 0x6c);
762 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
763 hc_base = mv_hc_base(mmio_base, hc);
764 DPRINTK("HC regs (HC %i):\n", hc);
765 mv_dump_mem(hc_base, 0x1c);
767 for (p = start_port; p < start_port + num_ports; p++) {
768 port_base = mv_port_base(mmio_base, p);
769 DPRINTK("EDMA regs (port %i):\n",p);
770 mv_dump_mem(port_base, 0x54);
771 DPRINTK("SATA regs (port %i):\n",p);
772 mv_dump_mem(port_base+0x300, 0x60);
777 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
785 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
788 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
797 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
799 unsigned int ofs = mv_scr_offset(sc_reg_in);
801 if (0xffffffffU != ofs)
802 return readl(mv_ap_base(ap) + ofs);
807 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
809 unsigned int ofs = mv_scr_offset(sc_reg_in);
811 if (0xffffffffU != ofs)
812 writelfl(val, mv_ap_base(ap) + ofs);
815 static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
817 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
819 /* set up non-NCQ EDMA configuration */
820 cfg &= ~(1 << 9); /* disable equeue */
822 if (IS_GEN_I(hpriv)) {
823 cfg &= ~0x1f; /* clear queue depth */
824 cfg |= (1 << 8); /* enab config burst size mask */
827 else if (IS_GEN_II(hpriv)) {
828 cfg &= ~0x1f; /* clear queue depth */
829 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
830 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
833 else if (IS_GEN_IIE(hpriv)) {
834 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
835 cfg |= (1 << 22); /* enab 4-entry host queue cache */
836 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
837 cfg |= (1 << 18); /* enab early completion */
838 cfg |= (1 << 17); /* enab cut-through (dis stor&forwrd) */
839 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
840 cfg &= ~(EDMA_CFG_NCQ | EDMA_CFG_NCQ_GO_ON_ERR); /* clear NCQ */
843 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
847 * mv_port_start - Port specific init/start routine.
848 * @ap: ATA channel to manipulate
850 * Allocate and point to DMA memory, init port private memory,
854 * Inherited from caller.
856 static int mv_port_start(struct ata_port *ap)
858 struct device *dev = ap->host->dev;
859 struct mv_host_priv *hpriv = ap->host->private_data;
860 struct mv_port_priv *pp;
861 void __iomem *port_mmio = mv_ap_base(ap);
866 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
870 mem = dmam_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
874 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
876 rc = ata_pad_alloc(ap, dev);
880 /* First item in chunk of DMA memory:
881 * 32-slot command request table (CRQB), 32 bytes each in size
884 pp->crqb_dma = mem_dma;
886 mem_dma += MV_CRQB_Q_SZ;
889 * 32-slot command response table (CRPB), 8 bytes each in size
892 pp->crpb_dma = mem_dma;
894 mem_dma += MV_CRPB_Q_SZ;
897 * Table of scatter-gather descriptors (ePRD), 16 bytes each
900 pp->sg_tbl_dma = mem_dma;
902 mv_edma_cfg(hpriv, port_mmio);
904 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
905 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
906 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
908 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
909 writelfl(pp->crqb_dma & 0xffffffff,
910 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
912 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
914 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
916 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
917 writelfl(pp->crpb_dma & 0xffffffff,
918 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
920 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
922 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
923 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
925 /* Don't turn on EDMA here...do it before DMA commands only. Else
926 * we'll be unable to send non-data, PIO, etc due to restricted access
929 ap->private_data = pp;
934 * mv_port_stop - Port specific cleanup/stop routine.
935 * @ap: ATA channel to manipulate
937 * Stop DMA, cleanup port memory.
940 * This routine uses the host lock to protect the DMA stop.
942 static void mv_port_stop(struct ata_port *ap)
946 spin_lock_irqsave(&ap->host->lock, flags);
948 spin_unlock_irqrestore(&ap->host->lock, flags);
952 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
953 * @qc: queued command whose SG list to source from
955 * Populate the SG list and mark the last entry.
958 * Inherited from caller.
960 static void mv_fill_sg(struct ata_queued_cmd *qc)
962 struct mv_port_priv *pp = qc->ap->private_data;
964 struct scatterlist *sg;
966 ata_for_each_sg(sg, qc) {
968 u32 sg_len, len, offset;
970 addr = sg_dma_address(sg);
971 sg_len = sg_dma_len(sg);
974 offset = addr & MV_DMA_BOUNDARY;
976 if ((offset + sg_len) > 0x10000)
977 len = 0x10000 - offset;
979 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
980 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
981 pp->sg_tbl[i].flags_size = cpu_to_le32(len & 0xffff);
986 if (!sg_len && ata_sg_is_last(sg, qc))
987 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
994 static inline unsigned mv_inc_q_index(unsigned index)
996 return (index + 1) & MV_MAX_Q_DEPTH_MASK;
999 static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1001 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1002 (last ? CRQB_CMD_LAST : 0);
1003 *cmdw = cpu_to_le16(tmp);
1007 * mv_qc_prep - Host specific command preparation.
1008 * @qc: queued command to prepare
1010 * This routine simply redirects to the general purpose routine
1011 * if command is not DMA. Else, it handles prep of the CRQB
1012 * (command request block), does some sanity checking, and calls
1013 * the SG load routine.
1016 * Inherited from caller.
1018 static void mv_qc_prep(struct ata_queued_cmd *qc)
1020 struct ata_port *ap = qc->ap;
1021 struct mv_port_priv *pp = ap->private_data;
1023 struct ata_taskfile *tf;
1027 if (ATA_PROT_DMA != qc->tf.protocol)
1030 /* Fill in command request block
1032 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1033 flags |= CRQB_FLAG_READ;
1034 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1035 flags |= qc->tag << CRQB_TAG_SHIFT;
1037 /* get current queue index from hardware */
1038 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1039 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1041 pp->crqb[in_index].sg_addr =
1042 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1043 pp->crqb[in_index].sg_addr_hi =
1044 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1045 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1047 cw = &pp->crqb[in_index].ata_cmd[0];
1050 /* Sadly, the CRQB cannot accomodate all registers--there are
1051 * only 11 bytes...so we must pick and choose required
1052 * registers based on the command. So, we drop feature and
1053 * hob_feature for [RW] DMA commands, but they are needed for
1054 * NCQ. NCQ will drop hob_nsect.
1056 switch (tf->command) {
1058 case ATA_CMD_READ_EXT:
1060 case ATA_CMD_WRITE_EXT:
1061 case ATA_CMD_WRITE_FUA_EXT:
1062 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1064 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1065 case ATA_CMD_FPDMA_READ:
1066 case ATA_CMD_FPDMA_WRITE:
1067 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1068 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1070 #endif /* FIXME: remove this line when NCQ added */
1072 /* The only other commands EDMA supports in non-queued and
1073 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1074 * of which are defined/used by Linux. If we get here, this
1075 * driver needs work.
1077 * FIXME: modify libata to give qc_prep a return value and
1078 * return error here.
1080 BUG_ON(tf->command);
1083 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1084 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1085 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1086 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1087 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1088 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1089 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1090 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1091 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1093 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1099 * mv_qc_prep_iie - Host specific command preparation.
1100 * @qc: queued command to prepare
1102 * This routine simply redirects to the general purpose routine
1103 * if command is not DMA. Else, it handles prep of the CRQB
1104 * (command request block), does some sanity checking, and calls
1105 * the SG load routine.
1108 * Inherited from caller.
1110 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1112 struct ata_port *ap = qc->ap;
1113 struct mv_port_priv *pp = ap->private_data;
1114 struct mv_crqb_iie *crqb;
1115 struct ata_taskfile *tf;
1119 if (ATA_PROT_DMA != qc->tf.protocol)
1122 /* Fill in Gen IIE command request block
1124 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1125 flags |= CRQB_FLAG_READ;
1127 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1128 flags |= qc->tag << CRQB_TAG_SHIFT;
1130 /* get current queue index from hardware */
1131 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1132 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1134 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1135 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1136 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1137 crqb->flags = cpu_to_le32(flags);
1140 crqb->ata_cmd[0] = cpu_to_le32(
1141 (tf->command << 16) |
1144 crqb->ata_cmd[1] = cpu_to_le32(
1150 crqb->ata_cmd[2] = cpu_to_le32(
1151 (tf->hob_lbal << 0) |
1152 (tf->hob_lbam << 8) |
1153 (tf->hob_lbah << 16) |
1154 (tf->hob_feature << 24)
1156 crqb->ata_cmd[3] = cpu_to_le32(
1158 (tf->hob_nsect << 8)
1161 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1167 * mv_qc_issue - Initiate a command to the host
1168 * @qc: queued command to start
1170 * This routine simply redirects to the general purpose routine
1171 * if command is not DMA. Else, it sanity checks our local
1172 * caches of the request producer/consumer indices then enables
1173 * DMA and bumps the request producer index.
1176 * Inherited from caller.
1178 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1180 void __iomem *port_mmio = mv_ap_base(qc->ap);
1181 struct mv_port_priv *pp = qc->ap->private_data;
1185 if (ATA_PROT_DMA != qc->tf.protocol) {
1186 /* We're about to send a non-EDMA capable command to the
1187 * port. Turn off EDMA so there won't be problems accessing
1188 * shadow block, etc registers.
1190 mv_stop_dma(qc->ap);
1191 return ata_qc_issue_prot(qc);
1194 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1195 in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1197 /* until we do queuing, the queue should be empty at this point */
1198 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1199 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1201 in_index = mv_inc_q_index(in_index); /* now incr producer index */
1203 mv_start_dma(port_mmio, pp);
1205 /* and write the request in pointer to kick the EDMA to life */
1206 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1207 in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
1208 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1214 * mv_get_crpb_status - get status from most recently completed cmd
1215 * @ap: ATA channel to manipulate
1217 * This routine is for use when the port is in DMA mode, when it
1218 * will be using the CRPB (command response block) method of
1219 * returning command completion information. We check indices
1220 * are good, grab status, and bump the response consumer index to
1221 * prove that we're up to date.
1224 * Inherited from caller.
1226 static u8 mv_get_crpb_status(struct ata_port *ap)
1228 void __iomem *port_mmio = mv_ap_base(ap);
1229 struct mv_port_priv *pp = ap->private_data;
1234 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1235 out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1237 ata_status = le16_to_cpu(pp->crpb[out_index].flags)
1238 >> CRPB_FLAG_STATUS_SHIFT;
1240 /* increment our consumer index... */
1241 out_index = mv_inc_q_index(out_index);
1243 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1244 WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1245 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1247 /* write out our inc'd consumer index so EDMA knows we're caught up */
1248 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1249 out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
1250 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1252 /* Return ATA status register for completed CRPB */
1257 * mv_err_intr - Handle error interrupts on the port
1258 * @ap: ATA channel to manipulate
1259 * @reset_allowed: bool: 0 == don't trigger from reset here
1261 * In most cases, just clear the interrupt and move on. However,
1262 * some cases require an eDMA reset, which is done right before
1263 * the COMRESET in mv_phy_reset(). The SERR case requires a
1264 * clear of pending errors in the SATA SERROR register. Finally,
1265 * if the port disabled DMA, update our cached copy to match.
1268 * Inherited from caller.
1270 static void mv_err_intr(struct ata_port *ap, int reset_allowed)
1272 void __iomem *port_mmio = mv_ap_base(ap);
1273 u32 edma_err_cause, serr = 0;
1275 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1277 if (EDMA_ERR_SERR & edma_err_cause) {
1278 sata_scr_read(ap, SCR_ERROR, &serr);
1279 sata_scr_write_flush(ap, SCR_ERROR, serr);
1281 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1282 struct mv_port_priv *pp = ap->private_data;
1283 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1285 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1286 "SERR: 0x%08x\n", ap->print_id, edma_err_cause, serr);
1288 /* Clear EDMA now that SERR cleanup done */
1289 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1291 /* check for fatal here and recover if needed */
1292 if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
1293 mv_stop_and_reset(ap);
1297 * mv_host_intr - Handle all interrupts on the given host controller
1298 * @host: host specific structure
1299 * @relevant: port error bits relevant to this host controller
1300 * @hc: which host controller we're to look at
1302 * Read then write clear the HC interrupt status then walk each
1303 * port connected to the HC and see if it needs servicing. Port
1304 * success ints are reported in the HC interrupt status reg, the
1305 * port error ints are reported in the higher level main
1306 * interrupt status register and thus are passed in via the
1307 * 'relevant' argument.
1310 * Inherited from caller.
1312 static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
1314 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1315 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1316 struct ata_queued_cmd *qc;
1318 int shift, port, port0, hard_port, handled;
1319 unsigned int err_mask;
1324 port0 = MV_PORTS_PER_HC;
1326 /* we'll need the HC success int register in most cases */
1327 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1329 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1331 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1332 hc,relevant,hc_irq_cause);
1334 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1336 struct ata_port *ap = host->ports[port];
1337 struct mv_port_priv *pp = ap->private_data;
1339 hard_port = mv_hardport_from_port(port); /* range 0..3 */
1340 handled = 0; /* ensure ata_status is set if handled++ */
1342 /* Note that DEV_IRQ might happen spuriously during EDMA,
1343 * and should be ignored in such cases.
1344 * The cause of this is still under investigation.
1346 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1347 /* EDMA: check for response queue interrupt */
1348 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1349 ata_status = mv_get_crpb_status(ap);
1353 /* PIO: check for device (drive) interrupt */
1354 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1355 ata_status = readb(ap->ioaddr.status_addr);
1357 /* ignore spurious intr if drive still BUSY */
1358 if (ata_status & ATA_BUSY) {
1365 if (ap && (ap->flags & ATA_FLAG_DISABLED))
1368 err_mask = ac_err_mask(ata_status);
1370 shift = port << 1; /* (port * 2) */
1371 if (port >= MV_PORTS_PER_HC) {
1372 shift++; /* skip bit 8 in the HC Main IRQ reg */
1374 if ((PORT0_ERR << shift) & relevant) {
1376 err_mask |= AC_ERR_OTHER;
1381 qc = ata_qc_from_tag(ap, ap->active_tag);
1382 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
1383 VPRINTK("port %u IRQ found for qc, "
1384 "ata_status 0x%x\n", port,ata_status);
1385 /* mark qc status appropriately */
1386 if (!(qc->tf.flags & ATA_TFLAG_POLLING)) {
1387 qc->err_mask |= err_mask;
1388 ata_qc_complete(qc);
1399 * @dev_instance: private data; in this case the host structure
1402 * Read the read only register to determine if any host
1403 * controllers have pending interrupts. If so, call lower level
1404 * routine to handle. Also check for PCI errors which are only
1408 * This routine holds the host lock while processing pending
1411 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
1413 struct ata_host *host = dev_instance;
1414 unsigned int hc, handled = 0, n_hcs;
1415 void __iomem *mmio = host->iomap[MV_PRIMARY_BAR];
1416 struct mv_host_priv *hpriv;
1419 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1421 /* check the cases where we either have nothing pending or have read
1422 * a bogus register value which can indicate HW removal or PCI fault
1424 if (!irq_stat || (0xffffffffU == irq_stat))
1427 n_hcs = mv_get_hc_count(host->ports[0]->flags);
1428 spin_lock(&host->lock);
1430 for (hc = 0; hc < n_hcs; hc++) {
1431 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1433 mv_host_intr(host, relevant, hc);
1438 hpriv = host->private_data;
1439 if (IS_60XX(hpriv)) {
1440 /* deal with the interrupt coalescing bits */
1441 if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
1442 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1443 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1444 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1448 if (PCI_ERR & irq_stat) {
1449 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1450 readl(mmio + PCI_IRQ_CAUSE_OFS));
1452 DPRINTK("All regs @ PCI error\n");
1453 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1455 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1458 spin_unlock(&host->lock);
1460 return IRQ_RETVAL(handled);
1463 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1465 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1466 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1468 return hc_mmio + ofs;
1471 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1475 switch (sc_reg_in) {
1479 ofs = sc_reg_in * sizeof(u32);
1488 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1490 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1491 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1492 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1494 if (ofs != 0xffffffffU)
1495 return readl(addr + ofs);
1500 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1502 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1503 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
1504 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1506 if (ofs != 0xffffffffU)
1507 writelfl(val, addr + ofs);
1510 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1515 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1517 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1520 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1522 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1525 mv_reset_pci_bus(pdev, mmio);
1528 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1530 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1533 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1536 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1539 tmp = readl(phy_mmio + MV5_PHY_MODE);
1541 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1542 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1545 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1549 writel(0, mmio + MV_GPIO_PORT_CTL);
1551 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1553 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1555 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1558 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1561 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1562 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1564 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1567 tmp = readl(phy_mmio + MV5_LT_MODE);
1569 writel(tmp, phy_mmio + MV5_LT_MODE);
1571 tmp = readl(phy_mmio + MV5_PHY_CTL);
1574 writel(tmp, phy_mmio + MV5_PHY_CTL);
1577 tmp = readl(phy_mmio + MV5_PHY_MODE);
1579 tmp |= hpriv->signal[port].pre;
1580 tmp |= hpriv->signal[port].amps;
1581 writel(tmp, phy_mmio + MV5_PHY_MODE);
1586 #define ZERO(reg) writel(0, port_mmio + (reg))
1587 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1590 void __iomem *port_mmio = mv_port_base(mmio, port);
1592 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1594 mv_channel_reset(hpriv, mmio, port);
1596 ZERO(0x028); /* command */
1597 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1598 ZERO(0x004); /* timer */
1599 ZERO(0x008); /* irq err cause */
1600 ZERO(0x00c); /* irq err mask */
1601 ZERO(0x010); /* rq bah */
1602 ZERO(0x014); /* rq inp */
1603 ZERO(0x018); /* rq outp */
1604 ZERO(0x01c); /* respq bah */
1605 ZERO(0x024); /* respq outp */
1606 ZERO(0x020); /* respq inp */
1607 ZERO(0x02c); /* test control */
1608 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1612 #define ZERO(reg) writel(0, hc_mmio + (reg))
1613 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1616 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1624 tmp = readl(hc_mmio + 0x20);
1627 writel(tmp, hc_mmio + 0x20);
1631 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1634 unsigned int hc, port;
1636 for (hc = 0; hc < n_hc; hc++) {
1637 for (port = 0; port < MV_PORTS_PER_HC; port++)
1638 mv5_reset_hc_port(hpriv, mmio,
1639 (hc * MV_PORTS_PER_HC) + port);
1641 mv5_reset_one_hc(hpriv, mmio, hc);
1648 #define ZERO(reg) writel(0, mmio + (reg))
1649 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1653 tmp = readl(mmio + MV_PCI_MODE);
1655 writel(tmp, mmio + MV_PCI_MODE);
1657 ZERO(MV_PCI_DISC_TIMER);
1658 ZERO(MV_PCI_MSI_TRIGGER);
1659 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1660 ZERO(HC_MAIN_IRQ_MASK_OFS);
1661 ZERO(MV_PCI_SERR_MASK);
1662 ZERO(PCI_IRQ_CAUSE_OFS);
1663 ZERO(PCI_IRQ_MASK_OFS);
1664 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1665 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1666 ZERO(MV_PCI_ERR_ATTRIBUTE);
1667 ZERO(MV_PCI_ERR_COMMAND);
1671 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1675 mv5_reset_flash(hpriv, mmio);
1677 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1679 tmp |= (1 << 5) | (1 << 6);
1680 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1684 * mv6_reset_hc - Perform the 6xxx global soft reset
1685 * @mmio: base address of the HBA
1687 * This routine only applies to 6xxx parts.
1690 * Inherited from caller.
1692 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1695 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1699 /* Following procedure defined in PCI "main command and status
1703 writel(t | STOP_PCI_MASTER, reg);
1705 for (i = 0; i < 1000; i++) {
1708 if (PCI_MASTER_EMPTY & t) {
1712 if (!(PCI_MASTER_EMPTY & t)) {
1713 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1721 writel(t | GLOB_SFT_RST, reg);
1724 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1726 if (!(GLOB_SFT_RST & t)) {
1727 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1732 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1735 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1738 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1740 if (GLOB_SFT_RST & t) {
1741 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1748 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1751 void __iomem *port_mmio;
1754 tmp = readl(mmio + MV_RESET_CFG);
1755 if ((tmp & (1 << 0)) == 0) {
1756 hpriv->signal[idx].amps = 0x7 << 8;
1757 hpriv->signal[idx].pre = 0x1 << 5;
1761 port_mmio = mv_port_base(mmio, idx);
1762 tmp = readl(port_mmio + PHY_MODE2);
1764 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1765 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1768 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1770 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1773 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1776 void __iomem *port_mmio = mv_port_base(mmio, port);
1778 u32 hp_flags = hpriv->hp_flags;
1780 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1782 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1785 if (fix_phy_mode2) {
1786 m2 = readl(port_mmio + PHY_MODE2);
1789 writel(m2, port_mmio + PHY_MODE2);
1793 m2 = readl(port_mmio + PHY_MODE2);
1794 m2 &= ~((1 << 16) | (1 << 31));
1795 writel(m2, port_mmio + PHY_MODE2);
1800 /* who knows what this magic does */
1801 tmp = readl(port_mmio + PHY_MODE3);
1804 writel(tmp, port_mmio + PHY_MODE3);
1806 if (fix_phy_mode4) {
1809 m4 = readl(port_mmio + PHY_MODE4);
1811 if (hp_flags & MV_HP_ERRATA_60X1B2)
1812 tmp = readl(port_mmio + 0x310);
1814 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1816 writel(m4, port_mmio + PHY_MODE4);
1818 if (hp_flags & MV_HP_ERRATA_60X1B2)
1819 writel(tmp, port_mmio + 0x310);
1822 /* Revert values of pre-emphasis and signal amps to the saved ones */
1823 m2 = readl(port_mmio + PHY_MODE2);
1825 m2 &= ~MV_M2_PREAMP_MASK;
1826 m2 |= hpriv->signal[port].amps;
1827 m2 |= hpriv->signal[port].pre;
1830 /* according to mvSata 3.6.1, some IIE values are fixed */
1831 if (IS_GEN_IIE(hpriv)) {
1836 writel(m2, port_mmio + PHY_MODE2);
1839 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1840 unsigned int port_no)
1842 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1844 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1846 if (IS_60XX(hpriv)) {
1847 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1848 ifctl |= (1 << 7); /* enable gen2i speed */
1849 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
1850 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1853 udelay(25); /* allow reset propagation */
1855 /* Spec never mentions clearing the bit. Marvell's driver does
1856 * clear the bit, however.
1858 writelfl(0, port_mmio + EDMA_CMD_OFS);
1860 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1866 static void mv_stop_and_reset(struct ata_port *ap)
1868 struct mv_host_priv *hpriv = ap->host->private_data;
1869 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
1873 mv_channel_reset(hpriv, mmio, ap->port_no);
1875 __mv_phy_reset(ap, 0);
1878 static inline void __msleep(unsigned int msec, int can_sleep)
1887 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1888 * @ap: ATA channel to manipulate
1890 * Part of this is taken from __sata_phy_reset and modified to
1891 * not sleep since this routine gets called from interrupt level.
1894 * Inherited from caller. This is coded to safe to call at
1895 * interrupt level, i.e. it does not sleep.
1897 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1899 struct mv_port_priv *pp = ap->private_data;
1900 struct mv_host_priv *hpriv = ap->host->private_data;
1901 void __iomem *port_mmio = mv_ap_base(ap);
1902 struct ata_taskfile tf;
1903 struct ata_device *dev = &ap->device[0];
1904 unsigned long timeout;
1908 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1910 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1911 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1912 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1914 /* Issue COMRESET via SControl */
1916 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
1917 __msleep(1, can_sleep);
1919 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
1920 __msleep(20, can_sleep);
1922 timeout = jiffies + msecs_to_jiffies(200);
1924 sata_scr_read(ap, SCR_STATUS, &sstatus);
1925 if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
1928 __msleep(1, can_sleep);
1929 } while (time_before(jiffies, timeout));
1931 /* work around errata */
1932 if (IS_60XX(hpriv) &&
1933 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1935 goto comreset_retry;
1937 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1938 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1939 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1941 if (ata_port_online(ap)) {
1944 sata_scr_read(ap, SCR_STATUS, &sstatus);
1945 ata_port_printk(ap, KERN_INFO,
1946 "no device found (phy stat %08x)\n", sstatus);
1947 ata_port_disable(ap);
1950 ap->cbl = ATA_CBL_SATA;
1952 /* even after SStatus reflects that device is ready,
1953 * it seems to take a while for link to be fully
1954 * established (and thus Status no longer 0x80/0x7F),
1955 * so we poll a bit for that, here.
1959 u8 drv_stat = ata_check_status(ap);
1960 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1962 __msleep(500, can_sleep);
1967 tf.lbah = readb(ap->ioaddr.lbah_addr);
1968 tf.lbam = readb(ap->ioaddr.lbam_addr);
1969 tf.lbal = readb(ap->ioaddr.lbal_addr);
1970 tf.nsect = readb(ap->ioaddr.nsect_addr);
1972 dev->class = ata_dev_classify(&tf);
1973 if (!ata_dev_enabled(dev)) {
1974 VPRINTK("Port disabled post-sig: No device present.\n");
1975 ata_port_disable(ap);
1978 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1980 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1985 static void mv_phy_reset(struct ata_port *ap)
1987 __mv_phy_reset(ap, 1);
1991 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1992 * @ap: ATA channel to manipulate
1994 * Intent is to clear all pending error conditions, reset the
1995 * chip/bus, fail the command, and move on.
1998 * This routine holds the host lock while failing the command.
2000 static void mv_eng_timeout(struct ata_port *ap)
2002 void __iomem *mmio = ap->host->iomap[MV_PRIMARY_BAR];
2003 struct ata_queued_cmd *qc;
2004 unsigned long flags;
2006 ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n");
2007 DPRINTK("All regs @ start of eng_timeout\n");
2008 mv_dump_all_regs(mmio, ap->port_no, to_pci_dev(ap->host->dev));
2010 qc = ata_qc_from_tag(ap, ap->active_tag);
2011 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
2012 mmio, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd);
2014 spin_lock_irqsave(&ap->host->lock, flags);
2016 mv_stop_and_reset(ap);
2017 spin_unlock_irqrestore(&ap->host->lock, flags);
2019 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
2020 if (qc->flags & ATA_QCFLAG_ACTIVE) {
2021 qc->err_mask |= AC_ERR_TIMEOUT;
2022 ata_eh_qc_complete(qc);
2027 * mv_port_init - Perform some early initialization on a single port.
2028 * @port: libata data structure storing shadow register addresses
2029 * @port_mmio: base address of the port
2031 * Initialize shadow register mmio addresses, clear outstanding
2032 * interrupts on the port, and unmask interrupts for the future
2033 * start of the port.
2036 * Inherited from caller.
2038 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2040 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2043 /* PIO related setup
2045 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2047 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2048 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2049 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2050 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2051 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2052 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2054 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2055 /* special case: control/altstatus doesn't have ATA_REG_ address */
2056 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2059 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2061 /* Clear any currently outstanding port interrupt conditions */
2062 serr_ofs = mv_scr_offset(SCR_ERROR);
2063 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2064 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2066 /* unmask all EDMA error interrupts */
2067 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2069 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2070 readl(port_mmio + EDMA_CFG_OFS),
2071 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2072 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2075 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
2076 unsigned int board_idx)
2079 u32 hp_flags = hpriv->hp_flags;
2081 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2085 hpriv->ops = &mv5xxx_ops;
2086 hp_flags |= MV_HP_50XX;
2090 hp_flags |= MV_HP_ERRATA_50XXB0;
2093 hp_flags |= MV_HP_ERRATA_50XXB2;
2096 dev_printk(KERN_WARNING, &pdev->dev,
2097 "Applying 50XXB2 workarounds to unknown rev\n");
2098 hp_flags |= MV_HP_ERRATA_50XXB2;
2105 hpriv->ops = &mv5xxx_ops;
2106 hp_flags |= MV_HP_50XX;
2110 hp_flags |= MV_HP_ERRATA_50XXB0;
2113 hp_flags |= MV_HP_ERRATA_50XXB2;
2116 dev_printk(KERN_WARNING, &pdev->dev,
2117 "Applying B2 workarounds to unknown rev\n");
2118 hp_flags |= MV_HP_ERRATA_50XXB2;
2125 hpriv->ops = &mv6xxx_ops;
2129 hp_flags |= MV_HP_ERRATA_60X1B2;
2132 hp_flags |= MV_HP_ERRATA_60X1C0;
2135 dev_printk(KERN_WARNING, &pdev->dev,
2136 "Applying B2 workarounds to unknown rev\n");
2137 hp_flags |= MV_HP_ERRATA_60X1B2;
2144 hpriv->ops = &mv6xxx_ops;
2146 hp_flags |= MV_HP_GEN_IIE;
2150 hp_flags |= MV_HP_ERRATA_XX42A0;
2153 hp_flags |= MV_HP_ERRATA_60X1C0;
2156 dev_printk(KERN_WARNING, &pdev->dev,
2157 "Applying 60X1C0 workarounds to unknown rev\n");
2158 hp_flags |= MV_HP_ERRATA_60X1C0;
2164 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2168 hpriv->hp_flags = hp_flags;
2174 * mv_init_host - Perform some early initialization of the host.
2175 * @pdev: host PCI device
2176 * @probe_ent: early data struct representing the host
2178 * If possible, do an early global reset of the host. Then do
2179 * our port init and clear/unmask all/relevant host interrupts.
2182 * Inherited from caller.
2184 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2185 unsigned int board_idx)
2187 int rc = 0, n_hc, port, hc;
2188 void __iomem *mmio = probe_ent->iomap[MV_PRIMARY_BAR];
2189 struct mv_host_priv *hpriv = probe_ent->private_data;
2191 /* global interrupt mask */
2192 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2194 rc = mv_chip_id(pdev, hpriv, board_idx);
2198 n_hc = mv_get_hc_count(probe_ent->port_flags);
2199 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2201 for (port = 0; port < probe_ent->n_ports; port++)
2202 hpriv->ops->read_preamp(hpriv, port, mmio);
2204 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2208 hpriv->ops->reset_flash(hpriv, mmio);
2209 hpriv->ops->reset_bus(pdev, mmio);
2210 hpriv->ops->enable_leds(hpriv, mmio);
2212 for (port = 0; port < probe_ent->n_ports; port++) {
2213 if (IS_60XX(hpriv)) {
2214 void __iomem *port_mmio = mv_port_base(mmio, port);
2216 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2217 ifctl |= (1 << 7); /* enable gen2i speed */
2218 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2219 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2222 hpriv->ops->phy_errata(hpriv, mmio, port);
2225 for (port = 0; port < probe_ent->n_ports; port++) {
2226 void __iomem *port_mmio = mv_port_base(mmio, port);
2227 mv_port_init(&probe_ent->port[port], port_mmio);
2230 for (hc = 0; hc < n_hc; hc++) {
2231 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2233 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2234 "(before clear)=0x%08x\n", hc,
2235 readl(hc_mmio + HC_CFG_OFS),
2236 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2238 /* Clear any currently outstanding hc interrupt conditions */
2239 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2242 /* Clear any currently outstanding host interrupt conditions */
2243 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2245 /* and unmask interrupt generation for host regs */
2246 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2249 writelfl(~HC_MAIN_MASKED_IRQS_5, mmio + HC_MAIN_IRQ_MASK_OFS);
2251 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2253 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2254 "PCI int cause/mask=0x%08x/0x%08x\n",
2255 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2256 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2257 readl(mmio + PCI_IRQ_CAUSE_OFS),
2258 readl(mmio + PCI_IRQ_MASK_OFS));
2265 * mv_print_info - Dump key info to kernel log for perusal.
2266 * @probe_ent: early data struct representing the host
2268 * FIXME: complete this.
2271 * Inherited from caller.
2273 static void mv_print_info(struct ata_probe_ent *probe_ent)
2275 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2276 struct mv_host_priv *hpriv = probe_ent->private_data;
2280 /* Use this to determine the HW stepping of the chip so we know
2281 * what errata to workaround
2283 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2285 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2288 else if (scc == 0x01)
2293 dev_printk(KERN_INFO, &pdev->dev,
2294 "%u slots %u ports %s mode IRQ via %s\n",
2295 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2296 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2300 * mv_init_one - handle a positive probe of a Marvell host
2301 * @pdev: PCI device found
2302 * @ent: PCI device ID entry for the matched host
2305 * Inherited from caller.
2307 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2309 static int printed_version = 0;
2310 struct device *dev = &pdev->dev;
2311 struct ata_probe_ent *probe_ent;
2312 struct mv_host_priv *hpriv;
2313 unsigned int board_idx = (unsigned int)ent->driver_data;
2316 if (!printed_version++)
2317 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2319 rc = pcim_enable_device(pdev);
2322 pci_set_master(pdev);
2324 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
2326 pcim_pin_device(pdev);
2330 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
2331 if (probe_ent == NULL)
2334 probe_ent->dev = pci_dev_to_dev(pdev);
2335 INIT_LIST_HEAD(&probe_ent->node);
2337 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2341 probe_ent->sht = mv_port_info[board_idx].sht;
2342 probe_ent->port_flags = mv_port_info[board_idx].flags;
2343 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2344 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2345 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2347 probe_ent->irq = pdev->irq;
2348 probe_ent->irq_flags = IRQF_SHARED;
2349 probe_ent->iomap = pcim_iomap_table(pdev);
2350 probe_ent->private_data = hpriv;
2352 /* initialize adapter */
2353 rc = mv_init_host(pdev, probe_ent, board_idx);
2357 /* Enable interrupts */
2358 if (msi && pci_enable_msi(pdev))
2361 mv_dump_pci_cfg(pdev, 0x68);
2362 mv_print_info(probe_ent);
2364 if (ata_device_add(probe_ent) == 0)
2367 devm_kfree(dev, probe_ent);
2371 static int __init mv_init(void)
2373 return pci_register_driver(&mv_pci_driver);
2376 static void __exit mv_exit(void)
2378 pci_unregister_driver(&mv_pci_driver);
2381 MODULE_AUTHOR("Brett Russ");
2382 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2383 MODULE_LICENSE("GPL");
2384 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2385 MODULE_VERSION(DRV_VERSION);
2387 module_param(msi, int, 0444);
2388 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2390 module_init(mv_init);
2391 module_exit(mv_exit);