2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/device.h>
41 #include <scsi/scsi.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
45 #include "sata_promise.h"
47 #define DRV_NAME "sata_promise"
48 #define DRV_VERSION "1.05"
54 /* register offsets */
55 PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */
56 PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */
57 PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */
58 PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */
59 PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */
60 PDC_DEVICE = 0x18, /* Device/Head reg (per port) */
61 PDC_COMMAND = 0x1C, /* Command/status reg (per port) */
62 PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */
63 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
64 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
65 PDC_FLASH_CTL = 0x44, /* Flash control register */
66 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
67 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
68 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
69 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
70 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
71 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
73 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
74 (1<<8) | (1<<9) | (1<<10),
76 board_2037x = 0, /* FastTrak S150 TX2plus */
77 board_20319 = 1, /* FastTrak S150 TX4 */
78 board_20619 = 2, /* FastTrak TX4000 */
79 board_2057x = 3, /* SATAII150 Tx2plus */
80 board_40518 = 4, /* SATAII150 Tx4 */
82 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
84 /* Sequence counter control registers bit definitions */
85 PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */
87 /* Feature register values */
88 PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */
89 PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */
91 /* Device/Head register values */
92 PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */
94 /* PDC_CTLSTAT bit definitions */
95 PDC_DMA_ENABLE = (1 << 7),
96 PDC_IRQ_DISABLE = (1 << 10),
97 PDC_RESET = (1 << 11), /* HDMA reset */
99 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
101 ATA_FLAG_PIO_POLLING,
104 PDC_FLAG_GEN_II = (1 << 0),
108 struct pdc_port_priv {
113 struct pdc_host_priv {
115 unsigned long port_flags[ATA_MAX_PORTS];
118 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
119 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
120 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
121 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
122 static int pdc_port_start(struct ata_port *ap);
123 static void pdc_qc_prep(struct ata_queued_cmd *qc);
124 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
125 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
126 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
127 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc);
128 static void pdc_irq_clear(struct ata_port *ap);
129 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
130 static void pdc_freeze(struct ata_port *ap);
131 static void pdc_thaw(struct ata_port *ap);
132 static void pdc_error_handler(struct ata_port *ap);
133 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
136 static struct scsi_host_template pdc_ata_sht = {
137 .module = THIS_MODULE,
139 .ioctl = ata_scsi_ioctl,
140 .queuecommand = ata_scsi_queuecmd,
141 .can_queue = ATA_DEF_QUEUE,
142 .this_id = ATA_SHT_THIS_ID,
143 .sg_tablesize = LIBATA_MAX_PRD,
144 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
145 .emulated = ATA_SHT_EMULATED,
146 .use_clustering = ATA_SHT_USE_CLUSTERING,
147 .proc_name = DRV_NAME,
148 .dma_boundary = ATA_DMA_BOUNDARY,
149 .slave_configure = ata_scsi_slave_config,
150 .slave_destroy = ata_scsi_slave_destroy,
151 .bios_param = ata_std_bios_param,
154 static const struct ata_port_operations pdc_sata_ops = {
155 .port_disable = ata_port_disable,
156 .tf_load = pdc_tf_load_mmio,
157 .tf_read = ata_tf_read,
158 .check_status = ata_check_status,
159 .exec_command = pdc_exec_command_mmio,
160 .dev_select = ata_std_dev_select,
161 .check_atapi_dma = pdc_check_atapi_dma,
163 .qc_prep = pdc_qc_prep,
164 .qc_issue = pdc_qc_issue_prot,
165 .freeze = pdc_freeze,
167 .error_handler = pdc_error_handler,
168 .post_internal_cmd = pdc_post_internal_cmd,
169 .data_xfer = ata_data_xfer,
170 .irq_handler = pdc_interrupt,
171 .irq_clear = pdc_irq_clear,
172 .irq_on = ata_irq_on,
173 .irq_ack = ata_irq_ack,
175 .scr_read = pdc_sata_scr_read,
176 .scr_write = pdc_sata_scr_write,
177 .port_start = pdc_port_start,
180 /* First-generation chips need a more restrictive ->check_atapi_dma op */
181 static const struct ata_port_operations pdc_old_sata_ops = {
182 .port_disable = ata_port_disable,
183 .tf_load = pdc_tf_load_mmio,
184 .tf_read = ata_tf_read,
185 .check_status = ata_check_status,
186 .exec_command = pdc_exec_command_mmio,
187 .dev_select = ata_std_dev_select,
188 .check_atapi_dma = pdc_old_check_atapi_dma,
190 .qc_prep = pdc_qc_prep,
191 .qc_issue = pdc_qc_issue_prot,
192 .freeze = pdc_freeze,
194 .error_handler = pdc_error_handler,
195 .post_internal_cmd = pdc_post_internal_cmd,
196 .data_xfer = ata_data_xfer,
197 .irq_handler = pdc_interrupt,
198 .irq_clear = pdc_irq_clear,
199 .irq_on = ata_irq_on,
200 .irq_ack = ata_irq_ack,
202 .scr_read = pdc_sata_scr_read,
203 .scr_write = pdc_sata_scr_write,
204 .port_start = pdc_port_start,
207 static const struct ata_port_operations pdc_pata_ops = {
208 .port_disable = ata_port_disable,
209 .tf_load = pdc_tf_load_mmio,
210 .tf_read = ata_tf_read,
211 .check_status = ata_check_status,
212 .exec_command = pdc_exec_command_mmio,
213 .dev_select = ata_std_dev_select,
214 .check_atapi_dma = pdc_check_atapi_dma,
216 .qc_prep = pdc_qc_prep,
217 .qc_issue = pdc_qc_issue_prot,
218 .freeze = pdc_freeze,
220 .error_handler = pdc_error_handler,
221 .data_xfer = ata_data_xfer,
222 .irq_handler = pdc_interrupt,
223 .irq_clear = pdc_irq_clear,
224 .irq_on = ata_irq_on,
225 .irq_ack = ata_irq_ack,
227 .port_start = pdc_port_start,
230 static const struct ata_port_info pdc_port_info[] = {
234 .flags = PDC_COMMON_FLAGS,
235 .pio_mask = 0x1f, /* pio0-4 */
236 .mwdma_mask = 0x07, /* mwdma0-2 */
237 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
238 .port_ops = &pdc_old_sata_ops,
244 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
245 .pio_mask = 0x1f, /* pio0-4 */
246 .mwdma_mask = 0x07, /* mwdma0-2 */
247 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
248 .port_ops = &pdc_old_sata_ops,
254 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
255 .pio_mask = 0x1f, /* pio0-4 */
256 .mwdma_mask = 0x07, /* mwdma0-2 */
257 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
258 .port_ops = &pdc_pata_ops,
264 .flags = PDC_COMMON_FLAGS,
265 .pio_mask = 0x1f, /* pio0-4 */
266 .mwdma_mask = 0x07, /* mwdma0-2 */
267 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
268 .port_ops = &pdc_sata_ops,
274 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
275 .pio_mask = 0x1f, /* pio0-4 */
276 .mwdma_mask = 0x07, /* mwdma0-2 */
277 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
278 .port_ops = &pdc_sata_ops,
282 static const struct pci_device_id pdc_ata_pci_tbl[] = {
283 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
284 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
285 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
286 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
287 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
288 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
289 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
290 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
291 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
292 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
294 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
295 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
296 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
297 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
298 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
299 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
301 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
303 { } /* terminate list */
307 static struct pci_driver pdc_ata_pci_driver = {
309 .id_table = pdc_ata_pci_tbl,
310 .probe = pdc_ata_init_one,
311 .remove = ata_pci_remove_one,
315 static int pdc_port_start(struct ata_port *ap)
317 struct device *dev = ap->host->dev;
318 struct pdc_host_priv *hp = ap->host->private_data;
319 struct pdc_port_priv *pp;
322 /* fix up port flags and cable type for SATA+PATA chips */
323 ap->flags |= hp->port_flags[ap->port_no];
324 if (ap->flags & ATA_FLAG_SATA)
325 ap->cbl = ATA_CBL_SATA;
327 rc = ata_port_start(ap);
331 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
335 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
339 ap->private_data = pp;
341 /* fix up PHYMODE4 align timing */
342 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
343 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
346 tmp = readl(mmio + 0x014);
347 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
348 writel(tmp, mmio + 0x014);
354 static void pdc_reset_port(struct ata_port *ap)
356 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
360 for (i = 11; i > 0; i--) {
373 readl(mmio); /* flush */
376 static void pdc_pata_cbl_detect(struct ata_port *ap)
379 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
384 ap->cbl = ATA_CBL_PATA40;
385 ap->udma_mask &= ATA_UDMA_MASK_40C;
387 ap->cbl = ATA_CBL_PATA80;
390 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
392 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
394 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
398 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
401 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
403 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
406 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
408 struct ata_port *ap = qc->ap;
409 dma_addr_t sg_table = ap->prd_dma;
410 unsigned int cdb_len = qc->dev->cdb_len;
412 struct pdc_port_priv *pp = ap->private_data;
414 u32 *buf32 = (u32 *) buf;
415 unsigned int dev_sel, feature, nbytes;
417 /* set control bits (byte 0), zero delay seq id (byte 3),
418 * and seq id (byte 2)
420 switch (qc->tf.protocol) {
421 case ATA_PROT_ATAPI_DMA:
422 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
423 buf32[0] = cpu_to_le32(PDC_PKT_READ);
427 case ATA_PROT_ATAPI_NODATA:
428 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
434 buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */
435 buf32[2] = 0; /* no next-packet */
438 if (sata_scr_valid(ap)) {
439 dev_sel = PDC_DEVICE_SATA;
441 dev_sel = ATA_DEVICE_OBS;
442 if (qc->dev->devno != 0)
445 buf[12] = (1 << 5) | ATA_REG_DEVICE;
447 buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
448 buf[15] = dev_sel; /* once more, waiting for BSY to clear */
450 buf[16] = (1 << 5) | ATA_REG_NSECT;
452 buf[18] = (1 << 5) | ATA_REG_LBAL;
455 /* set feature and byte counter registers */
456 if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
457 feature = PDC_FEATURE_ATAPI_PIO;
458 /* set byte counter register to real transfer byte count */
463 feature = PDC_FEATURE_ATAPI_DMA;
464 /* set byte counter register to 0 */
467 buf[20] = (1 << 5) | ATA_REG_FEATURE;
469 buf[22] = (1 << 5) | ATA_REG_BYTEL;
470 buf[23] = nbytes & 0xFF;
471 buf[24] = (1 << 5) | ATA_REG_BYTEH;
472 buf[25] = (nbytes >> 8) & 0xFF;
474 /* send ATAPI packet command 0xA0 */
475 buf[26] = (1 << 5) | ATA_REG_CMD;
476 buf[27] = ATA_CMD_PACKET;
478 /* select drive and check DRQ */
479 buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
482 /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
483 BUG_ON(cdb_len & ~0x1E);
485 /* append the CDB as the final part */
486 buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
487 memcpy(buf+31, cdb, cdb_len);
490 static void pdc_qc_prep(struct ata_queued_cmd *qc)
492 struct pdc_port_priv *pp = qc->ap->private_data;
497 switch (qc->tf.protocol) {
502 case ATA_PROT_NODATA:
503 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
504 qc->dev->devno, pp->pkt);
506 if (qc->tf.flags & ATA_TFLAG_LBA48)
507 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
509 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
511 pdc_pkt_footer(&qc->tf, pp->pkt, i);
518 case ATA_PROT_ATAPI_DMA:
521 case ATA_PROT_ATAPI_NODATA:
530 static void pdc_freeze(struct ata_port *ap)
532 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
535 tmp = readl(mmio + PDC_CTLSTAT);
536 tmp |= PDC_IRQ_DISABLE;
537 tmp &= ~PDC_DMA_ENABLE;
538 writel(tmp, mmio + PDC_CTLSTAT);
539 readl(mmio + PDC_CTLSTAT); /* flush */
542 static void pdc_thaw(struct ata_port *ap)
544 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
548 readl(mmio + PDC_INT_SEQMASK);
550 /* turn IRQ back on */
551 tmp = readl(mmio + PDC_CTLSTAT);
552 tmp &= ~PDC_IRQ_DISABLE;
553 writel(tmp, mmio + PDC_CTLSTAT);
554 readl(mmio + PDC_CTLSTAT); /* flush */
557 static int pdc_pre_reset(struct ata_port *ap)
559 if (!sata_scr_valid(ap))
560 pdc_pata_cbl_detect(ap);
561 return ata_std_prereset(ap);
564 static void pdc_error_handler(struct ata_port *ap)
566 ata_reset_fn_t hardreset;
568 if (!(ap->pflags & ATA_PFLAG_FROZEN))
572 if (sata_scr_valid(ap))
573 hardreset = sata_std_hardreset;
575 /* perform recovery */
576 ata_do_eh(ap, pdc_pre_reset, ata_std_softreset, hardreset,
580 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
582 struct ata_port *ap = qc->ap;
584 if (qc->flags & ATA_QCFLAG_FAILED)
585 qc->err_mask |= AC_ERR_OTHER;
587 /* make DMA engine forget about the failed command */
592 static inline unsigned int pdc_host_intr( struct ata_port *ap,
593 struct ata_queued_cmd *qc)
595 unsigned int handled = 0;
597 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
600 if (tmp & PDC_ERR_MASK) {
601 qc->err_mask |= AC_ERR_DEV;
605 switch (qc->tf.protocol) {
607 case ATA_PROT_NODATA:
608 case ATA_PROT_ATAPI_DMA:
609 case ATA_PROT_ATAPI_NODATA:
610 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
616 ap->stats.idle_irq++;
623 static void pdc_irq_clear(struct ata_port *ap)
625 struct ata_host *host = ap->host;
626 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
628 readl(mmio + PDC_INT_SEQMASK);
631 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
633 struct ata_host *host = dev_instance;
637 unsigned int handled = 0;
638 void __iomem *mmio_base;
642 if (!host || !host->iomap[PDC_MMIO_BAR]) {
643 VPRINTK("QUICK EXIT\n");
647 mmio_base = host->iomap[PDC_MMIO_BAR];
649 /* reading should also clear interrupts */
650 mask = readl(mmio_base + PDC_INT_SEQMASK);
652 if (mask == 0xffffffff) {
653 VPRINTK("QUICK EXIT 2\n");
657 spin_lock(&host->lock);
659 mask &= 0xffff; /* only 16 tags possible */
661 VPRINTK("QUICK EXIT 3\n");
665 writel(mask, mmio_base + PDC_INT_SEQMASK);
667 for (i = 0; i < host->n_ports; i++) {
668 VPRINTK("port %u\n", i);
670 tmp = mask & (1 << (i + 1));
672 !(ap->flags & ATA_FLAG_DISABLED)) {
673 struct ata_queued_cmd *qc;
675 qc = ata_qc_from_tag(ap, ap->active_tag);
676 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
677 handled += pdc_host_intr(ap, qc);
684 spin_unlock(&host->lock);
685 return IRQ_RETVAL(handled);
688 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
690 struct ata_port *ap = qc->ap;
691 struct pdc_port_priv *pp = ap->private_data;
692 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
693 unsigned int port_no = ap->port_no;
694 u8 seq = (u8) (port_no + 1);
696 VPRINTK("ENTER, ap %p\n", ap);
698 writel(0x00000001, mmio + (seq * 4));
699 readl(mmio + (seq * 4)); /* flush */
702 wmb(); /* flush PRD, pkt writes */
703 writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
704 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
707 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
709 switch (qc->tf.protocol) {
710 case ATA_PROT_ATAPI_NODATA:
711 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
714 case ATA_PROT_ATAPI_DMA:
716 case ATA_PROT_NODATA:
717 pdc_packet_start(qc);
724 return ata_qc_issue_prot(qc);
727 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
729 WARN_ON (tf->protocol == ATA_PROT_DMA ||
730 tf->protocol == ATA_PROT_NODATA);
735 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
737 WARN_ON (tf->protocol == ATA_PROT_DMA ||
738 tf->protocol == ATA_PROT_NODATA);
739 ata_exec_command(ap, tf);
742 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
744 u8 *scsicmd = qc->scsicmd->cmnd;
745 int pio = 1; /* atapi dma off by default */
747 /* Whitelist commands that may use DMA. */
748 switch (scsicmd[0]) {
755 case 0xad: /* READ_DVD_STRUCTURE */
756 case 0xbe: /* READ_CD */
759 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
760 if (scsicmd[0] == WRITE_10) {
762 lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
763 if (lba >= 0xFFFF4FA2)
769 static int pdc_old_check_atapi_dma(struct ata_queued_cmd *qc)
771 struct ata_port *ap = qc->ap;
773 /* First generation chips cannot use ATAPI DMA on SATA ports */
774 if (sata_scr_valid(ap))
776 return pdc_check_atapi_dma(qc);
779 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
781 port->cmd_addr = base;
782 port->data_addr = base;
784 port->error_addr = base + 0x4;
785 port->nsect_addr = base + 0x8;
786 port->lbal_addr = base + 0xc;
787 port->lbam_addr = base + 0x10;
788 port->lbah_addr = base + 0x14;
789 port->device_addr = base + 0x18;
791 port->status_addr = base + 0x1c;
792 port->altstatus_addr =
793 port->ctl_addr = base + 0x38;
797 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
799 void __iomem *mmio = pe->iomap[PDC_MMIO_BAR];
800 struct pdc_host_priv *hp = pe->private_data;
804 if (hp->flags & PDC_FLAG_GEN_II)
805 hotplug_offset = PDC2_SATA_PLUG_CSR;
807 hotplug_offset = PDC_SATA_PLUG_CSR;
810 * Except for the hotplug stuff, this is voodoo from the
811 * Promise driver. Label this entire section
812 * "TODO: figure out why we do this"
815 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
816 tmp = readl(mmio + PDC_FLASH_CTL);
817 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
818 if (!(hp->flags & PDC_FLAG_GEN_II))
819 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
820 writel(tmp, mmio + PDC_FLASH_CTL);
822 /* clear plug/unplug flags for all ports */
823 tmp = readl(mmio + hotplug_offset);
824 writel(tmp | 0xff, mmio + hotplug_offset);
826 /* mask plug/unplug ints */
827 tmp = readl(mmio + hotplug_offset);
828 writel(tmp | 0xff0000, mmio + hotplug_offset);
830 /* don't initialise TBG or SLEW on 2nd generation chips */
831 if (hp->flags & PDC_FLAG_GEN_II)
834 /* reduce TBG clock to 133 Mhz. */
835 tmp = readl(mmio + PDC_TBG_MODE);
836 tmp &= ~0x30000; /* clear bit 17, 16*/
837 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
838 writel(tmp, mmio + PDC_TBG_MODE);
840 readl(mmio + PDC_TBG_MODE); /* flush */
843 /* adjust slew rate control register. */
844 tmp = readl(mmio + PDC_SLEW_CTL);
845 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
846 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
847 writel(tmp, mmio + PDC_SLEW_CTL);
850 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
852 static int printed_version;
853 struct ata_probe_ent *probe_ent;
854 struct pdc_host_priv *hp;
856 unsigned int board_idx = (unsigned int) ent->driver_data;
860 if (!printed_version++)
861 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
863 rc = pcim_enable_device(pdev);
867 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
869 pcim_pin_device(pdev);
873 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
876 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
880 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
881 if (probe_ent == NULL)
884 probe_ent->dev = pci_dev_to_dev(pdev);
885 INIT_LIST_HEAD(&probe_ent->node);
887 hp = devm_kzalloc(&pdev->dev, sizeof(*hp), GFP_KERNEL);
891 probe_ent->private_data = hp;
893 probe_ent->sht = pdc_port_info[board_idx].sht;
894 probe_ent->port_flags = pdc_port_info[board_idx].flags;
895 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
896 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
897 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
898 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
900 probe_ent->irq = pdev->irq;
901 probe_ent->irq_flags = IRQF_SHARED;
902 probe_ent->iomap = pcim_iomap_table(pdev);
904 base = probe_ent->iomap[PDC_MMIO_BAR];
906 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
907 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
909 probe_ent->port[0].scr_addr = base + 0x400;
910 probe_ent->port[1].scr_addr = base + 0x500;
912 /* notice 4-port boards */
915 hp->flags |= PDC_FLAG_GEN_II;
918 probe_ent->n_ports = 4;
920 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
921 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
923 probe_ent->port[2].scr_addr = base + 0x600;
924 probe_ent->port[3].scr_addr = base + 0x700;
927 hp->flags |= PDC_FLAG_GEN_II;
930 /* TX2plus boards also have a PATA port */
931 tmp = readb(base + PDC_FLASH_CTL+1);
933 probe_ent->n_ports = 3;
934 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
935 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
936 printk(KERN_INFO DRV_NAME " PATA port found\n");
938 probe_ent->n_ports = 2;
939 hp->port_flags[0] = ATA_FLAG_SATA;
940 hp->port_flags[1] = ATA_FLAG_SATA;
943 probe_ent->n_ports = 4;
945 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
946 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
948 probe_ent->port[2].scr_addr = base + 0x600;
949 probe_ent->port[3].scr_addr = base + 0x700;
956 pci_set_master(pdev);
958 /* initialize adapter */
959 pdc_host_init(board_idx, probe_ent);
961 if (!ata_device_add(probe_ent))
964 devm_kfree(&pdev->dev, probe_ent);
969 static int __init pdc_ata_init(void)
971 return pci_register_driver(&pdc_ata_pci_driver);
975 static void __exit pdc_ata_exit(void)
977 pci_unregister_driver(&pdc_ata_pci_driver);
981 MODULE_AUTHOR("Jeff Garzik");
982 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
983 MODULE_LICENSE("GPL");
984 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
985 MODULE_VERSION(DRV_VERSION);
987 module_init(pdc_ata_init);
988 module_exit(pdc_ata_exit);