2 * RocketPort device driver for Linux
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Kernel Synchronization:
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
42 /****** Defines ******/
43 #define ROCKET_PARANOIA_CHECK
44 #define ROCKET_DISABLE_SIMUSAGE
46 #undef ROCKET_SOFT_FLOW
47 #undef ROCKET_DEBUG_OPEN
48 #undef ROCKET_DEBUG_INTR
49 #undef ROCKET_DEBUG_WRITE
50 #undef ROCKET_DEBUG_FLOW
51 #undef ROCKET_DEBUG_THROTTLE
52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53 #undef ROCKET_DEBUG_RECEIVE
54 #undef ROCKET_DEBUG_HANGUP
56 #undef ROCKET_DEBUG_IO
58 #define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
60 /****** Kernel includes ******/
62 #include <linux/module.h>
63 #include <linux/errno.h>
64 #include <linux/major.h>
65 #include <linux/kernel.h>
66 #include <linux/signal.h>
67 #include <linux/slab.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/tty.h>
73 #include <linux/tty_driver.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/string.h>
77 #include <linux/fcntl.h>
78 #include <linux/ptrace.h>
79 #include <linux/mutex.h>
80 #include <linux/ioport.h>
81 #include <linux/delay.h>
82 #include <linux/completion.h>
83 #include <linux/wait.h>
84 #include <linux/pci.h>
85 #include <linux/uaccess.h>
86 #include <asm/atomic.h>
87 #include <asm/unaligned.h>
88 #include <linux/bitops.h>
89 #include <linux/spinlock.h>
90 #include <linux/init.h>
92 /****** RocketPort includes ******/
94 #include "rocket_int.h"
97 #define ROCKET_VERSION "2.09"
98 #define ROCKET_DATE "12-June-2003"
100 /****** RocketPort Local Variables ******/
102 static void rp_do_poll(unsigned long dummy);
104 static struct tty_driver *rocket_driver;
106 static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
110 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113 static atomic_t rp_num_ports_open; /* Number of serial ports open */
114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
116 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117 static unsigned long board2;
118 static unsigned long board3;
119 static unsigned long board4;
120 static unsigned long controller;
121 static int support_low_speed;
122 static unsigned long modem1;
123 static unsigned long modem2;
124 static unsigned long modem3;
125 static unsigned long modem4;
126 static unsigned long pc104_1[8];
127 static unsigned long pc104_2[8];
128 static unsigned long pc104_3[8];
129 static unsigned long pc104_4[8];
130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
132 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
134 static int rcktpt_type[NUM_BOARDS];
135 static int is_PCI[NUM_BOARDS];
136 static rocketModel_t rocketModel[NUM_BOARDS];
137 static int max_board;
138 static const struct tty_port_operations rocket_port_ops;
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
153 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
154 UPCI_AIOP_INTR_BIT_0,
155 UPCI_AIOP_INTR_BIT_1,
156 UPCI_AIOP_INTR_BIT_2,
160 static Byte_t RData[RDATASIZE] = {
161 0x00, 0x09, 0xf6, 0x82,
162 0x02, 0x09, 0x86, 0xfb,
163 0x04, 0x09, 0x00, 0x0a,
164 0x06, 0x09, 0x01, 0x0a,
165 0x08, 0x09, 0x8a, 0x13,
166 0x0a, 0x09, 0xc5, 0x11,
167 0x0c, 0x09, 0x86, 0x85,
168 0x0e, 0x09, 0x20, 0x0a,
169 0x10, 0x09, 0x21, 0x0a,
170 0x12, 0x09, 0x41, 0xff,
171 0x14, 0x09, 0x82, 0x00,
172 0x16, 0x09, 0x82, 0x7b,
173 0x18, 0x09, 0x8a, 0x7d,
174 0x1a, 0x09, 0x88, 0x81,
175 0x1c, 0x09, 0x86, 0x7a,
176 0x1e, 0x09, 0x84, 0x81,
177 0x20, 0x09, 0x82, 0x7c,
178 0x22, 0x09, 0x0a, 0x0a
181 static Byte_t RRegData[RREGDATASIZE] = {
182 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
183 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
184 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
185 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
186 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
187 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
188 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
189 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
190 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
191 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
192 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
193 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
194 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
197 static CONTROLLER_T sController[CTL_SIZE] = {
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208 static Byte_t sBitMapClrTbl[8] = {
209 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212 static Byte_t sBitMapSetTbl[8] = {
213 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216 static int sClockPrescale = 0x14;
219 * Line number is the ttySIx number (x), the Minor number. We
220 * assign them sequentially, starting at zero. The following
221 * array keeps track of the line number assigned to a given board/aiop/channel.
223 static unsigned char lineNumbers[MAX_RP_PORTS];
224 static unsigned long nextLineNumber;
226 /***** RocketPort Static Prototypes *********/
227 static int __init init_ISA(int i);
228 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
229 static void rp_flush_buffer(struct tty_struct *tty);
230 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
231 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
232 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
233 static void rp_start(struct tty_struct *tty);
234 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
237 static void sFlushRxFIFO(CHANNEL_T * ChP);
238 static void sFlushTxFIFO(CHANNEL_T * ChP);
239 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
240 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
241 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
242 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
243 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
244 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
245 ByteIO_t * AiopIOList, int AiopIOListSize,
246 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
247 int PeriodicOnly, int altChanRingIndicator,
249 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
250 ByteIO_t * AiopIOList, int AiopIOListSize,
251 int IRQNum, Byte_t Frequency, int PeriodicOnly);
252 static int sReadAiopID(ByteIO_t io);
253 static int sReadAiopNumChan(WordIO_t io);
255 MODULE_AUTHOR("Theodore Ts'o");
256 MODULE_DESCRIPTION("Comtrol RocketPort driver");
257 module_param(board1, ulong, 0);
258 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
259 module_param(board2, ulong, 0);
260 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
261 module_param(board3, ulong, 0);
262 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
263 module_param(board4, ulong, 0);
264 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
265 module_param(controller, ulong, 0);
266 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
267 module_param(support_low_speed, bool, 0);
268 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
269 module_param(modem1, ulong, 0);
270 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
271 module_param(modem2, ulong, 0);
272 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
273 module_param(modem3, ulong, 0);
274 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
275 module_param(modem4, ulong, 0);
276 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
277 module_param_array(pc104_1, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
279 module_param_array(pc104_2, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
281 module_param_array(pc104_3, ulong, NULL, 0);
282 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
283 module_param_array(pc104_4, ulong, NULL, 0);
284 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
286 static int rp_init(void);
287 static void rp_cleanup_module(void);
289 module_init(rp_init);
290 module_exit(rp_cleanup_module);
293 MODULE_LICENSE("Dual BSD/GPL");
295 /*************************************************************************/
296 /* Module code starts here */
298 static inline int rocket_paranoia_check(struct r_port *info,
301 #ifdef ROCKET_PARANOIA_CHECK
304 if (info->magic != RPORT_MAGIC) {
305 printk(KERN_WARNING "Warning: bad magic number for rocketport "
306 "struct in %s\n", routine);
314 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
315 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
318 static void rp_do_receive(struct r_port *info,
319 struct tty_struct *tty,
320 CHANNEL_t * cp, unsigned int ChanStatus)
322 unsigned int CharNStat;
323 int ToRecv, wRecv, space;
326 ToRecv = sGetRxCnt(cp);
327 #ifdef ROCKET_DEBUG_INTR
328 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
334 * if status indicates there are errored characters in the
335 * FIFO, then enter status mode (a word in FIFO holds
336 * character and status).
338 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
339 if (!(ChanStatus & STATMODE)) {
340 #ifdef ROCKET_DEBUG_RECEIVE
341 printk(KERN_INFO "Entering STATMODE...\n");
343 ChanStatus |= STATMODE;
349 * if we previously entered status mode, then read down the
350 * FIFO one word at a time, pulling apart the character and
351 * the status. Update error counters depending on status
353 if (ChanStatus & STATMODE) {
354 #ifdef ROCKET_DEBUG_RECEIVE
355 printk(KERN_INFO "Ignore %x, read %x...\n",
356 info->ignore_status_mask, info->read_status_mask);
361 CharNStat = sInW(sGetTxRxDataIO(cp));
362 #ifdef ROCKET_DEBUG_RECEIVE
363 printk(KERN_INFO "%x...\n", CharNStat);
365 if (CharNStat & STMBREAKH)
366 CharNStat &= ~(STMFRAMEH | STMPARITYH);
367 if (CharNStat & info->ignore_status_mask) {
371 CharNStat &= info->read_status_mask;
372 if (CharNStat & STMBREAKH)
374 else if (CharNStat & STMPARITYH)
376 else if (CharNStat & STMFRAMEH)
378 else if (CharNStat & STMRCVROVRH)
382 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
387 * after we've emptied the FIFO in status mode, turn
388 * status mode back off
390 if (sGetRxCnt(cp) == 0) {
391 #ifdef ROCKET_DEBUG_RECEIVE
392 printk(KERN_INFO "Status mode off.\n");
394 sDisRxStatusMode(cp);
398 * we aren't in status mode, so read down the FIFO two
399 * characters at time by doing repeated word IO
402 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
403 if (space < ToRecv) {
404 #ifdef ROCKET_DEBUG_RECEIVE
405 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
413 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
415 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
417 /* Push the data up to the tty layer */
418 tty_flip_buffer_push(tty);
422 * Serial port transmit data function. Called from the timer polling loop as a
423 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
424 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
425 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
427 static void rp_do_transmit(struct r_port *info)
430 CHANNEL_t *cp = &info->channel;
431 struct tty_struct *tty;
434 #ifdef ROCKET_DEBUG_INTR
435 printk(KERN_DEBUG "%s\n", __func__);
439 tty = tty_port_tty_get(&info->port);
442 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
443 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
447 spin_lock_irqsave(&info->slock, flags);
448 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
450 /* Loop sending data to FIFO until done or FIFO full */
452 if (tty->stopped || tty->hw_stopped)
454 c = min(info->xmit_fifo_room, info->xmit_cnt);
455 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
456 if (c <= 0 || info->xmit_fifo_room <= 0)
458 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
460 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
461 info->xmit_tail += c;
462 info->xmit_tail &= XMIT_BUF_SIZE - 1;
464 info->xmit_fifo_room -= c;
465 #ifdef ROCKET_DEBUG_INTR
466 printk(KERN_INFO "tx %d chars...\n", c);
470 if (info->xmit_cnt == 0)
471 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
473 if (info->xmit_cnt < WAKEUP_CHARS) {
475 #ifdef ROCKETPORT_HAVE_POLL_WAIT
476 wake_up_interruptible(&tty->poll_wait);
480 spin_unlock_irqrestore(&info->slock, flags);
483 #ifdef ROCKET_DEBUG_INTR
484 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
485 info->xmit_tail, info->xmit_fifo_room);
490 * Called when a serial port signals it has read data in it's RX FIFO.
491 * It checks what interrupts are pending and services them, including
492 * receiving serial data.
494 static void rp_handle_port(struct r_port *info)
497 struct tty_struct *tty;
498 unsigned int IntMask, ChanStatus;
503 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
504 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
505 "info->flags & NOT_INIT\n");
508 tty = tty_port_tty_get(&info->port);
510 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
516 IntMask = sGetChanIntID(cp) & info->intmask;
517 #ifdef ROCKET_DEBUG_INTR
518 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
520 ChanStatus = sGetChanStatus(cp);
521 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
522 rp_do_receive(info, tty, cp, ChanStatus);
524 if (IntMask & DELTA_CD) { /* CD change */
525 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
526 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
527 (ChanStatus & CD_ACT) ? "on" : "off");
529 if (!(ChanStatus & CD_ACT) && info->cd_status) {
530 #ifdef ROCKET_DEBUG_HANGUP
531 printk(KERN_INFO "CD drop, calling hangup.\n");
535 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
536 wake_up_interruptible(&info->port.open_wait);
538 #ifdef ROCKET_DEBUG_INTR
539 if (IntMask & DELTA_CTS) { /* CTS change */
540 printk(KERN_INFO "CTS change...\n");
542 if (IntMask & DELTA_DSR) { /* DSR change */
543 printk(KERN_INFO "DSR change...\n");
550 * The top level polling routine. Repeats every 1/100 HZ (10ms).
552 static void rp_do_poll(unsigned long dummy)
555 int ctrl, aiop, ch, line;
556 unsigned int xmitmask, i;
557 unsigned int CtlMask;
558 unsigned char AiopMask;
561 /* Walk through all the boards (ctrl's) */
562 for (ctrl = 0; ctrl < max_board; ctrl++) {
563 if (rcktpt_io_addr[ctrl] <= 0)
566 /* Get a ptr to the board's control struct */
567 ctlp = sCtlNumToCtlPtr(ctrl);
569 /* Get the interrupt status from the board */
571 if (ctlp->BusType == isPCI)
572 CtlMask = sPCIGetControllerIntStatus(ctlp);
575 CtlMask = sGetControllerIntStatus(ctlp);
577 /* Check if any AIOP read bits are set */
578 for (aiop = 0; CtlMask; aiop++) {
579 bit = ctlp->AiopIntrBits[aiop];
582 AiopMask = sGetAiopIntStatus(ctlp, aiop);
584 /* Check if any port read bits are set */
585 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
588 /* Get the line number (/dev/ttyRx number). */
589 /* Read the data from the port. */
590 line = GetLineNumber(ctrl, aiop, ch);
591 rp_handle_port(rp_table[line]);
597 xmitmask = xmit_flags[ctrl];
600 * xmit_flags contains bit-significant flags, indicating there is data
601 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
602 * 1, ... (32 total possible). The variable i has the aiop and ch
603 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
606 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
607 if (xmitmask & (1 << i)) {
608 aiop = (i & 0x18) >> 3;
610 line = GetLineNumber(ctrl, aiop, ch);
611 rp_do_transmit(rp_table[line]);
618 * Reset the timer so we get called at the next clock tick (10ms).
620 if (atomic_read(&rp_num_ports_open))
621 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
625 * Initializes the r_port structure for a port, as well as enabling the port on
627 * Inputs: board, aiop, chan numbers
629 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
636 /* Get the next available line number */
637 line = SetLineNumber(board, aiop, chan);
639 ctlp = sCtlNumToCtlPtr(board);
641 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
642 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
644 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
649 info->magic = RPORT_MAGIC;
655 tty_port_init(&info->port);
656 info->port.ops = &rocket_port_ops;
657 init_completion(&info->close_wait);
658 info->flags &= ~ROCKET_MODE_MASK;
659 switch (pc104[board][line]) {
661 info->flags |= ROCKET_MODE_RS422;
664 info->flags |= ROCKET_MODE_RS485;
668 info->flags |= ROCKET_MODE_RS232;
672 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
673 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
674 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
680 rocketMode = info->flags & ROCKET_MODE_MASK;
682 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
683 sEnRTSToggle(&info->channel);
685 sDisRTSToggle(&info->channel);
687 if (ctlp->boardType == ROCKET_TYPE_PC104) {
688 switch (rocketMode) {
689 case ROCKET_MODE_RS485:
690 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
692 case ROCKET_MODE_RS422:
693 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
695 case ROCKET_MODE_RS232:
697 if (info->flags & ROCKET_RTS_TOGGLE)
698 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
700 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
704 spin_lock_init(&info->slock);
705 mutex_init(&info->write_mtx);
706 rp_table[line] = info;
707 tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
712 * Configures a rocketport port according to its termio settings. Called from
713 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
715 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
716 struct ktermios *old_termios)
721 int bits, baud, divisor;
723 struct ktermios *t = tty->termios;
728 /* Byte size and parity */
729 if ((cflag & CSIZE) == CS8) {
736 if (cflag & CSTOPB) {
743 if (cflag & PARENB) {
746 if (cflag & PARODD) {
756 baud = tty_get_baud_rate(tty);
759 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
760 if ((divisor >= 8192 || divisor < 0) && old_termios) {
761 baud = tty_termios_baud_rate(old_termios);
764 divisor = (rp_baud_base[info->board] / baud) - 1;
766 if (divisor >= 8192 || divisor < 0) {
768 divisor = (rp_baud_base[info->board] / baud) - 1;
770 info->cps = baud / bits;
771 sSetBaud(cp, divisor);
773 /* FIXME: Should really back compute a baud rate from the divisor */
774 tty_encode_baud_rate(tty, baud, baud);
776 if (cflag & CRTSCTS) {
777 info->intmask |= DELTA_CTS;
780 info->intmask &= ~DELTA_CTS;
783 if (cflag & CLOCAL) {
784 info->intmask &= ~DELTA_CD;
786 spin_lock_irqsave(&info->slock, flags);
787 if (sGetChanStatus(cp) & CD_ACT)
791 info->intmask |= DELTA_CD;
792 spin_unlock_irqrestore(&info->slock, flags);
796 * Handle software flow control in the board
798 #ifdef ROCKET_SOFT_FLOW
800 sEnTxSoftFlowCtl(cp);
806 sSetTxXONChar(cp, START_CHAR(tty));
807 sSetTxXOFFChar(cp, STOP_CHAR(tty));
809 sDisTxSoftFlowCtl(cp);
816 * Set up ignore/read mask words
818 info->read_status_mask = STMRCVROVRH | 0xFF;
820 info->read_status_mask |= STMFRAMEH | STMPARITYH;
821 if (I_BRKINT(tty) || I_PARMRK(tty))
822 info->read_status_mask |= STMBREAKH;
825 * Characters to ignore
827 info->ignore_status_mask = 0;
829 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
831 info->ignore_status_mask |= STMBREAKH;
833 * If we're ignoring parity and break indicators,
834 * ignore overruns too. (For real raw support).
837 info->ignore_status_mask |= STMRCVROVRH;
840 rocketMode = info->flags & ROCKET_MODE_MASK;
842 if ((info->flags & ROCKET_RTS_TOGGLE)
843 || (rocketMode == ROCKET_MODE_RS485))
848 sSetRTS(&info->channel);
850 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
851 switch (rocketMode) {
852 case ROCKET_MODE_RS485:
853 sSetInterfaceMode(cp, InterfaceModeRS485);
855 case ROCKET_MODE_RS422:
856 sSetInterfaceMode(cp, InterfaceModeRS422);
858 case ROCKET_MODE_RS232:
860 if (info->flags & ROCKET_RTS_TOGGLE)
861 sSetInterfaceMode(cp, InterfaceModeRS232T);
863 sSetInterfaceMode(cp, InterfaceModeRS232);
869 static int carrier_raised(struct tty_port *port)
871 struct r_port *info = container_of(port, struct r_port, port);
872 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
875 static void raise_dtr_rts(struct tty_port *port)
877 struct r_port *info = container_of(port, struct r_port, port);
878 sSetDTR(&info->channel);
879 sSetRTS(&info->channel);
882 /* info->port.count is considered critical, protected by spinlocks. */
883 static int block_til_ready(struct tty_struct *tty, struct file *filp,
886 DECLARE_WAITQUEUE(wait, current);
887 struct tty_port *port = &info->port;
889 int do_clocal = 0, extra_count = 0;
893 * If the device is in the middle of being closed, then block
894 * until it's done, and then try again.
896 if (tty_hung_up_p(filp))
897 return ((info->port.flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
898 if (info->flags & ASYNC_CLOSING) {
899 if (wait_for_completion_interruptible(&info->close_wait))
901 return ((info->port.flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
905 * If non-blocking mode is set, or the port is not enabled,
906 * then make the check up front and then exit.
908 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
909 info->port.flags |= ASYNC_NORMAL_ACTIVE;
912 if (tty->termios->c_cflag & CLOCAL)
916 * Block waiting for the carrier detect and the line to become free. While we are in
917 * this loop, port->count is dropped by one, so that rp_close() knows when to free things.
918 * We restore it upon exit, either normal or abnormal.
921 add_wait_queue(&port->open_wait, &wait);
922 #ifdef ROCKET_DEBUG_OPEN
923 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, port->count);
925 spin_lock_irqsave(&port->lock, flags);
927 #ifdef ROCKET_DISABLE_SIMUSAGE
928 info->port.flags |= ASYNC_NORMAL_ACTIVE;
930 if (!tty_hung_up_p(filp)) {
935 port->blocked_open++;
937 spin_unlock_irqrestore(&port->lock, flags);
940 if (tty->termios->c_cflag & CBAUD)
941 tty_port_raise_dtr_rts(port);
942 set_current_state(TASK_INTERRUPTIBLE);
943 if (tty_hung_up_p(filp) || !(info->port.flags & ASYNC_INITIALIZED)) {
944 if (info->port.flags & ASYNC_HUP_NOTIFY)
947 retval = -ERESTARTSYS;
950 if (!(info->port.flags & ASYNC_CLOSING) &&
951 (do_clocal || tty_port_carrier_raised(port)))
953 if (signal_pending(current)) {
954 retval = -ERESTARTSYS;
957 #ifdef ROCKET_DEBUG_OPEN
958 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
959 info->line, port->count, info->port.flags);
961 schedule(); /* Don't hold spinlock here, will hang PC */
963 __set_current_state(TASK_RUNNING);
964 remove_wait_queue(&port->open_wait, &wait);
966 spin_lock_irqsave(&port->lock, flags);
970 port->blocked_open--;
972 spin_unlock_irqrestore(&port->lock, flags);
974 #ifdef ROCKET_DEBUG_OPEN
975 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
976 info->line, port->count);
980 info->port.flags |= ASYNC_NORMAL_ACTIVE;
985 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
986 * port's r_port struct. Initializes the port hardware.
988 static int rp_open(struct tty_struct *tty, struct file *filp)
991 int line = 0, retval;
996 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
999 page = __get_free_page(GFP_KERNEL);
1003 if (info->port.flags & ASYNC_CLOSING) {
1004 retval = wait_for_completion_interruptible(&info->close_wait);
1008 return ((info->port.flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
1012 * We must not sleep from here until the port is marked fully in use.
1017 info->xmit_buf = (unsigned char *) page;
1019 tty->driver_data = info;
1020 tty_port_tty_set(&info->port, tty);
1022 if (info->port.count++ == 0) {
1023 atomic_inc(&rp_num_ports_open);
1025 #ifdef ROCKET_DEBUG_OPEN
1026 printk(KERN_INFO "rocket mod++ = %d...\n",
1027 atomic_read(&rp_num_ports_open));
1030 #ifdef ROCKET_DEBUG_OPEN
1031 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
1035 * Info->count is now 1; so it's safe to sleep now.
1037 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
1038 cp = &info->channel;
1039 sSetRxTrigger(cp, TRIG_1);
1040 if (sGetChanStatus(cp) & CD_ACT)
1041 info->cd_status = 1;
1043 info->cd_status = 0;
1044 sDisRxStatusMode(cp);
1048 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1049 sSetRxTrigger(cp, TRIG_1);
1052 sDisRxStatusMode(cp);
1056 sDisTxSoftFlowCtl(cp);
1061 info->port.flags |= ASYNC_INITIALIZED;
1064 * Set up the tty->alt_speed kludge
1066 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1067 tty->alt_speed = 57600;
1068 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1069 tty->alt_speed = 115200;
1070 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1071 tty->alt_speed = 230400;
1072 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1073 tty->alt_speed = 460800;
1075 configure_r_port(tty, info, NULL);
1076 if (tty->termios->c_cflag & CBAUD) {
1081 /* Starts (or resets) the maint polling loop */
1082 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1084 retval = block_til_ready(tty, filp, info);
1086 #ifdef ROCKET_DEBUG_OPEN
1087 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1095 * Exception handler that closes a serial port. info->port.count is considered critical.
1097 static void rp_close(struct tty_struct *tty, struct file *filp)
1099 struct r_port *info = tty->driver_data;
1100 struct tty_port *port = &info->port;
1101 unsigned long flags;
1105 if (rocket_paranoia_check(info, "rp_close"))
1108 #ifdef ROCKET_DEBUG_OPEN
1109 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1112 if (tty_hung_up_p(filp))
1114 spin_lock_irqsave(&port->lock, flags);
1116 if (tty->count == 1 && port->count != 1) {
1118 * Uh, oh. tty->count is 1, which means that the tty
1119 * structure will be freed. Info->count should always
1120 * be one in these conditions. If it's greater than
1121 * one, we've got real problems, since it means the
1122 * serial port won't be shutdown.
1124 printk(KERN_WARNING "rp_close: bad serial port count; "
1125 "tty->count is 1, info->port.count is %d\n", info->port.count);
1128 if (--port->count < 0) {
1129 printk(KERN_WARNING "rp_close: bad serial port count for "
1130 "ttyR%d: %d\n", info->line, info->port.count);
1134 spin_unlock_irqrestore(&port->lock, flags);
1137 info->port.flags |= ASYNC_CLOSING;
1138 spin_unlock_irqrestore(&port->lock, flags);
1140 cp = &info->channel;
1143 * Notify the line discpline to only process XON/XOFF characters
1148 * If transmission was throttled by the application request,
1149 * just flush the xmit buffer.
1151 if (tty->flow_stopped)
1152 rp_flush_buffer(tty);
1155 * Wait for the transmit buffer to clear
1157 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE)
1158 tty_wait_until_sent(tty, port->closing_wait);
1160 * Before we drop DTR, make sure the UART transmitter
1161 * has completely drained; this is especially
1162 * important if there is a transmit FIFO!
1164 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1167 rp_wait_until_sent(tty, timeout);
1168 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1171 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1173 sDisTxSoftFlowCtl(cp);
1181 rp_flush_buffer(tty);
1183 tty_ldisc_flush(tty);
1185 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1187 if (port->blocked_open) {
1188 if (port->close_delay) {
1189 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1191 wake_up_interruptible(&port->open_wait);
1193 if (info->xmit_buf) {
1194 free_page((unsigned long) info->xmit_buf);
1195 info->xmit_buf = NULL;
1198 info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1200 complete_all(&info->close_wait);
1201 atomic_dec(&rp_num_ports_open);
1203 #ifdef ROCKET_DEBUG_OPEN
1204 printk(KERN_INFO "rocket mod-- = %d...\n",
1205 atomic_read(&rp_num_ports_open));
1206 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1211 static void rp_set_termios(struct tty_struct *tty,
1212 struct ktermios *old_termios)
1214 struct r_port *info = tty->driver_data;
1218 if (rocket_paranoia_check(info, "rp_set_termios"))
1221 cflag = tty->termios->c_cflag;
1224 * This driver doesn't support CS5 or CS6
1226 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1227 tty->termios->c_cflag =
1228 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1230 tty->termios->c_cflag &= ~CMSPAR;
1232 configure_r_port(tty, info, old_termios);
1234 cp = &info->channel;
1236 /* Handle transition to B0 status */
1237 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1242 /* Handle transition away from B0 status */
1243 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1244 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1249 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1250 tty->hw_stopped = 0;
1255 static int rp_break(struct tty_struct *tty, int break_state)
1257 struct r_port *info = tty->driver_data;
1258 unsigned long flags;
1260 if (rocket_paranoia_check(info, "rp_break"))
1263 spin_lock_irqsave(&info->slock, flags);
1264 if (break_state == -1)
1265 sSendBreak(&info->channel);
1267 sClrBreak(&info->channel);
1268 spin_unlock_irqrestore(&info->slock, flags);
1273 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1274 * the UPCI boards was added, it was decided to make this a function because
1275 * the macro was getting too complicated. All cases except the first one
1276 * (UPCIRingInd) are taken directly from the original macro.
1278 static int sGetChanRI(CHANNEL_T * ChP)
1280 CONTROLLER_t *CtlP = ChP->CtlP;
1281 int ChanNum = ChP->ChanNum;
1284 if (CtlP->UPCIRingInd)
1285 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1286 else if (CtlP->AltChanRingIndicator)
1287 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1288 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1289 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1294 /********************************************************************************************/
1295 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1298 * Returns the state of the serial modem control lines. These next 2 functions
1299 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1301 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1303 struct r_port *info = tty->driver_data;
1304 unsigned int control, result, ChanStatus;
1306 ChanStatus = sGetChanStatusLo(&info->channel);
1307 control = info->channel.TxControl[3];
1308 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1309 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1310 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1311 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1312 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1313 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1319 * Sets the modem control lines
1321 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1322 unsigned int set, unsigned int clear)
1324 struct r_port *info = tty->driver_data;
1326 if (set & TIOCM_RTS)
1327 info->channel.TxControl[3] |= SET_RTS;
1328 if (set & TIOCM_DTR)
1329 info->channel.TxControl[3] |= SET_DTR;
1330 if (clear & TIOCM_RTS)
1331 info->channel.TxControl[3] &= ~SET_RTS;
1332 if (clear & TIOCM_DTR)
1333 info->channel.TxControl[3] &= ~SET_DTR;
1335 out32(info->channel.IndexAddr, info->channel.TxControl);
1339 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1341 struct rocket_config tmp;
1345 memset(&tmp, 0, sizeof (tmp));
1346 tmp.line = info->line;
1347 tmp.flags = info->flags;
1348 tmp.close_delay = info->port.close_delay;
1349 tmp.closing_wait = info->port.closing_wait;
1350 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1352 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1357 static int set_config(struct tty_struct *tty, struct r_port *info,
1358 struct rocket_config __user *new_info)
1360 struct rocket_config new_serial;
1362 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1365 if (!capable(CAP_SYS_ADMIN))
1367 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1369 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1370 configure_r_port(tty, info, NULL);
1374 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1375 info->port.close_delay = new_serial.close_delay;
1376 info->port.closing_wait = new_serial.closing_wait;
1378 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1379 tty->alt_speed = 57600;
1380 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1381 tty->alt_speed = 115200;
1382 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1383 tty->alt_speed = 230400;
1384 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1385 tty->alt_speed = 460800;
1387 configure_r_port(tty, info, NULL);
1392 * This function fills in a rocket_ports struct with information
1393 * about what boards/ports are in the system. This info is passed
1394 * to user space. See setrocket.c where the info is used to create
1395 * the /dev/ttyRx ports.
1397 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1399 struct rocket_ports tmp;
1404 memset(&tmp, 0, sizeof (tmp));
1405 tmp.tty_major = rocket_driver->major;
1407 for (board = 0; board < 4; board++) {
1408 tmp.rocketModel[board].model = rocketModel[board].model;
1409 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1410 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1411 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1412 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1414 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1419 static int reset_rm2(struct r_port *info, void __user *arg)
1423 if (!capable(CAP_SYS_ADMIN))
1426 if (copy_from_user(&reset, arg, sizeof (int)))
1431 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1432 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1435 if (info->ctlp->BusType == isISA)
1436 sModemReset(info->ctlp, info->chan, reset);
1438 sPCIModemReset(info->ctlp, info->chan, reset);
1443 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1445 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1450 /* IOCTL call handler into the driver */
1451 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1452 unsigned int cmd, unsigned long arg)
1454 struct r_port *info = tty->driver_data;
1455 void __user *argp = (void __user *)arg;
1458 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1464 case RCKP_GET_STRUCT:
1465 if (copy_to_user(argp, info, sizeof (struct r_port)))
1468 case RCKP_GET_CONFIG:
1469 ret = get_config(info, argp);
1471 case RCKP_SET_CONFIG:
1472 ret = set_config(tty, info, argp);
1474 case RCKP_GET_PORTS:
1475 ret = get_ports(info, argp);
1477 case RCKP_RESET_RM2:
1478 ret = reset_rm2(info, argp);
1480 case RCKP_GET_VERSION:
1481 ret = get_version(info, argp);
1490 static void rp_send_xchar(struct tty_struct *tty, char ch)
1492 struct r_port *info = tty->driver_data;
1495 if (rocket_paranoia_check(info, "rp_send_xchar"))
1498 cp = &info->channel;
1500 sWriteTxPrioByte(cp, ch);
1502 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1505 static void rp_throttle(struct tty_struct *tty)
1507 struct r_port *info = tty->driver_data;
1510 #ifdef ROCKET_DEBUG_THROTTLE
1511 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1512 tty->ldisc.chars_in_buffer(tty));
1515 if (rocket_paranoia_check(info, "rp_throttle"))
1518 cp = &info->channel;
1520 rp_send_xchar(tty, STOP_CHAR(tty));
1522 sClrRTS(&info->channel);
1525 static void rp_unthrottle(struct tty_struct *tty)
1527 struct r_port *info = tty->driver_data;
1529 #ifdef ROCKET_DEBUG_THROTTLE
1530 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1531 tty->ldisc.chars_in_buffer(tty));
1534 if (rocket_paranoia_check(info, "rp_throttle"))
1537 cp = &info->channel;
1539 rp_send_xchar(tty, START_CHAR(tty));
1541 sSetRTS(&info->channel);
1545 * ------------------------------------------------------------
1546 * rp_stop() and rp_start()
1548 * This routines are called before setting or resetting tty->stopped.
1549 * They enable or disable transmitter interrupts, as necessary.
1550 * ------------------------------------------------------------
1552 static void rp_stop(struct tty_struct *tty)
1554 struct r_port *info = tty->driver_data;
1556 #ifdef ROCKET_DEBUG_FLOW
1557 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1558 info->xmit_cnt, info->xmit_fifo_room);
1561 if (rocket_paranoia_check(info, "rp_stop"))
1564 if (sGetTxCnt(&info->channel))
1565 sDisTransmit(&info->channel);
1568 static void rp_start(struct tty_struct *tty)
1570 struct r_port *info = tty->driver_data;
1572 #ifdef ROCKET_DEBUG_FLOW
1573 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1574 info->xmit_cnt, info->xmit_fifo_room);
1577 if (rocket_paranoia_check(info, "rp_stop"))
1580 sEnTransmit(&info->channel);
1581 set_bit((info->aiop * 8) + info->chan,
1582 (void *) &xmit_flags[info->board]);
1586 * rp_wait_until_sent() --- wait until the transmitter is empty
1588 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1590 struct r_port *info = tty->driver_data;
1592 unsigned long orig_jiffies;
1593 int check_time, exit_time;
1596 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1599 cp = &info->channel;
1601 orig_jiffies = jiffies;
1602 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1603 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1605 printk(KERN_INFO "cps=%d...\n", info->cps);
1609 txcnt = sGetTxCnt(cp);
1611 if (sGetChanStatusLo(cp) & TXSHRMT)
1613 check_time = (HZ / info->cps) / 5;
1615 check_time = HZ * txcnt / info->cps;
1618 exit_time = orig_jiffies + timeout - jiffies;
1621 if (exit_time < check_time)
1622 check_time = exit_time;
1624 if (check_time == 0)
1626 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1627 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1628 jiffies, check_time);
1630 msleep_interruptible(jiffies_to_msecs(check_time));
1631 if (signal_pending(current))
1634 __set_current_state(TASK_RUNNING);
1636 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1637 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1642 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1644 static void rp_hangup(struct tty_struct *tty)
1647 struct r_port *info = tty->driver_data;
1649 if (rocket_paranoia_check(info, "rp_hangup"))
1652 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1653 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1655 rp_flush_buffer(tty);
1656 if (info->port.flags & ASYNC_CLOSING)
1658 if (info->port.count)
1659 atomic_dec(&rp_num_ports_open);
1660 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1662 info->port.count = 0;
1663 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
1664 tty_port_tty_set(&info->port, NULL);
1666 cp = &info->channel;
1669 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1671 sDisTxSoftFlowCtl(cp);
1673 info->port.flags &= ~ASYNC_INITIALIZED;
1675 wake_up_interruptible(&info->port.open_wait);
1679 * Exception handler - write char routine. The RocketPort driver uses a
1680 * double-buffering strategy, with the twist that if the in-memory CPU
1681 * buffer is empty, and there's space in the transmit FIFO, the
1682 * writing routines will write directly to transmit FIFO.
1683 * Write buffer and counters protected by spinlocks
1685 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1687 struct r_port *info = tty->driver_data;
1689 unsigned long flags;
1691 if (rocket_paranoia_check(info, "rp_put_char"))
1695 * Grab the port write mutex, locking out other processes that try to
1696 * write to this port
1698 mutex_lock(&info->write_mtx);
1700 #ifdef ROCKET_DEBUG_WRITE
1701 printk(KERN_INFO "rp_put_char %c...\n", ch);
1704 spin_lock_irqsave(&info->slock, flags);
1705 cp = &info->channel;
1707 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1708 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1710 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1711 info->xmit_buf[info->xmit_head++] = ch;
1712 info->xmit_head &= XMIT_BUF_SIZE - 1;
1714 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1716 sOutB(sGetTxRxDataIO(cp), ch);
1717 info->xmit_fifo_room--;
1719 spin_unlock_irqrestore(&info->slock, flags);
1720 mutex_unlock(&info->write_mtx);
1725 * Exception handler - write routine, called when user app writes to the device.
1726 * A per port write mutex is used to protect from another process writing to
1727 * this port at the same time. This other process could be running on the other CPU
1728 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1729 * Spinlocks protect the info xmit members.
1731 static int rp_write(struct tty_struct *tty,
1732 const unsigned char *buf, int count)
1734 struct r_port *info = tty->driver_data;
1736 const unsigned char *b;
1738 unsigned long flags;
1740 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1743 if (mutex_lock_interruptible(&info->write_mtx))
1744 return -ERESTARTSYS;
1746 #ifdef ROCKET_DEBUG_WRITE
1747 printk(KERN_INFO "rp_write %d chars...\n", count);
1749 cp = &info->channel;
1751 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1752 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1755 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1756 * into FIFO. Use the write queue for temp storage.
1758 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1759 c = min(count, info->xmit_fifo_room);
1762 /* Push data into FIFO, 2 bytes at a time */
1763 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1765 /* If there is a byte remaining, write it */
1767 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1773 spin_lock_irqsave(&info->slock, flags);
1774 info->xmit_fifo_room -= c;
1775 spin_unlock_irqrestore(&info->slock, flags);
1778 /* If count is zero, we wrote it all and are done */
1782 /* Write remaining data into the port's xmit_buf */
1785 if (!test_bit(ASYNC_NORMAL_ACTIVE, &info->port.flags))
1787 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1788 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1793 memcpy(info->xmit_buf + info->xmit_head, b, c);
1795 spin_lock_irqsave(&info->slock, flags);
1797 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1798 info->xmit_cnt += c;
1799 spin_unlock_irqrestore(&info->slock, flags);
1806 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1807 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1810 if (info->xmit_cnt < WAKEUP_CHARS) {
1812 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1813 wake_up_interruptible(&tty->poll_wait);
1816 mutex_unlock(&info->write_mtx);
1821 * Return the number of characters that can be sent. We estimate
1822 * only using the in-memory transmit buffer only, and ignore the
1823 * potential space in the transmit FIFO.
1825 static int rp_write_room(struct tty_struct *tty)
1827 struct r_port *info = tty->driver_data;
1830 if (rocket_paranoia_check(info, "rp_write_room"))
1833 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1836 #ifdef ROCKET_DEBUG_WRITE
1837 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1843 * Return the number of characters in the buffer. Again, this only
1844 * counts those characters in the in-memory transmit buffer.
1846 static int rp_chars_in_buffer(struct tty_struct *tty)
1848 struct r_port *info = tty->driver_data;
1851 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1854 cp = &info->channel;
1856 #ifdef ROCKET_DEBUG_WRITE
1857 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1859 return info->xmit_cnt;
1863 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1864 * r_port struct for the port. Note that spinlock are used to protect info members,
1865 * do not call this function if the spinlock is already held.
1867 static void rp_flush_buffer(struct tty_struct *tty)
1869 struct r_port *info = tty->driver_data;
1871 unsigned long flags;
1873 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1876 spin_lock_irqsave(&info->slock, flags);
1877 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1878 spin_unlock_irqrestore(&info->slock, flags);
1880 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1881 wake_up_interruptible(&tty->poll_wait);
1885 cp = &info->channel;
1891 static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1892 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1895 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1898 * Called when a PCI card is found. Retrieves and stores model information,
1899 * init's aiopic and serial port hardware.
1900 * Inputs: i is the board number (0-n)
1902 static __init int register_PCI(int i, struct pci_dev *dev)
1904 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1905 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1906 char *str, *board_type;
1910 int altChanRingIndicator = 0;
1911 int ports_per_aiop = 8;
1912 WordIO_t ConfigIO = 0;
1913 ByteIO_t UPCIRingInd = 0;
1915 if (!dev || pci_enable_device(dev))
1918 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1920 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1921 rocketModel[i].loadrm2 = 0;
1922 rocketModel[i].startingPortNumber = nextLineNumber;
1924 /* Depending on the model, set up some config variables */
1925 switch (dev->device) {
1926 case PCI_DEVICE_ID_RP4QUAD:
1930 rocketModel[i].model = MODEL_RP4QUAD;
1931 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1932 rocketModel[i].numPorts = 4;
1934 case PCI_DEVICE_ID_RP8OCTA:
1937 rocketModel[i].model = MODEL_RP8OCTA;
1938 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1939 rocketModel[i].numPorts = 8;
1941 case PCI_DEVICE_ID_URP8OCTA:
1944 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1945 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1946 rocketModel[i].numPorts = 8;
1948 case PCI_DEVICE_ID_RP8INTF:
1951 rocketModel[i].model = MODEL_RP8INTF;
1952 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1953 rocketModel[i].numPorts = 8;
1955 case PCI_DEVICE_ID_URP8INTF:
1958 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1959 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1960 rocketModel[i].numPorts = 8;
1962 case PCI_DEVICE_ID_RP8J:
1965 rocketModel[i].model = MODEL_RP8J;
1966 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1967 rocketModel[i].numPorts = 8;
1969 case PCI_DEVICE_ID_RP4J:
1973 rocketModel[i].model = MODEL_RP4J;
1974 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1975 rocketModel[i].numPorts = 4;
1977 case PCI_DEVICE_ID_RP8SNI:
1978 str = "8 (DB78 Custom)";
1980 rocketModel[i].model = MODEL_RP8SNI;
1981 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1982 rocketModel[i].numPorts = 8;
1984 case PCI_DEVICE_ID_RP16SNI:
1985 str = "16 (DB78 Custom)";
1987 rocketModel[i].model = MODEL_RP16SNI;
1988 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1989 rocketModel[i].numPorts = 16;
1991 case PCI_DEVICE_ID_RP16INTF:
1994 rocketModel[i].model = MODEL_RP16INTF;
1995 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1996 rocketModel[i].numPorts = 16;
1998 case PCI_DEVICE_ID_URP16INTF:
2001 rocketModel[i].model = MODEL_UPCI_RP16INTF;
2002 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
2003 rocketModel[i].numPorts = 16;
2005 case PCI_DEVICE_ID_CRP16INTF:
2008 rocketModel[i].model = MODEL_CPCI_RP16INTF;
2009 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
2010 rocketModel[i].numPorts = 16;
2012 case PCI_DEVICE_ID_RP32INTF:
2015 rocketModel[i].model = MODEL_RP32INTF;
2016 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
2017 rocketModel[i].numPorts = 32;
2019 case PCI_DEVICE_ID_URP32INTF:
2022 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2023 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2024 rocketModel[i].numPorts = 32;
2026 case PCI_DEVICE_ID_RPP4:
2027 str = "Plus Quadcable";
2030 altChanRingIndicator++;
2032 rocketModel[i].model = MODEL_RPP4;
2033 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2034 rocketModel[i].numPorts = 4;
2036 case PCI_DEVICE_ID_RPP8:
2037 str = "Plus Octacable";
2040 altChanRingIndicator++;
2042 rocketModel[i].model = MODEL_RPP8;
2043 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2044 rocketModel[i].numPorts = 8;
2046 case PCI_DEVICE_ID_RP2_232:
2047 str = "Plus 2 (RS-232)";
2050 altChanRingIndicator++;
2052 rocketModel[i].model = MODEL_RP2_232;
2053 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2054 rocketModel[i].numPorts = 2;
2056 case PCI_DEVICE_ID_RP2_422:
2057 str = "Plus 2 (RS-422)";
2060 altChanRingIndicator++;
2062 rocketModel[i].model = MODEL_RP2_422;
2063 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2064 rocketModel[i].numPorts = 2;
2066 case PCI_DEVICE_ID_RP6M:
2072 /* If revision is 1, the rocketmodem flash must be loaded.
2073 * If it is 2 it is a "socketed" version. */
2074 if (dev->revision == 1) {
2075 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2076 rocketModel[i].loadrm2 = 1;
2078 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2081 rocketModel[i].model = MODEL_RP6M;
2082 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2083 rocketModel[i].numPorts = 6;
2085 case PCI_DEVICE_ID_RP4M:
2089 if (dev->revision == 1) {
2090 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2091 rocketModel[i].loadrm2 = 1;
2093 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2096 rocketModel[i].model = MODEL_RP4M;
2097 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2098 rocketModel[i].numPorts = 4;
2101 str = "(unknown/unsupported)";
2107 * Check for UPCI boards.
2110 switch (dev->device) {
2111 case PCI_DEVICE_ID_URP32INTF:
2112 case PCI_DEVICE_ID_URP8INTF:
2113 case PCI_DEVICE_ID_URP16INTF:
2114 case PCI_DEVICE_ID_CRP16INTF:
2115 case PCI_DEVICE_ID_URP8OCTA:
2116 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2117 ConfigIO = pci_resource_start(dev, 1);
2118 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2119 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2122 * Check for octa or quad cable.
2125 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2126 PCI_GPIO_CTRL_8PORT)) {
2129 rocketModel[i].numPorts = 4;
2133 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2136 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2137 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2138 rocketModel[i].numPorts = 8;
2139 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2140 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2141 ConfigIO = pci_resource_start(dev, 1);
2142 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2144 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2147 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2148 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2149 rocketModel[i].numPorts = 4;
2150 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2151 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2152 ConfigIO = pci_resource_start(dev, 1);
2153 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2159 switch (rcktpt_type[i]) {
2160 case ROCKET_TYPE_MODEM:
2161 board_type = "RocketModem";
2163 case ROCKET_TYPE_MODEMII:
2164 board_type = "RocketModem II";
2166 case ROCKET_TYPE_MODEMIII:
2167 board_type = "RocketModem III";
2170 board_type = "RocketPort";
2175 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2176 rp_baud_base[i] = 921600;
2179 * If support_low_speed is set, use the slow clock
2180 * prescale, which supports 50 bps
2182 if (support_low_speed) {
2183 /* mod 9 (divide by 10) prescale */
2184 sClockPrescale = 0x19;
2185 rp_baud_base[i] = 230400;
2187 /* mod 4 (devide by 5) prescale */
2188 sClockPrescale = 0x14;
2189 rp_baud_base[i] = 460800;
2193 for (aiop = 0; aiop < max_num_aiops; aiop++)
2194 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2195 ctlp = sCtlNumToCtlPtr(i);
2196 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2197 for (aiop = 0; aiop < max_num_aiops; aiop++)
2198 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2200 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2201 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2202 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2203 rocketModel[i].startingPortNumber,
2204 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2206 if (num_aiops <= 0) {
2207 rcktpt_io_addr[i] = 0;
2212 /* Reset the AIOPIC, init the serial ports */
2213 for (aiop = 0; aiop < num_aiops; aiop++) {
2214 sResetAiopByNum(ctlp, aiop);
2215 num_chan = ports_per_aiop;
2216 for (chan = 0; chan < num_chan; chan++)
2217 init_r_port(i, aiop, chan, dev);
2220 /* Rocket modems must be reset */
2221 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2222 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2223 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2224 num_chan = ports_per_aiop;
2225 for (chan = 0; chan < num_chan; chan++)
2226 sPCIModemReset(ctlp, chan, 1);
2228 for (chan = 0; chan < num_chan; chan++)
2229 sPCIModemReset(ctlp, chan, 0);
2231 rmSpeakerReset(ctlp, rocketModel[i].model);
2237 * Probes for PCI cards, inits them if found
2238 * Input: board_found = number of ISA boards already found, or the
2239 * starting board number
2240 * Returns: Number of PCI boards found
2242 static int __init init_PCI(int boards_found)
2244 struct pci_dev *dev = NULL;
2247 /* Work through the PCI device list, pulling out ours */
2248 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2249 if (register_PCI(count + boards_found, dev))
2255 #endif /* CONFIG_PCI */
2258 * Probes for ISA cards
2259 * Input: i = the board number to look for
2260 * Returns: 1 if board found, 0 else
2262 static int __init init_ISA(int i)
2264 int num_aiops, num_chan = 0, total_num_chan = 0;
2266 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2270 /* If io_addr is zero, no board configured */
2271 if (rcktpt_io_addr[i] == 0)
2274 /* Reserve the IO region */
2275 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2276 printk(KERN_ERR "Unable to reserve IO region for configured "
2277 "ISA RocketPort at address 0x%lx, board not "
2278 "installed...\n", rcktpt_io_addr[i]);
2279 rcktpt_io_addr[i] = 0;
2283 ctlp = sCtlNumToCtlPtr(i);
2285 ctlp->boardType = rcktpt_type[i];
2287 switch (rcktpt_type[i]) {
2288 case ROCKET_TYPE_PC104:
2289 type_string = "(PC104)";
2291 case ROCKET_TYPE_MODEM:
2292 type_string = "(RocketModem)";
2294 case ROCKET_TYPE_MODEMII:
2295 type_string = "(RocketModem II)";
2303 * If support_low_speed is set, use the slow clock prescale,
2304 * which supports 50 bps
2306 if (support_low_speed) {
2307 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2308 rp_baud_base[i] = 230400;
2310 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2311 rp_baud_base[i] = 460800;
2314 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2315 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2317 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2319 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2320 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2321 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2324 /* If something went wrong initing the AIOP's release the ISA IO memory */
2325 if (num_aiops <= 0) {
2326 release_region(rcktpt_io_addr[i], 64);
2327 rcktpt_io_addr[i] = 0;
2331 rocketModel[i].startingPortNumber = nextLineNumber;
2333 for (aiop = 0; aiop < num_aiops; aiop++) {
2334 sResetAiopByNum(ctlp, aiop);
2335 sEnAiop(ctlp, aiop);
2336 num_chan = sGetAiopNumChan(ctlp, aiop);
2337 total_num_chan += num_chan;
2338 for (chan = 0; chan < num_chan; chan++)
2339 init_r_port(i, aiop, chan, NULL);
2342 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2343 num_chan = sGetAiopNumChan(ctlp, 0);
2344 total_num_chan = num_chan;
2345 for (chan = 0; chan < num_chan; chan++)
2346 sModemReset(ctlp, chan, 1);
2348 for (chan = 0; chan < num_chan; chan++)
2349 sModemReset(ctlp, chan, 0);
2351 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2353 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2355 rocketModel[i].numPorts = total_num_chan;
2356 rocketModel[i].model = MODEL_ISA;
2358 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2359 i, rcktpt_io_addr[i], num_aiops, type_string);
2361 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2362 rocketModel[i].modelString,
2363 rocketModel[i].startingPortNumber,
2364 rocketModel[i].startingPortNumber +
2365 rocketModel[i].numPorts - 1);
2370 static const struct tty_operations rocket_ops = {
2374 .put_char = rp_put_char,
2375 .write_room = rp_write_room,
2376 .chars_in_buffer = rp_chars_in_buffer,
2377 .flush_buffer = rp_flush_buffer,
2379 .throttle = rp_throttle,
2380 .unthrottle = rp_unthrottle,
2381 .set_termios = rp_set_termios,
2384 .hangup = rp_hangup,
2385 .break_ctl = rp_break,
2386 .send_xchar = rp_send_xchar,
2387 .wait_until_sent = rp_wait_until_sent,
2388 .tiocmget = rp_tiocmget,
2389 .tiocmset = rp_tiocmset,
2392 static const struct tty_port_operations rocket_port_ops = {
2393 .carrier_raised = carrier_raised,
2394 .raise_dtr_rts = raise_dtr_rts,
2398 * The module "startup" routine; it's run when the module is loaded.
2400 static int __init rp_init(void)
2402 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2404 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2405 ROCKET_VERSION, ROCKET_DATE);
2407 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2412 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2413 * zero, use the default controller IO address of board1 + 0x40.
2416 if (controller == 0)
2417 controller = board1 + 0x40;
2419 controller = 0; /* Used as a flag, meaning no ISA boards */
2422 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2423 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2424 printk(KERN_ERR "Unable to reserve IO region for first "
2425 "configured ISA RocketPort controller 0x%lx. "
2426 "Driver exiting\n", controller);
2431 /* Store ISA variable retrieved from command line or .conf file. */
2432 rcktpt_io_addr[0] = board1;
2433 rcktpt_io_addr[1] = board2;
2434 rcktpt_io_addr[2] = board3;
2435 rcktpt_io_addr[3] = board4;
2437 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2438 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2439 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2440 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2441 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2442 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2443 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2444 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2447 * Set up the tty driver structure and then register this
2448 * driver with the tty layer.
2451 rocket_driver->owner = THIS_MODULE;
2452 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2453 rocket_driver->name = "ttyR";
2454 rocket_driver->driver_name = "Comtrol RocketPort";
2455 rocket_driver->major = TTY_ROCKET_MAJOR;
2456 rocket_driver->minor_start = 0;
2457 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2458 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2459 rocket_driver->init_termios = tty_std_termios;
2460 rocket_driver->init_termios.c_cflag =
2461 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2462 rocket_driver->init_termios.c_ispeed = 9600;
2463 rocket_driver->init_termios.c_ospeed = 9600;
2464 #ifdef ROCKET_SOFT_FLOW
2465 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2467 tty_set_operations(rocket_driver, &rocket_ops);
2469 ret = tty_register_driver(rocket_driver);
2471 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2475 #ifdef ROCKET_DEBUG_OPEN
2476 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2480 * OK, let's probe each of the controllers looking for boards. Any boards found
2481 * will be initialized here.
2483 isa_boards_found = 0;
2484 pci_boards_found = 0;
2486 for (i = 0; i < NUM_BOARDS; i++) {
2492 if (isa_boards_found < NUM_BOARDS)
2493 pci_boards_found = init_PCI(isa_boards_found);
2496 max_board = pci_boards_found + isa_boards_found;
2498 if (max_board == 0) {
2499 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2506 tty_unregister_driver(rocket_driver);
2508 put_tty_driver(rocket_driver);
2514 static void rp_cleanup_module(void)
2519 del_timer_sync(&rocket_timer);
2521 retval = tty_unregister_driver(rocket_driver);
2523 printk(KERN_ERR "Error %d while trying to unregister "
2524 "rocketport driver\n", -retval);
2526 for (i = 0; i < MAX_RP_PORTS; i++)
2528 tty_unregister_device(rocket_driver, i);
2532 put_tty_driver(rocket_driver);
2534 for (i = 0; i < NUM_BOARDS; i++) {
2535 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2537 release_region(rcktpt_io_addr[i], 64);
2540 release_region(controller, 4);
2543 /***************************************************************************
2544 Function: sInitController
2545 Purpose: Initialization of controller global registers and controller
2547 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2548 IRQNum,Frequency,PeriodicOnly)
2549 CONTROLLER_T *CtlP; Ptr to controller structure
2550 int CtlNum; Controller number
2551 ByteIO_t MudbacIO; Mudbac base I/O address.
2552 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2553 This list must be in the order the AIOPs will be found on the
2554 controller. Once an AIOP in the list is not found, it is
2555 assumed that there are no more AIOPs on the controller.
2556 int AiopIOListSize; Number of addresses in AiopIOList
2557 int IRQNum; Interrupt Request number. Can be any of the following:
2558 0: Disable global interrupts
2567 Byte_t Frequency: A flag identifying the frequency
2568 of the periodic interrupt, can be any one of the following:
2569 FREQ_DIS - periodic interrupt disabled
2570 FREQ_137HZ - 137 Hertz
2571 FREQ_69HZ - 69 Hertz
2572 FREQ_34HZ - 34 Hertz
2573 FREQ_17HZ - 17 Hertz
2576 If IRQNum is set to 0 the Frequency parameter is
2577 overidden, it is forced to a value of FREQ_DIS.
2578 int PeriodicOnly: 1 if all interrupts except the periodic
2579 interrupt are to be blocked.
2580 0 is both the periodic interrupt and
2581 other channel interrupts are allowed.
2582 If IRQNum is set to 0 the PeriodicOnly parameter is
2583 overidden, it is forced to a value of 0.
2584 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2585 initialization failed.
2588 If periodic interrupts are to be disabled but AIOP interrupts
2589 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2591 If interrupts are to be completely disabled set IRQNum to 0.
2593 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2594 invalid combination.
2596 This function performs initialization of global interrupt modes,
2597 but it does not actually enable global interrupts. To enable
2598 and disable global interrupts use functions sEnGlobalInt() and
2599 sDisGlobalInt(). Enabling of global interrupts is normally not
2600 done until all other initializations are complete.
2602 Even if interrupts are globally enabled, they must also be
2603 individually enabled for each channel that is to generate
2606 Warnings: No range checking on any of the parameters is done.
2608 No context switches are allowed while executing this function.
2610 After this function all AIOPs on the controller are disabled,
2611 they can be enabled with sEnAiop().
2613 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2614 ByteIO_t * AiopIOList, int AiopIOListSize,
2615 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2621 CtlP->AiopIntrBits = aiop_intr_bits;
2622 CtlP->AltChanRingIndicator = 0;
2623 CtlP->CtlNum = CtlNum;
2624 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2625 CtlP->BusType = isISA;
2626 CtlP->MBaseIO = MudbacIO;
2627 CtlP->MReg1IO = MudbacIO + 1;
2628 CtlP->MReg2IO = MudbacIO + 2;
2629 CtlP->MReg3IO = MudbacIO + 3;
2631 CtlP->MReg2 = 0; /* interrupt disable */
2632 CtlP->MReg3 = 0; /* no periodic interrupts */
2634 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2635 CtlP->MReg2 = 0; /* interrupt disable */
2636 CtlP->MReg3 = 0; /* no periodic interrupts */
2638 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2639 CtlP->MReg3 = Frequency; /* set frequency */
2640 if (PeriodicOnly) { /* periodic interrupt only */
2641 CtlP->MReg3 |= PERIODIC_ONLY;
2645 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2646 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2647 sControllerEOI(CtlP); /* clear EOI if warm init */
2650 for (i = done = 0; i < AiopIOListSize; i++) {
2652 CtlP->AiopIO[i] = (WordIO_t) io;
2653 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2654 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2655 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2658 sEnAiop(CtlP, i); /* enable the AIOP */
2659 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2660 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2661 done = 1; /* done looking for AIOPs */
2663 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2664 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2665 sOutB(io + _INDX_DATA, sClockPrescale);
2666 CtlP->NumAiop++; /* bump count of AIOPs */
2668 sDisAiop(CtlP, i); /* disable AIOP */
2671 if (CtlP->NumAiop == 0)
2674 return (CtlP->NumAiop);
2677 /***************************************************************************
2678 Function: sPCIInitController
2679 Purpose: Initialization of controller global registers and controller
2681 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2682 IRQNum,Frequency,PeriodicOnly)
2683 CONTROLLER_T *CtlP; Ptr to controller structure
2684 int CtlNum; Controller number
2685 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2686 This list must be in the order the AIOPs will be found on the
2687 controller. Once an AIOP in the list is not found, it is
2688 assumed that there are no more AIOPs on the controller.
2689 int AiopIOListSize; Number of addresses in AiopIOList
2690 int IRQNum; Interrupt Request number. Can be any of the following:
2691 0: Disable global interrupts
2700 Byte_t Frequency: A flag identifying the frequency
2701 of the periodic interrupt, can be any one of the following:
2702 FREQ_DIS - periodic interrupt disabled
2703 FREQ_137HZ - 137 Hertz
2704 FREQ_69HZ - 69 Hertz
2705 FREQ_34HZ - 34 Hertz
2706 FREQ_17HZ - 17 Hertz
2709 If IRQNum is set to 0 the Frequency parameter is
2710 overidden, it is forced to a value of FREQ_DIS.
2711 int PeriodicOnly: 1 if all interrupts except the periodic
2712 interrupt are to be blocked.
2713 0 is both the periodic interrupt and
2714 other channel interrupts are allowed.
2715 If IRQNum is set to 0 the PeriodicOnly parameter is
2716 overidden, it is forced to a value of 0.
2717 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2718 initialization failed.
2721 If periodic interrupts are to be disabled but AIOP interrupts
2722 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2724 If interrupts are to be completely disabled set IRQNum to 0.
2726 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2727 invalid combination.
2729 This function performs initialization of global interrupt modes,
2730 but it does not actually enable global interrupts. To enable
2731 and disable global interrupts use functions sEnGlobalInt() and
2732 sDisGlobalInt(). Enabling of global interrupts is normally not
2733 done until all other initializations are complete.
2735 Even if interrupts are globally enabled, they must also be
2736 individually enabled for each channel that is to generate
2739 Warnings: No range checking on any of the parameters is done.
2741 No context switches are allowed while executing this function.
2743 After this function all AIOPs on the controller are disabled,
2744 they can be enabled with sEnAiop().
2746 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2747 ByteIO_t * AiopIOList, int AiopIOListSize,
2748 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2749 int PeriodicOnly, int altChanRingIndicator,
2755 CtlP->AltChanRingIndicator = altChanRingIndicator;
2756 CtlP->UPCIRingInd = UPCIRingInd;
2757 CtlP->CtlNum = CtlNum;
2758 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2759 CtlP->BusType = isPCI; /* controller release 1 */
2763 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2764 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2765 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2769 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2770 CtlP->AiopIntrBits = aiop_intr_bits;
2773 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2776 for (i = 0; i < AiopIOListSize; i++) {
2778 CtlP->AiopIO[i] = (WordIO_t) io;
2779 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2781 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2782 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2783 break; /* done looking for AIOPs */
2785 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2786 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2787 sOutB(io + _INDX_DATA, sClockPrescale);
2788 CtlP->NumAiop++; /* bump count of AIOPs */
2791 if (CtlP->NumAiop == 0)
2794 return (CtlP->NumAiop);
2797 /***************************************************************************
2798 Function: sReadAiopID
2799 Purpose: Read the AIOP idenfication number directly from an AIOP.
2800 Call: sReadAiopID(io)
2801 ByteIO_t io: AIOP base I/O address
2802 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2803 is replace by an identifying number.
2804 Flag AIOPID_NULL if no valid AIOP is found
2805 Warnings: No context switches are allowed while executing this function.
2808 static int sReadAiopID(ByteIO_t io)
2810 Byte_t AiopID; /* ID byte from AIOP */
2812 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2813 sOutB(io + _CMD_REG, 0x0);
2814 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2817 else /* AIOP does not exist */
2821 /***************************************************************************
2822 Function: sReadAiopNumChan
2823 Purpose: Read the number of channels available in an AIOP directly from
2825 Call: sReadAiopNumChan(io)
2826 WordIO_t io: AIOP base I/O address
2827 Return: int: The number of channels available
2828 Comments: The number of channels is determined by write/reads from identical
2829 offsets within the SRAM address spaces for channels 0 and 4.
2830 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2831 AIOP, otherwise it is an 8 channel.
2832 Warnings: No context switches are allowed while executing this function.
2834 static int sReadAiopNumChan(WordIO_t io)
2837 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2839 /* write to chan 0 SRAM */
2840 out32((DWordIO_t) io + _INDX_ADDR, R);
2841 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2842 x = sInW(io + _INDX_DATA);
2843 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2844 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2850 /***************************************************************************
2852 Purpose: Initialization of a channel and channel structure
2853 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2854 CONTROLLER_T *CtlP; Ptr to controller structure
2855 CHANNEL_T *ChP; Ptr to channel structure
2856 int AiopNum; AIOP number within controller
2857 int ChanNum; Channel number within AIOP
2858 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2859 number exceeds number of channels available in AIOP.
2860 Comments: This function must be called before a channel can be used.
2861 Warnings: No range checking on any of the parameters is done.
2863 No context switches are allowed while executing this function.
2865 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2876 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2877 return 0; /* exceeds num chans in AIOP */
2879 /* Channel, AIOP, and controller identifiers */
2881 ChP->ChanID = CtlP->AiopID[AiopNum];
2882 ChP->AiopNum = AiopNum;
2883 ChP->ChanNum = ChanNum;
2885 /* Global direct addresses */
2886 AiopIO = CtlP->AiopIO[AiopNum];
2887 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2888 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2889 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2890 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2891 ChP->IndexData = AiopIO + _INDX_DATA;
2893 /* Channel direct addresses */
2894 ChIOOff = AiopIO + ChP->ChanNum * 2;
2895 ChP->TxRxData = ChIOOff + _TD0;
2896 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2897 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2898 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2900 /* Initialize the channel from the RData array */
2901 for (i = 0; i < RDATASIZE; i += 4) {
2903 R[1] = RData[i + 1] + 0x10 * ChanNum;
2904 R[2] = RData[i + 2];
2905 R[3] = RData[i + 3];
2906 out32(ChP->IndexAddr, R);
2910 for (i = 0; i < RREGDATASIZE; i += 4) {
2911 ChR[i] = RRegData[i];
2912 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2913 ChR[i + 2] = RRegData[i + 2];
2914 ChR[i + 3] = RRegData[i + 3];
2917 /* Indexed registers */
2918 ChOff = (Word_t) ChanNum *0x1000;
2920 if (sClockPrescale == 0x14)
2925 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2926 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2927 ChP->BaudDiv[2] = (Byte_t) brd9600;
2928 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2929 out32(ChP->IndexAddr, ChP->BaudDiv);
2931 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2932 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2933 ChP->TxControl[2] = 0;
2934 ChP->TxControl[3] = 0;
2935 out32(ChP->IndexAddr, ChP->TxControl);
2937 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2938 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2939 ChP->RxControl[2] = 0;
2940 ChP->RxControl[3] = 0;
2941 out32(ChP->IndexAddr, ChP->RxControl);
2943 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2944 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2945 ChP->TxEnables[2] = 0;
2946 ChP->TxEnables[3] = 0;
2947 out32(ChP->IndexAddr, ChP->TxEnables);
2949 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2950 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2951 ChP->TxCompare[2] = 0;
2952 ChP->TxCompare[3] = 0;
2953 out32(ChP->IndexAddr, ChP->TxCompare);
2955 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2956 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2957 ChP->TxReplace1[2] = 0;
2958 ChP->TxReplace1[3] = 0;
2959 out32(ChP->IndexAddr, ChP->TxReplace1);
2961 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2962 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2963 ChP->TxReplace2[2] = 0;
2964 ChP->TxReplace2[3] = 0;
2965 out32(ChP->IndexAddr, ChP->TxReplace2);
2967 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2968 ChP->TxFIFO = ChOff + _TX_FIFO;
2970 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2971 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2972 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2973 sOutW(ChP->IndexData, 0);
2974 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2975 ChP->RxFIFO = ChOff + _RX_FIFO;
2977 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2978 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2979 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2980 sOutW(ChP->IndexData, 0);
2981 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2982 sOutW(ChP->IndexData, 0);
2983 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2984 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2985 sOutB(ChP->IndexData, 0);
2986 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2987 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2988 sOutB(ChP->IndexData, 0);
2989 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2990 sEnRxProcessor(ChP); /* start the Rx processor */
2995 /***************************************************************************
2996 Function: sStopRxProcessor
2997 Purpose: Stop the receive processor from processing a channel.
2998 Call: sStopRxProcessor(ChP)
2999 CHANNEL_T *ChP; Ptr to channel structure
3001 Comments: The receive processor can be started again with sStartRxProcessor().
3002 This function causes the receive processor to skip over the
3003 stopped channel. It does not stop it from processing other channels.
3005 Warnings: No context switches are allowed while executing this function.
3007 Do not leave the receive processor stopped for more than one
3010 After calling this function a delay of 4 uS is required to ensure
3011 that the receive processor is no longer processing this channel.
3013 static void sStopRxProcessor(CHANNEL_T * ChP)
3021 out32(ChP->IndexAddr, R);
3024 /***************************************************************************
3025 Function: sFlushRxFIFO
3026 Purpose: Flush the Rx FIFO
3027 Call: sFlushRxFIFO(ChP)
3028 CHANNEL_T *ChP; Ptr to channel structure
3030 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3031 while it is being flushed the receive processor is stopped
3032 and the transmitter is disabled. After these operations a
3033 4 uS delay is done before clearing the pointers to allow
3034 the receive processor to stop. These items are handled inside
3036 Warnings: No context switches are allowed while executing this function.
3038 static void sFlushRxFIFO(CHANNEL_T * ChP)
3041 Byte_t Ch; /* channel number within AIOP */
3042 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
3044 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3045 return; /* don't need to flush */
3048 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
3050 sDisRxFIFO(ChP); /* disable it */
3051 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3052 sInB(ChP->IntChan); /* depends on bus i/o timing */
3054 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3055 Ch = (Byte_t) sGetChanNum(ChP);
3056 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3057 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3058 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3059 sOutW(ChP->IndexData, 0);
3060 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3061 sOutW(ChP->IndexData, 0);
3063 sEnRxFIFO(ChP); /* enable Rx FIFO */
3066 /***************************************************************************
3067 Function: sFlushTxFIFO
3068 Purpose: Flush the Tx FIFO
3069 Call: sFlushTxFIFO(ChP)
3070 CHANNEL_T *ChP; Ptr to channel structure
3072 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3073 while it is being flushed the receive processor is stopped
3074 and the transmitter is disabled. After these operations a
3075 4 uS delay is done before clearing the pointers to allow
3076 the receive processor to stop. These items are handled inside
3078 Warnings: No context switches are allowed while executing this function.
3080 static void sFlushTxFIFO(CHANNEL_T * ChP)
3083 Byte_t Ch; /* channel number within AIOP */
3084 int TxEnabled; /* 1 if transmitter enabled */
3086 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3087 return; /* don't need to flush */
3090 if (ChP->TxControl[3] & TX_ENABLE) {
3092 sDisTransmit(ChP); /* disable transmitter */
3094 sStopRxProcessor(ChP); /* stop Rx processor */
3095 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3096 sInB(ChP->IntChan); /* depends on bus i/o timing */
3097 Ch = (Byte_t) sGetChanNum(ChP);
3098 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3099 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3100 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3101 sOutW(ChP->IndexData, 0);
3103 sEnTransmit(ChP); /* enable transmitter */
3104 sStartRxProcessor(ChP); /* restart Rx processor */
3107 /***************************************************************************
3108 Function: sWriteTxPrioByte
3109 Purpose: Write a byte of priority transmit data to a channel
3110 Call: sWriteTxPrioByte(ChP,Data)
3111 CHANNEL_T *ChP; Ptr to channel structure
3112 Byte_t Data; The transmit data byte
3114 Return: int: 1 if the bytes is successfully written, otherwise 0.
3116 Comments: The priority byte is transmitted before any data in the Tx FIFO.
3118 Warnings: No context switches are allowed while executing this function.
3120 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3122 Byte_t DWBuf[4]; /* buffer for double word writes */
3123 Word_t *WordPtr; /* must be far because Win SS != DS */
3124 register DWordIO_t IndexAddr;
3126 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3127 IndexAddr = ChP->IndexAddr;
3128 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3129 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3130 return (0); /* nothing sent */
3132 WordPtr = (Word_t *) (&DWBuf[0]);
3133 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3135 DWBuf[2] = Data; /* data byte value */
3136 out32(IndexAddr, DWBuf); /* write it out */
3138 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3140 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3141 DWBuf[3] = 0; /* priority buffer pointer */
3142 out32(IndexAddr, DWBuf); /* write it out */
3143 } else { /* write it to Tx FIFO */
3145 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3147 return (1); /* 1 byte sent */
3150 /***************************************************************************
3151 Function: sEnInterrupts
3152 Purpose: Enable one or more interrupts for a channel
3153 Call: sEnInterrupts(ChP,Flags)
3154 CHANNEL_T *ChP; Ptr to channel structure
3155 Word_t Flags: Interrupt enable flags, can be any combination
3156 of the following flags:
3157 TXINT_EN: Interrupt on Tx FIFO empty
3158 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3160 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3161 MCINT_EN: Interrupt on modem input change
3162 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3163 Interrupt Channel Register.
3165 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3166 enabled. If an interrupt enable flag is not set in Flags, that
3167 interrupt will not be changed. Interrupts can be disabled with
3168 function sDisInterrupts().
3170 This function sets the appropriate bit for the channel in the AIOP's
3171 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3172 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3174 Interrupts must also be globally enabled before channel interrupts
3175 will be passed on to the host. This is done with function
3178 In some cases it may be desirable to disable interrupts globally but
3179 enable channel interrupts. This would allow the global interrupt
3180 status register to be used to determine which AIOPs need service.
3182 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3184 Byte_t Mask; /* Interrupt Mask Register */
3186 ChP->RxControl[2] |=
3187 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3189 out32(ChP->IndexAddr, ChP->RxControl);
3191 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3193 out32(ChP->IndexAddr, ChP->TxControl);
3195 if (Flags & CHANINT_EN) {
3196 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3197 sOutB(ChP->IntMask, Mask);
3201 /***************************************************************************
3202 Function: sDisInterrupts
3203 Purpose: Disable one or more interrupts for a channel
3204 Call: sDisInterrupts(ChP,Flags)
3205 CHANNEL_T *ChP; Ptr to channel structure
3206 Word_t Flags: Interrupt flags, can be any combination
3207 of the following flags:
3208 TXINT_EN: Interrupt on Tx FIFO empty
3209 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3211 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3212 MCINT_EN: Interrupt on modem input change
3213 CHANINT_EN: Disable channel interrupt signal to the
3214 AIOP's Interrupt Channel Register.
3216 Comments: If an interrupt flag is set in Flags, that interrupt will be
3217 disabled. If an interrupt flag is not set in Flags, that
3218 interrupt will not be changed. Interrupts can be enabled with
3219 function sEnInterrupts().
3221 This function clears the appropriate bit for the channel in the AIOP's
3222 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3223 this channel's bit from being set in the AIOP's Interrupt Channel
3226 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3228 Byte_t Mask; /* Interrupt Mask Register */
3230 ChP->RxControl[2] &=
3231 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3232 out32(ChP->IndexAddr, ChP->RxControl);
3233 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3234 out32(ChP->IndexAddr, ChP->TxControl);
3236 if (Flags & CHANINT_EN) {
3237 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3238 sOutB(ChP->IntMask, Mask);
3242 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3244 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3248 * Not an official SSCI function, but how to reset RocketModems.
3251 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3256 addr = CtlP->AiopIO[0] + 0x400;
3257 val = sInB(CtlP->MReg3IO);
3258 /* if AIOP[1] is not enabled, enable it */
3259 if ((val & 2) == 0) {
3260 val = sInB(CtlP->MReg2IO);
3261 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3262 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3268 sOutB(addr + chan, 0); /* apply or remove reset */
3273 * Not an official SSCI function, but how to reset RocketModems.
3276 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3280 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3283 sOutB(addr + chan, 0); /* apply or remove reset */
3286 /* Resets the speaker controller on RocketModem II and III devices */
3287 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3291 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3292 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3293 addr = CtlP->AiopIO[0] + 0x4F;
3297 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3298 if ((model == MODEL_UPCI_RM3_8PORT)
3299 || (model == MODEL_UPCI_RM3_4PORT)) {
3300 addr = CtlP->AiopIO[0] + 0x88;
3305 /* Returns the line number given the controller (board), aiop and channel number */
3306 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3308 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3312 * Stores the line number associated with a given controller (board), aiop
3313 * and channel number.
3314 * Returns: The line number assigned
3316 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3318 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3319 return (nextLineNumber - 1);