1 #ifndef __PLAT_OMAP_DSP_MMU_H
2 #define __PLAT_OMAP_DSP_MMU_H
4 #ifdef CONFIG_ARCH_OMAP1
6 #ifdef CONFIG_ARCH_OMAP15XX
7 struct omap_mmu dsp_mmu = {
10 .base = IO_ADDRESS(OMAP1510_DSP_MMU_BASE),
11 .membase = OMAP1510_DSP_BASE,
12 .memsize = OMAP1510_DSP_SIZE,
15 .irq = INT_1510_DSP_MMU,
16 .ops = &omap1_mmu_ops,
19 #ifdef CONFIG_ARCH_OMAP16XX
20 struct omap_mmu dsp_mmu = {
23 .base = IO_ADDRESS(OMAP16XX_DSP_MMU_BASE),
24 .membase = OMAP16XX_DSP_BASE,
25 .memsize = OMAP16XX_DSP_SIZE,
28 .irq = INT_1610_DSP_MMU,
29 .ops = &omap1_mmu_ops,
33 struct omap_mmu dsp_mmu = {
36 .base = DSP_MMU_24XX_VIRT,
37 .membase = DSP_MEM_24XX_VIRT,
38 .memsize = DSP_MEM_24XX_SIZE,
41 .irq = INT_24XX_DSP_MMU,
42 .ops = &omap2_mmu_ops,
45 #define IOMAP_VAL 0x3f
48 #ifdef CONFIG_FB_OMAP_LCDC_EXTERNAL
49 static struct omapfb_notifier_block *omapfb_nb;
50 static int omapfb_ready;
56 #ifdef CONFIG_ARCH_OMAP1
57 #define EMIF_PRIO_LB_MASK 0x0000f000
58 #define EMIF_PRIO_LB_SHIFT 12
59 #define EMIF_PRIO_DMA_MASK 0x00000f00
60 #define EMIF_PRIO_DMA_SHIFT 8
61 #define EMIF_PRIO_DSP_MASK 0x00000070
62 #define EMIF_PRIO_DSP_SHIFT 4
63 #define EMIF_PRIO_MPU_MASK 0x00000007
64 #define EMIF_PRIO_MPU_SHIFT 0
65 #define set_emiff_dma_prio(prio) \
67 omap_writel((omap_readl(OMAP_TC_OCPT1_PRIOR) & \
68 ~EMIF_PRIO_DMA_MASK) | \
69 ((prio) << EMIF_PRIO_DMA_SHIFT), \
70 OMAP_TC_OCPT1_PRIOR); \
73 #define set_emiff_dma_prio(prio) do { } while (0)
74 #endif /* CONFIG_ARCH_OMAP1 */
76 #ifdef CONFIG_ARCH_OMAP1
77 static int dsp_mmu_itack(void)
81 pr_info("omapdsp: sending DSP MMU interrupt ack.\n");
82 if (!dsp_err_isset(ERRCODE_MMU)) {
83 printk(KERN_ERR "omapdsp: DSP MMU error has not been set.\n");
86 dspadr = dsp_mmu.fault_address & ~(SZ_4K-1);
87 /* FIXME: reserve TLB entry for this */
88 omap_mmu_exmap(&dsp_mmu, dspadr, 0, SZ_4K, EXMAP_TYPE_MEM);
89 pr_info("omapdsp: falling into recovery runlevel...\n");
90 dsp_set_runlevel(RUNLEVEL_RECOVERY);
91 omap_mmu_itack(&dsp_mmu);
93 omap_mmu_exunmap(&dsp_mmu, dspadr);
94 dsp_err_clear(ERRCODE_MMU);
99 * intmem_enable() / disable():
100 * if the address is in DSP internal memories,
101 * we send PM mailbox commands so that DSP DMA domain won't go in idle
102 * when ARM is accessing to those memories.
104 static int intmem_enable(void)
108 if (dsp_cfgstat_get_stat() == CFGSTAT_READY)
109 ret = mbcompose_send(PM, PM_ENABLE, DSPREG_ICR_DMA);
114 static void intmem_disable(void) {
115 if (dsp_cfgstat_get_stat() == CFGSTAT_READY)
116 mbcompose_send(PM, PM_DISABLE, DSPREG_ICR_DMA);
119 static int intmem_enable(void) { return 0; }
120 static void intmem_disable(void) { }
121 static int dsp_mmu_itack(void) { return 0; }
124 #ifdef CONFIG_ARCH_OMAP2
125 static inline void dsp_mem_ipi_init(void)
127 int i, dspmem_pg_count;
128 dspmem_pg_count = dspmem_size >> 12;
129 for (i = 0; i < dspmem_pg_count; i++) {
130 writel(i, DSP_IPI_INDEX);
131 writel(DSP_IPI_ENTRY_ELMSIZEVALUE_16, DSP_IPI_ENTRY);
133 writel(1, DSP_IPI_ENABLE);
134 writel(IOMAP_VAL, DSP_IPI_IOMAP);
137 static inline void dsp_mem_ipi_init(void) { }
140 #endif /* __PLAT_OMAP_DSP_MMU_H */