2 * Defines, structures, APIs for edac_core module
4 * (C) 2007 Linux Networx (http://lnxi.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
8 * Written by Thayne Harbaugh
9 * Based on work by Dan Hollis <goemon at anime dot net> and others.
10 * http://www.anime.net/~goemon/linux-ecc/
12 * NMI handling support added by
13 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>
15 * Refactored for multi-source files:
16 * Doug Thompson <norsk5@xmission.com>
23 #include <linux/kernel.h>
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/spinlock.h>
27 #include <linux/smp.h>
28 #include <linux/pci.h>
29 #include <linux/time.h>
30 #include <linux/nmi.h>
31 #include <linux/rcupdate.h>
32 #include <linux/completion.h>
33 #include <linux/kobject.h>
34 #include <linux/platform_device.h>
35 #include <linux/sysdev.h>
36 #include <linux/workqueue.h>
37 #include <linux/version.h>
39 #define EDAC_MC_LABEL_LEN 31
40 #define EDAC_DEVICE_NAME_LEN 31
41 #define EDAC_ATTRIB_VALUE_LEN 15
42 #define MC_PROC_NAME_MAX_LEN 7
45 #define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) )
46 #else /* PAGE_SHIFT > 20 */
47 #define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) )
50 #define edac_printk(level, prefix, fmt, arg...) \
51 printk(level "EDAC " prefix ": " fmt, ##arg)
53 #define edac_mc_printk(mci, level, fmt, arg...) \
54 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg)
56 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \
57 printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg)
59 /* edac_device printk */
60 #define edac_device_printk(ctl, level, fmt, arg...) \
61 printk(level "EDAC DEVICE%d: " fmt, ctl->dev_idx, ##arg)
64 #define edac_pci_printk(ctl, level, fmt, arg...) \
65 printk(level "EDAC PCI%d: " fmt, ctl->pci_idx, ##arg)
67 /* prefixes for edac_printk() and edac_mc_printk() */
69 #define EDAC_PCI "PCI"
70 #define EDAC_DEBUG "DEBUG"
72 #ifdef CONFIG_EDAC_DEBUG
73 extern int edac_debug_level;
75 #define edac_debug_printk(level, fmt, arg...) \
77 if (level <= edac_debug_level) \
78 edac_printk(KERN_EMERG, EDAC_DEBUG, fmt, ##arg); \
81 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ )
82 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ )
83 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ )
84 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ )
85 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ )
87 #else /* !CONFIG_EDAC_DEBUG */
89 #define debugf0( ... )
90 #define debugf1( ... )
91 #define debugf2( ... )
92 #define debugf3( ... )
93 #define debugf4( ... )
95 #endif /* !CONFIG_EDAC_DEBUG */
97 #define BIT(x) (1 << (x))
99 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \
100 PCI_DEVICE_ID_ ## vend ## _ ## dev
102 #define dev_name(dev) (dev)->dev_name
112 DEV_X32, /* Do these parts exist? */
113 DEV_X64 /* Do these parts exist? */
116 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
117 #define DEV_FLAG_X1 BIT(DEV_X1)
118 #define DEV_FLAG_X2 BIT(DEV_X2)
119 #define DEV_FLAG_X4 BIT(DEV_X4)
120 #define DEV_FLAG_X8 BIT(DEV_X8)
121 #define DEV_FLAG_X16 BIT(DEV_X16)
122 #define DEV_FLAG_X32 BIT(DEV_X32)
123 #define DEV_FLAG_X64 BIT(DEV_X64)
127 MEM_EMPTY = 0, /* Empty csrow */
128 MEM_RESERVED, /* Reserved csrow type */
129 MEM_UNKNOWN, /* Unknown csrow type */
130 MEM_FPM, /* Fast page mode */
131 MEM_EDO, /* Extended data out */
132 MEM_BEDO, /* Burst Extended data out */
133 MEM_SDR, /* Single data rate SDRAM */
134 MEM_RDR, /* Registered single data rate SDRAM */
135 MEM_DDR, /* Double data rate SDRAM */
136 MEM_RDDR, /* Registered Double data rate SDRAM */
137 MEM_RMBS, /* Rambus DRAM */
138 MEM_DDR2, /* DDR2 RAM */
139 MEM_FB_DDR2, /* fully buffered DDR2 */
140 MEM_RDDR2, /* Registered DDR2 RAM */
143 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
144 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
145 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
146 #define MEM_FLAG_FPM BIT(MEM_FPM)
147 #define MEM_FLAG_EDO BIT(MEM_EDO)
148 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
149 #define MEM_FLAG_SDR BIT(MEM_SDR)
150 #define MEM_FLAG_RDR BIT(MEM_RDR)
151 #define MEM_FLAG_DDR BIT(MEM_DDR)
152 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
153 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
154 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
155 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
156 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
158 /* chipset Error Detection and Correction capabilities and mode */
160 EDAC_UNKNOWN = 0, /* Unknown if ECC is available */
161 EDAC_NONE, /* Doesnt support ECC */
162 EDAC_RESERVED, /* Reserved ECC type */
163 EDAC_PARITY, /* Detects parity errors */
164 EDAC_EC, /* Error Checking - no correction */
165 EDAC_SECDED, /* Single bit error correction, Double detection */
166 EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */
167 EDAC_S4ECD4ED, /* Chipkill x4 devices */
168 EDAC_S8ECD8ED, /* Chipkill x8 devices */
169 EDAC_S16ECD16ED, /* Chipkill x16 devices */
172 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
173 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
174 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
175 #define EDAC_FLAG_EC BIT(EDAC_EC)
176 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
177 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
178 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
179 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
180 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
182 /* scrubbing capabilities */
184 SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */
185 SCRUB_NONE, /* No scrubber */
186 SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */
187 SCRUB_SW_SRC, /* Software scrub only errors */
188 SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */
189 SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */
190 SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */
191 SCRUB_HW_SRC, /* Hardware scrub only errors */
192 SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */
193 SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */
196 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
197 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
198 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
199 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
200 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
201 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
202 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
203 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
205 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
207 /* EDAC internal operation states */
208 #define OP_ALLOC 0x100
209 #define OP_RUNNING_POLL 0x201
210 #define OP_RUNNING_INTERRUPT 0x202
211 #define OP_RUNNING_POLL_INTR 0x203
212 #define OP_OFFLINE 0x300
214 extern char *edac_align_ptr(void *ptr, unsigned size);
217 * There are several things to be aware of that aren't at all obvious:
220 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc..
222 * These are some of the many terms that are thrown about that don't always
223 * mean what people think they mean (Inconceivable!). In the interest of
224 * creating a common ground for discussion, terms and their definitions
225 * will be established.
227 * Memory devices: The individual chip on a memory stick. These devices
228 * commonly output 4 and 8 bits each. Grouping several
229 * of these in parallel provides 64 bits which is common
230 * for a memory stick.
232 * Memory Stick: A printed circuit board that agregates multiple
233 * memory devices in parallel. This is the atomic
234 * memory component that is purchaseable by Joe consumer
235 * and loaded into a memory socket.
237 * Socket: A physical connector on the motherboard that accepts
238 * a single memory stick.
240 * Channel: Set of memory devices on a memory stick that must be
241 * grouped in parallel with one or more additional
242 * channels from other memory sticks. This parallel
243 * grouping of the output from multiple channels are
244 * necessary for the smallest granularity of memory access.
245 * Some memory controllers are capable of single channel -
246 * which means that memory sticks can be loaded
247 * individually. Other memory controllers are only
248 * capable of dual channel - which means that memory
249 * sticks must be loaded as pairs (see "socket set").
251 * Chip-select row: All of the memory devices that are selected together.
252 * for a single, minimum grain of memory access.
253 * This selects all of the parallel memory devices across
254 * all of the parallel channels. Common chip-select rows
255 * for single channel are 64 bits, for dual channel 128
258 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory.
259 * Motherboards commonly drive two chip-select pins to
260 * a memory stick. A single-ranked stick, will occupy
261 * only one of those rows. The other will be unused.
263 * Double-Ranked stick: A double-ranked stick has two chip-select rows which
264 * access different sets of memory devices. The two
265 * rows cannot be accessed concurrently.
267 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick.
268 * A double-sided stick has two chip-select rows which
269 * access different sets of memory devices. The two
270 * rows cannot be accessed concurrently. "Double-sided"
271 * is irrespective of the memory devices being mounted
272 * on both sides of the memory stick.
274 * Socket set: All of the memory sticks that are required for for
275 * a single memory access or all of the memory sticks
276 * spanned by a chip-select row. A single socket set
277 * has two chip-select rows and if double-sided sticks
278 * are used these will occupy those chip-select rows.
280 * Bank: This term is avoided because it is unclear when
281 * needing to distinguish between chip-select rows and
291 * STRUCTURE ORGANIZATION AND CHOICES
295 * PS - I enjoyed writing all that about as much as you enjoyed reading it.
298 struct channel_info {
299 int chan_idx; /* channel index */
300 u32 ce_count; /* Correctable Errors for this CHANNEL */
301 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
302 struct csrow_info *csrow; /* the parent */
306 unsigned long first_page; /* first page number in dimm */
307 unsigned long last_page; /* last page number in dimm */
308 unsigned long page_mask; /* used for interleaving -
311 u32 nr_pages; /* number of pages in csrow */
312 u32 grain; /* granularity of reported error in bytes */
313 int csrow_idx; /* the chip-select row */
314 enum dev_type dtype; /* memory device type */
315 u32 ue_count; /* Uncorrectable Errors for this csrow */
316 u32 ce_count; /* Correctable Errors for this csrow */
317 enum mem_type mtype; /* memory csrow type */
318 enum edac_type edac_mode; /* EDAC mode for this csrow */
319 struct mem_ctl_info *mci; /* the parent */
321 struct kobject kobj; /* sysfs kobject for this csrow */
322 struct completion kobj_complete;
324 /* FIXME the number of CHANNELs might need to become dynamic */
326 struct channel_info *channels;
329 struct mem_ctl_info {
330 struct list_head link; /* for global list of mem_ctl_info structs */
331 unsigned long mtype_cap; /* memory types supported by mc */
332 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
333 unsigned long edac_cap; /* configuration capabilities - this is
334 * closely related to edac_ctl_cap. The
335 * difference is that the controller may be
336 * capable of s4ecd4ed which would be listed
337 * in edac_ctl_cap, but if channels aren't
338 * capable of s4ecd4ed then the edac_cap would
339 * not have that capability.
341 unsigned long scrub_cap; /* chipset scrub capabilities */
342 enum scrub_type scrub_mode; /* current scrub mode */
344 /* Translates sdram memory scrub rate given in bytes/sec to the
345 internal representation and configures whatever else needs
348 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
350 /* Get the current sdram memory scrub rate from the internal
351 representation and converts it to the closest matching
352 bandwith in bytes/sec.
354 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 * bw);
356 /* pointer to edac checking routine */
357 void (*edac_check) (struct mem_ctl_info * mci);
360 * Remaps memory pages: controller pages to physical pages.
361 * For most MC's, this will be NULL.
363 /* FIXME - why not send the phys page to begin with? */
364 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
368 struct csrow_info *csrows;
370 * FIXME - what about controllers on other busses? - IDs must be
371 * unique. dev pointer should be sufficiently unique, but
372 * BUS:SLOT.FUNC numbers may not be unique.
375 const char *mod_name;
377 const char *ctl_name;
378 const char *dev_name;
379 char proc_name[MC_PROC_NAME_MAX_LEN + 1];
381 u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */
382 u32 ce_noinfo_count; /* Correctable Errors w/o info */
383 u32 ue_count; /* Total Uncorrectable Errors for this MC */
384 u32 ce_count; /* Total Correctable Errors for this MC */
385 unsigned long start_time; /* mci load start time (in jiffies) */
387 /* this stuff is for safe removal of mc devices from global list while
388 * NMI handlers may be traversing list
391 struct completion complete;
393 /* edac sysfs device control */
394 struct kobject edac_mci_kobj;
395 struct completion kobj_complete;
397 /* work struct for this MC */
398 struct delayed_work work;
400 /* the internal state of this controller instance */
405 * The following are the structures to provide for a generice
406 * or abstract 'edac_device'. This set of structures and the
407 * code that implements the APIs for the same, provide for
408 * registering EDAC type devices which are NOT standard memory.
410 * CPU caches (L1 and L2)
413 * Fabric switch units
414 * PCIe interface controllers
415 * other EDAC/ECC type devices that can be monitored for
418 * It allows for a 2 level set of hiearchry. For example:
420 * cache could be composed of L1, L2 and L3 levels of cache.
421 * Each CPU core would have its own L1 cache, while sharing
422 * L2 and maybe L3 caches.
424 * View them arranged, via the sysfs presentation:
425 * /sys/devices/system/edac/..
427 * mc/ <existing memory device directory>
428 * cpu/cpu0/.. <L1 and L2 block directory>
433 * cpu/cpu1/.. <L1 and L2 block directory>
440 * the L1 and L2 directories would be "edac_device_block's"
443 struct edac_device_counter {
448 #define INC_COUNTER(cnt) (cnt++)
451 * An array of these is passed to the alloc() function
452 * to specify attributes of the edac_block
454 struct edac_attrib_spec {
455 char name[EDAC_DEVICE_NAME_LEN + 1];
458 #define EDAC_ATTR_INT 0x01
459 #define EDAC_ATTR_CHAR 0x02
462 /* Attribute control structure
463 * In this structure is a pointer to the driver's edac_attrib_spec
464 * The life of this pointer is inclusive in the life of the driver's
468 struct edac_device_block *block; /* Up Pointer */
470 struct edac_attrib_spec *spec; /* ptr to module spec entry */
472 union { /* actual value */
473 int edac_attrib_int_value;
474 char edac_attrib_char_value[EDAC_ATTRIB_VALUE_LEN + 1];
478 /* device block control structure */
479 struct edac_device_block {
480 struct edac_device_instance *instance; /* Up Pointer */
481 char name[EDAC_DEVICE_NAME_LEN + 1];
483 struct edac_device_counter counters; /* basic UE and CE counters */
485 int nr_attribs; /* how many attributes */
486 struct edac_attrib *attribs; /* this block's attributes */
488 /* edac sysfs device control */
490 struct completion kobj_complete;
493 /* device instance control structure */
494 struct edac_device_instance {
495 struct edac_device_ctl_info *ctl; /* Up pointer */
496 char name[EDAC_DEVICE_NAME_LEN + 4];
498 struct edac_device_counter counters; /* instance counters */
500 u32 nr_blocks; /* how many blocks */
501 struct edac_device_block *blocks; /* block array */
503 /* edac sysfs device control */
505 struct completion kobj_complete;
509 * Abstract edac_device control info structure
512 struct edac_device_ctl_info {
513 /* for global list of edac_device_ctl_info structs */
514 struct list_head link;
518 /* Per instance controls for this edac_device */
519 int log_ue; /* boolean for logging UEs */
520 int log_ce; /* boolean for logging CEs */
521 int panic_on_ue; /* boolean for panic'ing on an UE */
522 unsigned poll_msec; /* number of milliseconds to poll interval */
523 unsigned long delay; /* number of jiffies for poll_msec */
525 struct sysdev_class *edac_class; /* pointer to class */
527 /* the internal state of this controller instance */
529 /* work struct for this instance */
530 struct delayed_work work;
532 /* pointer to edac polling checking routine:
533 * If NOT NULL: points to polling check routine
534 * If NULL: Then assumes INTERRUPT operation, where
535 * MC driver will receive events
537 void (*edac_check) (struct edac_device_ctl_info * edac_dev);
539 struct device *dev; /* pointer to device structure */
541 const char *mod_name; /* module name */
542 const char *ctl_name; /* edac controller name */
543 const char *dev_name; /* pci/platform/etc... name */
545 void *pvt_info; /* pointer to 'private driver' info */
547 unsigned long start_time; /* edac_device load start time (jiffies) */
549 /* these are for safe removal of mc devices from global list while
550 * NMI handlers may be traversing list
553 struct completion complete;
555 /* sysfs top name under 'edac' directory
562 char name[EDAC_DEVICE_NAME_LEN + 1];
564 /* Number of instances supported on this control structure
565 * and the array of those instances
568 struct edac_device_instance *instances;
570 /* Event counters for the this whole EDAC Device */
571 struct edac_device_counter counters;
573 /* edac sysfs device control for the 'name'
574 * device this structure controls
577 struct completion kobj_complete;
580 /* To get from the instance's wq to the beginning of the ctl structure */
581 #define to_edac_mem_ctl_work(w) \
582 container_of(w, struct mem_ctl_info, work)
584 #define to_edac_device_ctl_work(w) \
585 container_of(w,struct edac_device_ctl_info,work)
587 /* Function to calc the number of delay jiffies from poll_msec */
588 static inline void edac_device_calc_delay(struct edac_device_ctl_info *edac_dev)
590 /* convert from msec to jiffies */
591 edac_dev->delay = edac_dev->poll_msec * HZ / 1000;
594 #define edac_calc_delay(dev) dev->delay = dev->poll_msec * HZ / 1000;
597 * The alloc() and free() functions for the 'edac_device' control info
598 * structure. A MC driver will allocate one of these for each edac_device
599 * it is going to control/register with the EDAC CORE.
601 extern struct edac_device_ctl_info *edac_device_alloc_ctl_info(
602 unsigned sizeof_private,
603 char *edac_device_name,
604 unsigned nr_instances,
605 char *edac_block_name,
607 unsigned offset_value,
608 struct edac_attrib_spec *attrib_spec,
609 unsigned nr_attribs);
611 /* The offset value can be:
612 * -1 indicating no offset value
613 * 0 for zero-based block numbers
614 * 1 for 1-based block number
615 * other for other-based block number
617 #define BLOCK_OFFSET_VALUE_OFF ((unsigned) -1)
619 extern void edac_device_free_ctl_info(struct edac_device_ctl_info *ctl_info);
623 struct edac_pci_counter {
629 * Abstract edac_pci control info structure
632 struct edac_pci_ctl_info {
633 /* for global list of edac_pci_ctl_info structs */
634 struct list_head link;
638 struct sysdev_class *edac_class; /* pointer to class */
640 /* the internal state of this controller instance */
642 /* work struct for this instance */
643 struct delayed_work work;
645 /* pointer to edac polling checking routine:
646 * If NOT NULL: points to polling check routine
647 * If NULL: Then assumes INTERRUPT operation, where
648 * MC driver will receive events
650 void (*edac_check) (struct edac_pci_ctl_info * edac_dev);
652 struct device *dev; /* pointer to device structure */
654 const char *mod_name; /* module name */
655 const char *ctl_name; /* edac controller name */
656 const char *dev_name; /* pci/platform/etc... name */
658 void *pvt_info; /* pointer to 'private driver' info */
660 unsigned long start_time; /* edac_pci load start time (jiffies) */
662 /* these are for safe removal of devices from global list while
663 * NMI handlers may be traversing list
666 struct completion complete;
668 /* sysfs top name under 'edac' directory
675 char name[EDAC_DEVICE_NAME_LEN + 1];
677 /* Event counters for the this whole EDAC Device */
678 struct edac_pci_counter counters;
680 /* edac sysfs device control for the 'name'
681 * device this structure controls
684 struct completion kobj_complete;
687 #define to_edac_pci_ctl_work(w) \
688 container_of(w, struct edac_pci_ctl_info,work)
690 /* write all or some bits in a byte-register*/
691 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value,
697 pci_read_config_byte(pdev, offset, &buf);
703 pci_write_config_byte(pdev, offset, value);
706 /* write all or some bits in a word-register*/
707 static inline void pci_write_bits16(struct pci_dev *pdev, int offset,
710 if (mask != 0xffff) {
713 pci_read_config_word(pdev, offset, &buf);
719 pci_write_config_word(pdev, offset, value);
722 /* write all or some bits in a dword-register*/
723 static inline void pci_write_bits32(struct pci_dev *pdev, int offset,
726 if (mask != 0xffff) {
729 pci_read_config_dword(pdev, offset, &buf);
735 pci_write_config_dword(pdev, offset, value);
738 #endif /* CONFIG_PCI */
740 extern struct mem_ctl_info *edac_mc_find(int idx);
741 extern int edac_mc_add_mc(struct mem_ctl_info *mci, int mc_idx);
742 extern struct mem_ctl_info *edac_mc_del_mc(struct device *dev);
743 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci,
747 * The no info errors are used when error overflows are reported.
748 * There are a limited number of error logging registers that can
749 * be exausted. When all registers are exhausted and an additional
750 * error occurs then an error overflow register records that an
751 * error occured and the type of error, but doesn't have any
752 * further information. The ce/ue versions make for cleaner
753 * reporting logic and function interface - reduces conditional
754 * statement clutter and extra function arguments.
756 extern void edac_mc_handle_ce(struct mem_ctl_info *mci,
757 unsigned long page_frame_number,
758 unsigned long offset_in_page,
759 unsigned long syndrome, int row, int channel,
761 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci,
763 extern void edac_mc_handle_ue(struct mem_ctl_info *mci,
764 unsigned long page_frame_number,
765 unsigned long offset_in_page, int row,
767 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci,
769 extern void edac_mc_handle_fbd_ue(struct mem_ctl_info *mci, unsigned int csrow,
770 unsigned int channel0, unsigned int channel1,
772 extern void edac_mc_handle_fbd_ce(struct mem_ctl_info *mci, unsigned int csrow,
773 unsigned int channel, char *msg);
778 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows,
780 extern void edac_mc_free(struct mem_ctl_info *mci);
781 extern int edac_device_add_device(struct edac_device_ctl_info *edac_dev,
783 extern struct edac_device_ctl_info *edac_device_del_device(struct device *dev);
784 extern void edac_device_handle_ue(struct edac_device_ctl_info *edac_dev,
785 int inst_nr, int block_nr, const char *msg);
786 extern void edac_device_handle_ce(struct edac_device_ctl_info *edac_dev,
787 int inst_nr, int block_nr, const char *msg);
792 extern struct edac_pci_ctl_info *edac_pci_alloc_ctl_info(unsigned int sz_pvt, const char
795 extern void edac_pci_free_ctl_info(struct edac_pci_ctl_info *pci);
798 edac_pci_reset_delay_period(struct edac_pci_ctl_info *pci, unsigned long value);
800 extern int edac_pci_add_device(struct edac_pci_ctl_info *pci, int edac_idx);
801 extern struct edac_pci_ctl_info *edac_pci_del_device(struct device *dev);
803 extern struct edac_pci_ctl_info *edac_pci_create_generic_ctl(struct device *dev, const char
806 extern void edac_pci_release_generic_ctl(struct edac_pci_ctl_info *pci);
807 extern int edac_pci_create_sysfs(struct edac_pci_ctl_info *pci);
808 extern void edac_pci_remove_sysfs(struct edac_pci_ctl_info *pci);
813 extern char *edac_op_state_toString(int op_state);
815 #endif /* _EDAC_CORE_H_ */