drivers/firewire/fw-ohci.c

   1 /*                                              -*- c-basic-offset: 8 -*-
   2  *
   3  * fw-ohci.c - Driver for OHCI 1394 boards
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/pci.h>
  26 #include <linux/delay.h>
  27 #include <linux/poll.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <asm/uaccess.h>
  31 #include <asm/semaphore.h>
  32
  33 #include "fw-transaction.h"
  34 #include "fw-ohci.h"
  35
  36 #define descriptor_output_more          0
  37 #define descriptor_output_last          (1 << 12)
  38 #define descriptor_input_more           (2 << 12)
  39 #define descriptor_input_last           (3 << 12)
  40 #define descriptor_status               (1 << 11)
  41 #define descriptor_key_immediate        (2 << 8)
  42 #define descriptor_ping                 (1 << 7)
  43 #define descriptor_yy                   (1 << 6)
  44 #define descriptor_no_irq               (0 << 4)
  45 #define descriptor_irq_error            (1 << 4)
  46 #define descriptor_irq_always           (3 << 4)
  47 #define descriptor_branch_always        (3 << 2)
  48 #define descriptor_wait                 (3 << 0)
  49
  50 struct descriptor {
  51         __le16 req_count;
  52         __le16 control;
  53         __le32 data_address;
  54         __le32 branch_address;
  55         __le16 res_count;
  56         __le16 transfer_status;
  57 } __attribute__((aligned(16)));
  58
  59 struct db_descriptor {
  60         __le16 first_size;
  61         __le16 control;
  62         __le16 second_req_count;
  63         __le16 first_req_count;
  64         __le32 branch_address;
  65         __le16 second_res_count;
  66         __le16 first_res_count;
  67         __le32 reserved0;
  68         __le32 first_buffer;
  69         __le32 second_buffer;
  70         __le32 reserved1;
  71 } __attribute__((aligned(16)));
  72
  73 #define control_set(regs)       (regs)
  74 #define control_clear(regs)     ((regs) + 4)
  75 #define command_ptr(regs)       ((regs) + 12)
  76 #define context_match(regs)     ((regs) + 16)
  77
  78 struct ar_buffer {
  79         struct descriptor descriptor;
  80         struct ar_buffer *next;
  81         __le32 data[0];
  82 };
  83
  84 struct ar_context {
  85         struct fw_ohci *ohci;
  86         struct ar_buffer *current_buffer;
  87         struct ar_buffer *last_buffer;
  88         void *pointer;
  89         u32 regs;
  90         struct tasklet_struct tasklet;
  91 };
  92
  93 struct context;
  94
  95 typedef int (*descriptor_callback_t)(struct context *ctx,
  96                                      struct descriptor *d,
  97                                      struct descriptor *last);
  98 struct context {
  99         struct fw_ohci *ohci;
 100         u32 regs;
 101
 102         struct descriptor *buffer;
 103         dma_addr_t buffer_bus;
 104         size_t buffer_size;
 105         struct descriptor *head_descriptor;
 106         struct descriptor *tail_descriptor;
 107         struct descriptor *tail_descriptor_last;
 108         struct descriptor *prev_descriptor;
 109
 110         descriptor_callback_t callback;
 111
 112         struct tasklet_struct tasklet;
 113 };
 114
 115 #define it_header_sy(v)          ((v) <<  0)
 116 #define it_header_tcode(v)       ((v) <<  4)
 117 #define it_header_channel(v)     ((v) <<  8)
 118 #define it_header_tag(v)         ((v) << 14)
 119 #define it_header_speed(v)       ((v) << 16)
 120 #define it_header_data_length(v) ((v) << 16)
 121
 122 struct iso_context {
 123         struct fw_iso_context base;
 124         struct context context;
 125         void *header;
 126         size_t header_length;
 127 };
 128
 129 #define CONFIG_ROM_SIZE 1024
 130
 131 struct fw_ohci {
 132         struct fw_card card;
 133
 134         u32 version;
 135         __iomem char *registers;
 136         dma_addr_t self_id_bus;
 137         __le32 *self_id_cpu;
 138         struct tasklet_struct bus_reset_tasklet;
 139         int node_id;
 140         int generation;
 141         int request_generation;
 142         u32 bus_seconds;
 143
 144         /* Spinlock for accessing fw_ohci data.  Never call out of
 145          * this driver with this lock held. */
 146         spinlock_t lock;
 147         u32 self_id_buffer[512];
 148
 149         /* Config rom buffers */
 150         __be32 *config_rom;
 151         dma_addr_t config_rom_bus;
 152         __be32 *next_config_rom;
 153         dma_addr_t next_config_rom_bus;
 154         u32 next_header;
 155
 156         struct ar_context ar_request_ctx;
 157         struct ar_context ar_response_ctx;
 158         struct context at_request_ctx;
 159         struct context at_response_ctx;
 160
 161         u32 it_context_mask;
 162         struct iso_context *it_context_list;
 163         u32 ir_context_mask;
 164         struct iso_context *ir_context_list;
 165 };
 166
 167 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 168 {
 169         return container_of(card, struct fw_ohci, card);
 170 }
 171
 172 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 173 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 174 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 175 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 176 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 177 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 178
 179 #define CONTEXT_RUN     0x8000
 180 #define CONTEXT_WAKE    0x1000
 181 #define CONTEXT_DEAD    0x0800
 182 #define CONTEXT_ACTIVE  0x0400
 183
 184 #define OHCI1394_MAX_AT_REQ_RETRIES     0x2
 185 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 186 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 187
 188 #define FW_OHCI_MAJOR                   240
 189 #define OHCI1394_REGISTER_SIZE          0x800
 190 #define OHCI_LOOP_COUNT                 500
 191 #define OHCI1394_PCI_HCI_Control        0x40
 192 #define SELF_ID_BUF_SIZE                0x800
 193 #define OHCI_TCODE_PHY_PACKET           0x0e
 194 #define OHCI_VERSION_1_1                0x010010
 195 #define ISO_BUFFER_SIZE                 (64 * 1024)
 196 #define AT_BUFFER_SIZE                  4096
 197
 198 static char ohci_driver_name[] = KBUILD_MODNAME;
 199
 200 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 201 {
 202         writel(data, ohci->registers + offset);
 203 }
 204
 205 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 206 {
 207         return readl(ohci->registers + offset);
 208 }
 209
 210 static inline void flush_writes(const struct fw_ohci *ohci)
 211 {
 212         /* Do a dummy read to flush writes. */
 213         reg_read(ohci, OHCI1394_Version);
 214 }
 215
 216 static int
 217 ohci_update_phy_reg(struct fw_card *card, int addr,
 218                     int clear_bits, int set_bits)
 219 {
 220         struct fw_ohci *ohci = fw_ohci(card);
 221         u32 val, old;
 222
 223         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 224         msleep(2);
 225         val = reg_read(ohci, OHCI1394_PhyControl);
 226         if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
 227                 fw_error("failed to set phy reg bits.\n");
 228                 return -EBUSY;
 229         }
 230
 231         old = OHCI1394_PhyControl_ReadData(val);
 232         old = (old & ~clear_bits) | set_bits;
 233         reg_write(ohci, OHCI1394_PhyControl,
 234                   OHCI1394_PhyControl_Write(addr, old));
 235
 236         return 0;
 237 }
 238
 239 static int ar_context_add_page(struct ar_context *ctx)
 240 {
 241         struct device *dev = ctx->ohci->card.device;
 242         struct ar_buffer *ab;
 243         dma_addr_t ab_bus;
 244         size_t offset;
 245
 246         ab = (struct ar_buffer *) __get_free_page(GFP_ATOMIC);
 247         if (ab == NULL)
 248                 return -ENOMEM;
 249
 250         ab_bus = dma_map_single(dev, ab, PAGE_SIZE, DMA_BIDIRECTIONAL);
 251         if (dma_mapping_error(ab_bus)) {
 252                 free_page((unsigned long) ab);
 253                 return -ENOMEM;
 254         }
 255
 256         memset(&ab->descriptor, 0, sizeof ab->descriptor);
 257         ab->descriptor.control        = cpu_to_le16(descriptor_input_more |
 258                                                     descriptor_status |
 259                                                     descriptor_branch_always);
 260         offset = offsetof(struct ar_buffer, data);
 261         ab->descriptor.req_count      = cpu_to_le16(PAGE_SIZE - offset);
 262         ab->descriptor.data_address   = cpu_to_le32(ab_bus + offset);
 263         ab->descriptor.res_count      = cpu_to_le16(PAGE_SIZE - offset);
 264         ab->descriptor.branch_address = 0;
 265
 266         dma_sync_single_for_device(dev, ab_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
 267
 268         ctx->last_buffer->descriptor.branch_address = ab_bus | 1;
 269         ctx->last_buffer->next = ab;
 270         ctx->last_buffer = ab;
 271
 272         reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE);
 273         flush_writes(ctx->ohci);
 274
 275         return 0;
 276 }
 277
 278 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 279 {
 280         struct fw_ohci *ohci = ctx->ohci;
 281         struct fw_packet p;
 282         u32 status, length, tcode;
 283
 284         p.header[0] = le32_to_cpu(buffer[0]);
 285         p.header[1] = le32_to_cpu(buffer[1]);
 286         p.header[2] = le32_to_cpu(buffer[2]);
 287
 288         tcode = (p.header[0] >> 4) & 0x0f;
 289         switch (tcode) {
 290         case TCODE_WRITE_QUADLET_REQUEST:
 291         case TCODE_READ_QUADLET_RESPONSE:
 292                 p.header[3] = (__force __u32) buffer[3];
 293                 p.header_length = 16;
 294                 p.payload_length = 0;
 295                 break;
 296
 297         case TCODE_READ_BLOCK_REQUEST :
 298                 p.header[3] = le32_to_cpu(buffer[3]);
 299                 p.header_length = 16;
 300                 p.payload_length = 0;
 301                 break;
 302
 303         case TCODE_WRITE_BLOCK_REQUEST:
 304         case TCODE_READ_BLOCK_RESPONSE:
 305         case TCODE_LOCK_REQUEST:
 306         case TCODE_LOCK_RESPONSE:
 307                 p.header[3] = le32_to_cpu(buffer[3]);
 308                 p.header_length = 16;
 309                 p.payload_length = p.header[3] >> 16;
 310                 break;
 311
 312         case TCODE_WRITE_RESPONSE:
 313         case TCODE_READ_QUADLET_REQUEST:
 314         case OHCI_TCODE_PHY_PACKET:
 315                 p.header_length = 12;
 316                 p.payload_length = 0;
 317                 break;
 318         }
 319
 320         p.payload = (void *) buffer + p.header_length;
 321
 322         /* FIXME: What to do about evt_* errors? */
 323         length = (p.header_length + p.payload_length + 3) / 4;
 324         status = le32_to_cpu(buffer[length]);
 325
 326         p.ack        = ((status >> 16) & 0x1f) - 16;
 327         p.speed      = (status >> 21) & 0x7;
 328         p.timestamp  = status & 0xffff;
 329         p.generation = ohci->request_generation;
 330
 331         /* The OHCI bus reset handler synthesizes a phy packet with
 332          * the new generation number when a bus reset happens (see
 333          * section 8.4.2.3).  This helps us determine when a request
 334          * was received and make sure we send the response in the same
 335          * generation.  We only need this for requests; for responses
 336          * we use the unique tlabel for finding the matching
 337          * request. */
 338
 339         if (p.ack + 16 == 0x09)
 340                 ohci->request_generation = (buffer[2] >> 16) & 0xff;
 341         else if (ctx == &ohci->ar_request_ctx)
 342                 fw_core_handle_request(&ohci->card, &p);
 343         else
 344                 fw_core_handle_response(&ohci->card, &p);
 345
 346         return buffer + length + 1;
 347 }
 348
 349 static void ar_context_tasklet(unsigned long data)
 350 {
 351         struct ar_context *ctx = (struct ar_context *)data;
 352         struct fw_ohci *ohci = ctx->ohci;
 353         struct ar_buffer *ab;
 354         struct descriptor *d;
 355         void *buffer, *end;
 356
 357         ab = ctx->current_buffer;
 358         d = &ab->descriptor;
 359
 360         if (d->res_count == 0) {
 361                 size_t size, rest, offset;
 362
 363                 /* This descriptor is finished and we may have a
 364                  * packet split across this and the next buffer. We
 365                  * reuse the page for reassembling the split packet. */
 366
 367                 offset = offsetof(struct ar_buffer, data);
 368                 dma_unmap_single(ohci->card.device,
 369                                  ab->descriptor.data_address - offset,
 370                                  PAGE_SIZE, DMA_BIDIRECTIONAL);
 371
 372                 buffer = ab;
 373                 ab = ab->next;
 374                 d = &ab->descriptor;
 375                 size = buffer + PAGE_SIZE - ctx->pointer;
 376                 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
 377                 memmove(buffer, ctx->pointer, size);
 378                 memcpy(buffer + size, ab->data, rest);
 379                 ctx->current_buffer = ab;
 380                 ctx->pointer = (void *) ab->data + rest;
 381                 end = buffer + size + rest;
 382
 383                 while (buffer < end)
 384                         buffer = handle_ar_packet(ctx, buffer);
 385
 386                 free_page((unsigned long)buffer);
 387                 ar_context_add_page(ctx);
 388         } else {
 389                 buffer = ctx->pointer;
 390                 ctx->pointer = end =
 391                         (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
 392
 393                 while (buffer < end)
 394                         buffer = handle_ar_packet(ctx, buffer);
 395         }
 396 }
 397
 398 static int
 399 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
 400 {
 401         struct ar_buffer ab;
 402
 403         ctx->regs        = regs;
 404         ctx->ohci        = ohci;
 405         ctx->last_buffer = &ab;
 406         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 407
 408         ar_context_add_page(ctx);
 409         ar_context_add_page(ctx);
 410         ctx->current_buffer = ab.next;
 411         ctx->pointer = ctx->current_buffer->data;
 412
 413         reg_write(ctx->ohci, command_ptr(ctx->regs), ab.descriptor.branch_address);
 414         reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_RUN);
 415         flush_writes(ctx->ohci);
 416
 417         return 0;
 418 }
 419
 420 static void context_tasklet(unsigned long data)
 421 {
 422         struct context *ctx = (struct context *) data;
 423         struct fw_ohci *ohci = ctx->ohci;
 424         struct descriptor *d, *last;
 425         u32 address;
 426         int z;
 427
 428         dma_sync_single_for_cpu(ohci->card.device, ctx->buffer_bus,
 429                                 ctx->buffer_size, DMA_TO_DEVICE);
 430
 431         d    = ctx->tail_descriptor;
 432         last = ctx->tail_descriptor_last;
 433
 434         while (last->branch_address != 0) {
 435                 address = le32_to_cpu(last->branch_address);
 436                 z = address & 0xf;
 437                 d = ctx->buffer + (address - ctx->buffer_bus) / sizeof *d;
 438                 last = (z == 2) ? d : d + z - 1;
 439
 440                 if (!ctx->callback(ctx, d, last))
 441                         break;
 442
 443                 ctx->tail_descriptor      = d;
 444                 ctx->tail_descriptor_last = last;
 445         }
 446 }
 447
 448 static int
 449 context_init(struct context *ctx, struct fw_ohci *ohci,
 450              size_t buffer_size, u32 regs,
 451              descriptor_callback_t callback)
 452 {
 453         ctx->ohci = ohci;
 454         ctx->regs = regs;
 455         ctx->buffer_size = buffer_size;
 456         ctx->buffer = kmalloc(buffer_size, GFP_KERNEL);
 457         if (ctx->buffer == NULL)
 458                 return -ENOMEM;
 459
 460         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
 461         ctx->callback = callback;
 462
 463         ctx->buffer_bus =
 464                 dma_map_single(ohci->card.device, ctx->buffer,
 465                                buffer_size, DMA_TO_DEVICE);
 466         if (dma_mapping_error(ctx->buffer_bus)) {
 467                 kfree(ctx->buffer);
 468                 return -ENOMEM;
 469         }
 470
 471         ctx->head_descriptor      = ctx->buffer;
 472         ctx->prev_descriptor      = ctx->buffer;
 473         ctx->tail_descriptor      = ctx->buffer;
 474         ctx->tail_descriptor_last = ctx->buffer;
 475
 476         /* We put a dummy descriptor in the buffer that has a NULL
 477          * branch address and looks like it's been sent.  That way we
 478          * have a descriptor to append DMA programs to.  Also, the
 479          * ring buffer invariant is that it always has at least one
 480          * element so that head == tail means buffer full. */
 481
 482         memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor);
 483         ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last);
 484         ctx->head_descriptor->transfer_status = cpu_to_le16(0x8011);
 485         ctx->head_descriptor++;
 486
 487         return 0;
 488 }
 489
 490 static void
 491 context_release(struct context *ctx)
 492 {
 493         struct fw_card *card = &ctx->ohci->card;
 494
 495         dma_unmap_single(card->device, ctx->buffer_bus,
 496                          ctx->buffer_size, DMA_TO_DEVICE);
 497         kfree(ctx->buffer);
 498 }
 499
 500 static struct descriptor *
 501 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
 502 {
 503         struct descriptor *d, *tail, *end;
 504
 505         d = ctx->head_descriptor;
 506         tail = ctx->tail_descriptor;
 507         end = ctx->buffer + ctx->buffer_size / sizeof(struct descriptor);
 508
 509         if (d + z <= tail) {
 510                 goto has_space;
 511         } else if (d > tail && d + z <= end) {
 512                 goto has_space;
 513         } else if (d > tail && ctx->buffer + z <= tail) {
 514                 d = ctx->buffer;
 515                 goto has_space;
 516         }
 517
 518         return NULL;
 519
 520  has_space:
 521         memset(d, 0, z * sizeof *d);
 522         *d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
 523
 524         return d;
 525 }
 526
 527 static void context_run(struct context *ctx, u32 extra)
 528 {
 529         struct fw_ohci *ohci = ctx->ohci;
 530
 531         reg_write(ohci, command_ptr(ctx->regs),
 532                   le32_to_cpu(ctx->tail_descriptor_last->branch_address));
 533         reg_write(ohci, control_clear(ctx->regs), ~0);
 534         reg_write(ohci, control_set(ctx->regs), CONTEXT_RUN | extra);
 535         flush_writes(ohci);
 536 }
 537
 538 static void context_append(struct context *ctx,
 539                            struct descriptor *d, int z, int extra)
 540 {
 541         dma_addr_t d_bus;
 542
 543         d_bus = ctx->buffer_bus + (d - ctx->buffer) * sizeof *d;
 544
 545         ctx->head_descriptor = d + z + extra;
 546         ctx->prev_descriptor->branch_address = cpu_to_le32(d_bus | z);
 547         ctx->prev_descriptor = z == 2 ? d : d + z - 1;
 548
 549         dma_sync_single_for_device(ctx->ohci->card.device, ctx->buffer_bus,
 550                                    ctx->buffer_size, DMA_TO_DEVICE);
 551
 552         reg_write(ctx->ohci, control_set(ctx->regs), CONTEXT_WAKE);
 553         flush_writes(ctx->ohci);
 554 }
 555
 556 static void context_stop(struct context *ctx)
 557 {
 558         u32 reg;
 559         int i;
 560
 561         reg_write(ctx->ohci, control_clear(ctx->regs), CONTEXT_RUN);
 562         flush_writes(ctx->ohci);
 563
 564         for (i = 0; i < 10; i++) {
 565                 reg = reg_read(ctx->ohci, control_set(ctx->regs));
 566                 if ((reg & CONTEXT_ACTIVE) == 0)
 567                         break;
 568
 569                 fw_notify("context_stop: still active (0x%08x)\n", reg);
 570                 msleep(1);
 571         }
 572 }
 573
 574 struct driver_data {
 575         struct fw_packet *packet;
 576 };
 577
 578 /* This function apppends a packet to the DMA queue for transmission.
 579  * Must always be called with the ochi->lock held to ensure proper
 580  * generation handling and locking around packet queue manipulation. */
 581 static int
 582 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
 583 {
 584         struct fw_ohci *ohci = ctx->ohci;
 585         dma_addr_t d_bus, payload_bus;
 586         struct driver_data *driver_data;
 587         struct descriptor *d, *last;
 588         __le32 *header;
 589         int z, tcode;
 590         u32 reg;
 591
 592         d = context_get_descriptors(ctx, 4, &d_bus);
 593         if (d == NULL) {
 594                 packet->ack = RCODE_SEND_ERROR;
 595                 return -1;
 596         }
 597
 598         d[0].control   = cpu_to_le16(descriptor_key_immediate);
 599         d[0].res_count = cpu_to_le16(packet->timestamp);
 600
 601         /* The DMA format for asyncronous link packets is different
 602          * from the IEEE1394 layout, so shift the fields around
 603          * accordingly.  If header_length is 8, it's a PHY packet, to
 604          * which we need to prepend an extra quadlet. */
 605
 606         header = (__le32 *) &d[1];
 607         if (packet->header_length > 8) {
 608                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
 609                                         (packet->speed << 16));
 610                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
 611                                         (packet->header[0] & 0xffff0000));
 612                 header[2] = cpu_to_le32(packet->header[2]);
 613
 614                 tcode = (packet->header[0] >> 4) & 0x0f;
 615                 if (TCODE_IS_BLOCK_PACKET(tcode))
 616                         header[3] = cpu_to_le32(packet->header[3]);
 617                 else
 618                         header[3] = (__force __le32) packet->header[3];
 619
 620                 d[0].req_count = cpu_to_le16(packet->header_length);
 621         } else {
 622                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
 623                                         (packet->speed << 16));
 624                 header[1] = cpu_to_le32(packet->header[0]);
 625                 header[2] = cpu_to_le32(packet->header[1]);
 626                 d[0].req_count = cpu_to_le16(12);
 627         }
 628
 629         driver_data = (struct driver_data *) &d[3];
 630         driver_data->packet = packet;
 631
 632         if (packet->payload_length > 0) {
 633                 payload_bus =
 634                         dma_map_single(ohci->card.device, packet->payload,
 635                                        packet->payload_length, DMA_TO_DEVICE);
 636                 if (dma_mapping_error(payload_bus)) {
 637                         packet->ack = RCODE_SEND_ERROR;
 638                         return -1;
 639                 }
 640
 641                 d[2].req_count    = cpu_to_le16(packet->payload_length);
 642                 d[2].data_address = cpu_to_le32(payload_bus);
 643                 last = &d[2];
 644                 z = 3;
 645         } else {
 646                 last = &d[0];
 647                 z = 2;
 648         }
 649
 650         last->control |= cpu_to_le16(descriptor_output_last |
 651                                      descriptor_irq_always |
 652                                      descriptor_branch_always);
 653
 654         /* FIXME: Document how the locking works. */
 655         if (ohci->generation != packet->generation) {
 656                 packet->ack = RCODE_GENERATION;
 657                 return -1;
 658         }
 659
 660         context_append(ctx, d, z, 4 - z);
 661
 662         /* If the context isn't already running, start it up. */
 663         reg = reg_read(ctx->ohci, control_set(ctx->regs));
 664         if ((reg & CONTEXT_ACTIVE) == 0)
 665                 context_run(ctx, 0);
 666
 667         return 0;
 668 }
 669
 670 static int handle_at_packet(struct context *context,
 671                             struct descriptor *d,
 672                             struct descriptor *last)
 673 {
 674         struct driver_data *driver_data;
 675         struct fw_packet *packet;
 676         struct fw_ohci *ohci = context->ohci;
 677         dma_addr_t payload_bus;
 678         int evt;
 679
 680         if (last->transfer_status == 0)
 681                 /* This descriptor isn't done yet, stop iteration. */
 682                 return 0;
 683
 684         driver_data = (struct driver_data *) &d[3];
 685         packet = driver_data->packet;
 686         if (packet == NULL)
 687                 /* This packet was cancelled, just continue. */
 688                 return 1;
 689
 690         payload_bus = le32_to_cpu(last->data_address);
 691         if (payload_bus != 0)
 692                 dma_unmap_single(ohci->card.device, payload_bus,
 693                                  packet->payload_length, DMA_TO_DEVICE);
 694
 695         evt = le16_to_cpu(last->transfer_status) & 0x1f;
 696         packet->timestamp = le16_to_cpu(last->res_count);
 697
 698         switch (evt) {
 699         case OHCI1394_evt_timeout:
 700                 /* Async response transmit timed out. */
 701                 packet->ack = RCODE_CANCELLED;
 702                 break;
 703
 704         case OHCI1394_evt_flushed:
 705                 /* The packet was flushed should give same error as
 706                  * when we try to use a stale generation count. */
 707                 packet->ack = RCODE_GENERATION;
 708                 break;
 709
 710         case OHCI1394_evt_missing_ack:
 711                 /* Using a valid (current) generation count, but the
 712                  * node is not on the bus or not sending acks. */
 713                 packet->ack = RCODE_NO_ACK;
 714                 break;
 715
 716         case ACK_COMPLETE + 0x10:
 717         case ACK_PENDING + 0x10:
 718         case ACK_BUSY_X + 0x10:
 719         case ACK_BUSY_A + 0x10:
 720         case ACK_BUSY_B + 0x10:
 721         case ACK_DATA_ERROR + 0x10:
 722         case ACK_TYPE_ERROR + 0x10:
 723                 packet->ack = evt - 0x10;
 724                 break;
 725
 726         default:
 727                 packet->ack = RCODE_SEND_ERROR;
 728                 break;
 729         }
 730
 731         packet->callback(packet, &ohci->card, packet->ack);
 732
 733         return 1;
 734 }
 735
 736 #define header_get_destination(q)       (((q) >> 16) & 0xffff)
 737 #define header_get_tcode(q)             (((q) >> 4) & 0x0f)
 738 #define header_get_offset_high(q)       (((q) >> 0) & 0xffff)
 739 #define header_get_data_length(q)       (((q) >> 16) & 0xffff)
 740 #define header_get_extended_tcode(q)    (((q) >> 0) & 0xffff)
 741
 742 static void
 743 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
 744 {
 745         struct fw_packet response;
 746         int tcode, length, i;
 747
 748         tcode = header_get_tcode(packet->header[0]);
 749         if (TCODE_IS_BLOCK_PACKET(tcode))
 750                 length = header_get_data_length(packet->header[3]);
 751         else
 752                 length = 4;
 753
 754         i = csr - CSR_CONFIG_ROM;
 755         if (i + length > CONFIG_ROM_SIZE) {
 756                 fw_fill_response(&response, packet->header,
 757                                  RCODE_ADDRESS_ERROR, NULL, 0);
 758         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
 759                 fw_fill_response(&response, packet->header,
 760                                  RCODE_TYPE_ERROR, NULL, 0);
 761         } else {
 762                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
 763                                  (void *) ohci->config_rom + i, length);
 764         }
 765
 766         fw_core_handle_response(&ohci->card, &response);
 767 }
 768
 769 static void
 770 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
 771 {
 772         struct fw_packet response;
 773         int tcode, length, ext_tcode, sel;
 774         __be32 *payload, lock_old;
 775         u32 lock_arg, lock_data;
 776
 777         tcode = header_get_tcode(packet->header[0]);
 778         length = header_get_data_length(packet->header[3]);
 779         payload = packet->payload;
 780         ext_tcode = header_get_extended_tcode(packet->header[3]);
 781
 782         if (tcode == TCODE_LOCK_REQUEST &&
 783             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
 784                 lock_arg = be32_to_cpu(payload[0]);
 785                 lock_data = be32_to_cpu(payload[1]);
 786         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
 787                 lock_arg = 0;
 788                 lock_data = 0;
 789         } else {
 790                 fw_fill_response(&response, packet->header,
 791                                  RCODE_TYPE_ERROR, NULL, 0);
 792                 goto out;
 793         }
 794
 795         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
 796         reg_write(ohci, OHCI1394_CSRData, lock_data);
 797         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
 798         reg_write(ohci, OHCI1394_CSRControl, sel);
 799
 800         if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
 801                 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
 802         else
 803                 fw_notify("swap not done yet\n");
 804
 805         fw_fill_response(&response, packet->header,
 806                          RCODE_COMPLETE, &lock_old, sizeof lock_old);
 807  out:
 808         fw_core_handle_response(&ohci->card, &response);
 809 }
 810
 811 static void
 812 handle_local_request(struct context *ctx, struct fw_packet *packet)
 813 {
 814         u64 offset;
 815         u32 csr;
 816
 817         if (ctx == &ctx->ohci->at_request_ctx) {
 818                 packet->ack = ACK_PENDING;
 819                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 820         }
 821
 822         offset =
 823                 ((unsigned long long)
 824                  header_get_offset_high(packet->header[1]) << 32) |
 825                 packet->header[2];
 826         csr = offset - CSR_REGISTER_BASE;
 827
 828         /* Handle config rom reads. */
 829         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
 830                 handle_local_rom(ctx->ohci, packet, csr);
 831         else switch (csr) {
 832         case CSR_BUS_MANAGER_ID:
 833         case CSR_BANDWIDTH_AVAILABLE:
 834         case CSR_CHANNELS_AVAILABLE_HI:
 835         case CSR_CHANNELS_AVAILABLE_LO:
 836                 handle_local_lock(ctx->ohci, packet, csr);
 837                 break;
 838         default:
 839                 if (ctx == &ctx->ohci->at_request_ctx)
 840                         fw_core_handle_request(&ctx->ohci->card, packet);
 841                 else
 842                         fw_core_handle_response(&ctx->ohci->card, packet);
 843                 break;
 844         }
 845
 846         if (ctx == &ctx->ohci->at_response_ctx) {
 847                 packet->ack = ACK_COMPLETE;
 848                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 849         }
 850 }
 851
 852 static void
 853 at_context_transmit(struct context *ctx, struct fw_packet *packet)
 854 {
 855         unsigned long flags;
 856         int retval;
 857
 858         spin_lock_irqsave(&ctx->ohci->lock, flags);
 859
 860         if (header_get_destination(packet->header[0]) == ctx->ohci->node_id &&
 861             ctx->ohci->generation == packet->generation) {
 862                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 863                 handle_local_request(ctx, packet);
 864                 return;
 865         }
 866
 867         retval = at_context_queue_packet(ctx, packet);
 868         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
 869
 870         if (retval < 0)
 871                 packet->callback(packet, &ctx->ohci->card, packet->ack);
 872
 873 }
 874
 875 static void bus_reset_tasklet(unsigned long data)
 876 {
 877         struct fw_ohci *ohci = (struct fw_ohci *)data;
 878         int self_id_count, i, j, reg;
 879         int generation, new_generation;
 880         unsigned long flags;
 881
 882         reg = reg_read(ohci, OHCI1394_NodeID);
 883         if (!(reg & OHCI1394_NodeID_idValid)) {
 884                 fw_error("node ID not valid, new bus reset in progress\n");
 885                 return;
 886         }
 887         ohci->node_id = reg & 0xffff;
 888
 889         /* The count in the SelfIDCount register is the number of
 890          * bytes in the self ID receive buffer.  Since we also receive
 891          * the inverted quadlets and a header quadlet, we shift one
 892          * bit extra to get the actual number of self IDs. */
 893
 894         self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
 895         generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
 896
 897         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
 898                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1])
 899                         fw_error("inconsistent self IDs\n");
 900                 ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
 901         }
 902
 903         /* Check the consistency of the self IDs we just read.  The
 904          * problem we face is that a new bus reset can start while we
 905          * read out the self IDs from the DMA buffer. If this happens,
 906          * the DMA buffer will be overwritten with new self IDs and we
 907          * will read out inconsistent data.  The OHCI specification
 908          * (section 11.2) recommends a technique similar to
 909          * linux/seqlock.h, where we remember the generation of the
 910          * self IDs in the buffer before reading them out and compare
 911          * it to the current generation after reading them out.  If
 912          * the two generations match we know we have a consistent set
 913          * of self IDs. */
 914
 915         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
 916         if (new_generation != generation) {
 917                 fw_notify("recursive bus reset detected, "
 918                           "discarding self ids\n");
 919                 return;
 920         }
 921
 922         /* FIXME: Document how the locking works. */
 923         spin_lock_irqsave(&ohci->lock, flags);
 924
 925         ohci->generation = generation;
 926         context_stop(&ohci->at_request_ctx);
 927         context_stop(&ohci->at_response_ctx);
 928         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
 929
 930         /* This next bit is unrelated to the AT context stuff but we
 931          * have to do it under the spinlock also.  If a new config rom
 932          * was set up before this reset, the old one is now no longer
 933          * in use and we can free it. Update the config rom pointers
 934          * to point to the current config rom and clear the
 935          * next_config_rom pointer so a new udpate can take place. */
 936
 937         if (ohci->next_config_rom != NULL) {
 938                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
 939                                   ohci->config_rom, ohci->config_rom_bus);
 940                 ohci->config_rom      = ohci->next_config_rom;
 941                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
 942                 ohci->next_config_rom = NULL;
 943
 944                 /* Restore config_rom image and manually update
 945                  * config_rom registers.  Writing the header quadlet
 946                  * will indicate that the config rom is ready, so we
 947                  * do that last. */
 948                 reg_write(ohci, OHCI1394_BusOptions,
 949                           be32_to_cpu(ohci->config_rom[2]));
 950                 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
 951                 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
 952         }
 953
 954         spin_unlock_irqrestore(&ohci->lock, flags);
 955
 956         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
 957                                  self_id_count, ohci->self_id_buffer);
 958 }
 959
 960 static irqreturn_t irq_handler(int irq, void *data)
 961 {
 962         struct fw_ohci *ohci = data;
 963         u32 event, iso_event, cycle_time;
 964         int i;
 965
 966         event = reg_read(ohci, OHCI1394_IntEventClear);
 967
 968         if (!event)
 969                 return IRQ_NONE;
 970
 971         reg_write(ohci, OHCI1394_IntEventClear, event);
 972
 973         if (event & OHCI1394_selfIDComplete)
 974                 tasklet_schedule(&ohci->bus_reset_tasklet);
 975
 976         if (event & OHCI1394_RQPkt)
 977                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
 978
 979         if (event & OHCI1394_RSPkt)
 980                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
 981
 982         if (event & OHCI1394_reqTxComplete)
 983                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
 984
 985         if (event & OHCI1394_respTxComplete)
 986                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
 987
 988         iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
 989         reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
 990
 991         while (iso_event) {
 992                 i = ffs(iso_event) - 1;
 993                 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
 994                 iso_event &= ~(1 << i);
 995         }
 996
 997         iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
 998         reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
 999
1000         while (iso_event) {
1001                 i = ffs(iso_event) - 1;
1002                 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1003                 iso_event &= ~(1 << i);
1004         }
1005
1006         if (event & OHCI1394_cycle64Seconds) {
1007                 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1008                 if ((cycle_time & 0x80000000) == 0)
1009                         ohci->bus_seconds++;
1010         }
1011
1012         return IRQ_HANDLED;
1013 }
1014
1015 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1016 {
1017         struct fw_ohci *ohci = fw_ohci(card);
1018         struct pci_dev *dev = to_pci_dev(card->device);
1019
1020         /* When the link is not yet enabled, the atomic config rom
1021          * update mechanism described below in ohci_set_config_rom()
1022          * is not active.  We have to update ConfigRomHeader and
1023          * BusOptions manually, and the write to ConfigROMmap takes
1024          * effect immediately.  We tie this to the enabling of the
1025          * link, so we have a valid config rom before enabling - the
1026          * OHCI requires that ConfigROMhdr and BusOptions have valid
1027          * values before enabling.
1028          *
1029          * However, when the ConfigROMmap is written, some controllers
1030          * always read back quadlets 0 and 2 from the config rom to
1031          * the ConfigRomHeader and BusOptions registers on bus reset.
1032          * They shouldn't do that in this initial case where the link
1033          * isn't enabled.  This means we have to use the same
1034          * workaround here, setting the bus header to 0 and then write
1035          * the right values in the bus reset tasklet.
1036          */
1037
1038         ohci->next_config_rom =
1039                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1040                                    &ohci->next_config_rom_bus, GFP_KERNEL);
1041         if (ohci->next_config_rom == NULL)
1042                 return -ENOMEM;
1043
1044         memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1045         fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1046
1047         ohci->next_header = config_rom[0];
1048         ohci->next_config_rom[0] = 0;
1049         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1050         reg_write(ohci, OHCI1394_BusOptions, config_rom[2]);
1051         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1052
1053         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1054
1055         if (request_irq(dev->irq, irq_handler,
1056                         IRQF_SHARED, ohci_driver_name, ohci)) {
1057                 fw_error("Failed to allocate shared interrupt %d.\n",
1058                          dev->irq);
1059                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1060                                   ohci->config_rom, ohci->config_rom_bus);
1061                 return -EIO;
1062         }
1063
1064         reg_write(ohci, OHCI1394_HCControlSet,
1065                   OHCI1394_HCControl_linkEnable |
1066                   OHCI1394_HCControl_BIBimageValid);
1067         flush_writes(ohci);
1068
1069         /* We are ready to go, initiate bus reset to finish the
1070          * initialization. */
1071
1072         fw_core_initiate_bus_reset(&ohci->card, 1);
1073
1074         return 0;
1075 }
1076
1077 static int
1078 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1079 {
1080         struct fw_ohci *ohci;
1081         unsigned long flags;
1082         int retval = 0;
1083         __be32 *next_config_rom;
1084         dma_addr_t next_config_rom_bus;
1085
1086         ohci = fw_ohci(card);
1087
1088         /* When the OHCI controller is enabled, the config rom update
1089          * mechanism is a bit tricky, but easy enough to use.  See
1090          * section 5.5.6 in the OHCI specification.
1091          *
1092          * The OHCI controller caches the new config rom address in a
1093          * shadow register (ConfigROMmapNext) and needs a bus reset
1094          * for the changes to take place.  When the bus reset is
1095          * detected, the controller loads the new values for the
1096          * ConfigRomHeader and BusOptions registers from the specified
1097          * config rom and loads ConfigROMmap from the ConfigROMmapNext
1098          * shadow register. All automatically and atomically.
1099          *
1100          * Now, there's a twist to this story.  The automatic load of
1101          * ConfigRomHeader and BusOptions doesn't honor the
1102          * noByteSwapData bit, so with a be32 config rom, the
1103          * controller will load be32 values in to these registers
1104          * during the atomic update, even on litte endian
1105          * architectures.  The workaround we use is to put a 0 in the
1106          * header quadlet; 0 is endian agnostic and means that the
1107          * config rom isn't ready yet.  In the bus reset tasklet we
1108          * then set up the real values for the two registers.
1109          *
1110          * We use ohci->lock to avoid racing with the code that sets
1111          * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1112          */
1113
1114         next_config_rom =
1115                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1116                                    &next_config_rom_bus, GFP_KERNEL);
1117         if (next_config_rom == NULL)
1118                 return -ENOMEM;
1119
1120         spin_lock_irqsave(&ohci->lock, flags);
1121
1122         if (ohci->next_config_rom == NULL) {
1123                 ohci->next_config_rom = next_config_rom;
1124                 ohci->next_config_rom_bus = next_config_rom_bus;
1125
1126                 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1127                 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1128                                   length * 4);
1129
1130                 ohci->next_header = config_rom[0];
1131                 ohci->next_config_rom[0] = 0;
1132
1133                 reg_write(ohci, OHCI1394_ConfigROMmap,
1134                           ohci->next_config_rom_bus);
1135         } else {
1136                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1137                                   next_config_rom, next_config_rom_bus);
1138                 retval = -EBUSY;
1139         }
1140
1141         spin_unlock_irqrestore(&ohci->lock, flags);
1142
1143         /* Now initiate a bus reset to have the changes take
1144          * effect. We clean up the old config rom memory and DMA
1145          * mappings in the bus reset tasklet, since the OHCI
1146          * controller could need to access it before the bus reset
1147          * takes effect. */
1148         if (retval == 0)
1149                 fw_core_initiate_bus_reset(&ohci->card, 1);
1150
1151         return retval;
1152 }
1153
1154 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1155 {
1156         struct fw_ohci *ohci = fw_ohci(card);
1157
1158         at_context_transmit(&ohci->at_request_ctx, packet);
1159 }
1160
1161 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1162 {
1163         struct fw_ohci *ohci = fw_ohci(card);
1164
1165         at_context_transmit(&ohci->at_response_ctx, packet);
1166 }
1167
1168 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1169 {
1170         struct fw_ohci *ohci = fw_ohci(card);
1171         struct context *ctx = &ohci->at_request_ctx;
1172         struct driver_data *driver_data = packet->driver_data;
1173         int retval = -ENOENT;
1174
1175         tasklet_disable(&ctx->tasklet);
1176
1177         if (packet->ack != 0)
1178                 goto out;
1179
1180         driver_data->packet = NULL;
1181         packet->ack = RCODE_CANCELLED;
1182         packet->callback(packet, &ohci->card, packet->ack);
1183         retval = 0;
1184
1185  out:
1186         tasklet_enable(&ctx->tasklet);
1187
1188         return retval;
1189 }
1190
1191 static int
1192 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1193 {
1194         struct fw_ohci *ohci = fw_ohci(card);
1195         unsigned long flags;
1196         int n, retval = 0;
1197
1198         /* FIXME:  Make sure this bitmask is cleared when we clear the busReset
1199          * interrupt bit.  Clear physReqResourceAllBuses on bus reset. */
1200
1201         spin_lock_irqsave(&ohci->lock, flags);
1202
1203         if (ohci->generation != generation) {
1204                 retval = -ESTALE;
1205                 goto out;
1206         }
1207
1208         /* NOTE, if the node ID contains a non-local bus ID, physical DMA is
1209          * enabled for _all_ nodes on remote buses. */
1210
1211         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1212         if (n < 32)
1213                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1214         else
1215                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1216
1217         flush_writes(ohci);
1218  out:
1219         spin_unlock_irqrestore(&ohci->lock, flags);
1220         return retval;
1221 }
1222
1223 static u64
1224 ohci_get_bus_time(struct fw_card *card)
1225 {
1226         struct fw_ohci *ohci = fw_ohci(card);
1227         u32 cycle_time;
1228         u64 bus_time;
1229
1230         cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1231         bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1232
1233         return bus_time;
1234 }
1235
1236 static int handle_ir_dualbuffer_packet(struct context *context,
1237                                        struct descriptor *d,
1238                                        struct descriptor *last)
1239 {
1240         struct iso_context *ctx =
1241                 container_of(context, struct iso_context, context);
1242         struct db_descriptor *db = (struct db_descriptor *) d;
1243         __le32 *ir_header;
1244         size_t header_length;
1245         void *p, *end;
1246         int i;
1247
1248         if (db->first_res_count > 0 && db->second_res_count > 0)
1249                 /* This descriptor isn't done yet, stop iteration. */
1250                 return 0;
1251
1252         header_length = le16_to_cpu(db->first_req_count) -
1253                 le16_to_cpu(db->first_res_count);
1254
1255         i = ctx->header_length;
1256         p = db + 1;
1257         end = p + header_length;
1258         while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1259                 memcpy(ctx->header + i, p + 4, ctx->base.header_size);
1260                 i += ctx->base.header_size;
1261                 p += ctx->base.header_size + 4;
1262         }
1263
1264         ctx->header_length = i;
1265
1266         if (le16_to_cpu(db->control) & descriptor_irq_always) {
1267                 ir_header = (__le32 *) (db + 1);
1268                 ctx->base.callback(&ctx->base,
1269                                    le32_to_cpu(ir_header[0]) & 0xffff,
1270                                    ctx->header_length, ctx->header,
1271                                    ctx->base.callback_data);
1272                 ctx->header_length = 0;
1273         }
1274
1275         return 1;
1276 }
1277
1278 static int handle_it_packet(struct context *context,
1279                             struct descriptor *d,
1280                             struct descriptor *last)
1281 {
1282         struct iso_context *ctx =
1283                 container_of(context, struct iso_context, context);
1284
1285         if (last->transfer_status == 0)
1286                 /* This descriptor isn't done yet, stop iteration. */
1287                 return 0;
1288
1289         if (le16_to_cpu(last->control) & descriptor_irq_always)
1290                 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1291                                    0, NULL, ctx->base.callback_data);
1292
1293         return 1;
1294 }
1295
1296 static struct fw_iso_context *
1297 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1298 {
1299         struct fw_ohci *ohci = fw_ohci(card);
1300         struct iso_context *ctx, *list;
1301         descriptor_callback_t callback;
1302         u32 *mask, regs;
1303         unsigned long flags;
1304         int index, retval = -ENOMEM;
1305
1306         if (type == FW_ISO_CONTEXT_TRANSMIT) {
1307                 mask = &ohci->it_context_mask;
1308                 list = ohci->it_context_list;
1309                 callback = handle_it_packet;
1310         } else {
1311                 mask = &ohci->ir_context_mask;
1312                 list = ohci->ir_context_list;
1313                 callback = handle_ir_dualbuffer_packet;
1314         }
1315
1316         /* FIXME: We need a fallback for pre 1.1 OHCI. */
1317         if (callback == handle_ir_dualbuffer_packet &&
1318             ohci->version < OHCI_VERSION_1_1)
1319                 return ERR_PTR(-EINVAL);
1320
1321         spin_lock_irqsave(&ohci->lock, flags);
1322         index = ffs(*mask) - 1;
1323         if (index >= 0)
1324                 *mask &= ~(1 << index);
1325         spin_unlock_irqrestore(&ohci->lock, flags);
1326
1327         if (index < 0)
1328                 return ERR_PTR(-EBUSY);
1329
1330         if (type == FW_ISO_CONTEXT_TRANSMIT)
1331                 regs = OHCI1394_IsoXmitContextBase(index);
1332         else
1333                 regs = OHCI1394_IsoRcvContextBase(index);
1334
1335         ctx = &list[index];
1336         memset(ctx, 0, sizeof *ctx);
1337         ctx->header_length = 0;
1338         ctx->header = (void *) __get_free_page(GFP_KERNEL);
1339         if (ctx->header == NULL)
1340                 goto out;
1341
1342         retval = context_init(&ctx->context, ohci, ISO_BUFFER_SIZE,
1343                               regs, callback);
1344         if (retval < 0)
1345                 goto out_with_header;
1346
1347         return &ctx->base;
1348
1349  out_with_header:
1350         free_page((unsigned long)ctx->header);
1351  out:
1352         spin_lock_irqsave(&ohci->lock, flags);
1353         *mask |= 1 << index;
1354         spin_unlock_irqrestore(&ohci->lock, flags);
1355
1356         return ERR_PTR(retval);
1357 }
1358
1359 static int ohci_start_iso(struct fw_iso_context *base,
1360                           s32 cycle, u32 sync, u32 tags)
1361 {
1362         struct iso_context *ctx = container_of(base, struct iso_context, base);
1363         struct fw_ohci *ohci = ctx->context.ohci;
1364         u32 cycle_match = 0;
1365         int index;
1366
1367         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1368                 index = ctx - ohci->it_context_list;
1369                 if (cycle > 0)
1370                         cycle_match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1371                                 (cycle & 0x7fff) << 16;
1372
1373                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1374                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1375                 context_run(&ctx->context, cycle_match);
1376         } else {
1377                 index = ctx - ohci->ir_context_list;
1378
1379                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1380                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1381                 reg_write(ohci, context_match(ctx->context.regs),
1382                           (tags << 28) | (sync << 8) | ctx->base.channel);
1383                 context_run(&ctx->context,
1384                             IR_CONTEXT_DUAL_BUFFER_MODE |
1385                             IR_CONTEXT_ISOCH_HEADER);
1386         }
1387
1388         return 0;
1389 }
1390
1391 static int ohci_stop_iso(struct fw_iso_context *base)
1392 {
1393         struct fw_ohci *ohci = fw_ohci(base->card);
1394         struct iso_context *ctx = container_of(base, struct iso_context, base);
1395         int index;
1396
1397         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1398                 index = ctx - ohci->it_context_list;
1399                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1400         } else {
1401                 index = ctx - ohci->ir_context_list;
1402                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1403         }
1404         flush_writes(ohci);
1405         context_stop(&ctx->context);
1406
1407         return 0;
1408 }
1409
1410 static void ohci_free_iso_context(struct fw_iso_context *base)
1411 {
1412         struct fw_ohci *ohci = fw_ohci(base->card);
1413         struct iso_context *ctx = container_of(base, struct iso_context, base);
1414         unsigned long flags;
1415         int index;
1416
1417         ohci_stop_iso(base);
1418         context_release(&ctx->context);
1419         free_page((unsigned long)ctx->header);
1420
1421         spin_lock_irqsave(&ohci->lock, flags);
1422
1423         if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1424                 index = ctx - ohci->it_context_list;
1425                 ohci->it_context_mask |= 1 << index;
1426         } else {
1427                 index = ctx - ohci->ir_context_list;
1428                 ohci->ir_context_mask |= 1 << index;
1429         }
1430
1431         spin_unlock_irqrestore(&ohci->lock, flags);
1432 }
1433
1434 static int
1435 ohci_queue_iso_transmit(struct fw_iso_context *base,
1436                         struct fw_iso_packet *packet,
1437                         struct fw_iso_buffer *buffer,
1438                         unsigned long payload)
1439 {
1440         struct iso_context *ctx = container_of(base, struct iso_context, base);
1441         struct descriptor *d, *last, *pd;
1442         struct fw_iso_packet *p;
1443         __le32 *header;
1444         dma_addr_t d_bus, page_bus;
1445         u32 z, header_z, payload_z, irq;
1446         u32 payload_index, payload_end_index, next_page_index;
1447         int page, end_page, i, length, offset;
1448
1449         /* FIXME: Cycle lost behavior should be configurable: lose
1450          * packet, retransmit or terminate.. */
1451
1452         p = packet;
1453         payload_index = payload;
1454
1455         if (p->skip)
1456                 z = 1;
1457         else
1458                 z = 2;
1459         if (p->header_length > 0)
1460                 z++;
1461
1462         /* Determine the first page the payload isn't contained in. */
1463         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
1464         if (p->payload_length > 0)
1465                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
1466         else
1467                 payload_z = 0;
1468
1469         z += payload_z;
1470
1471         /* Get header size in number of descriptors. */
1472         header_z = DIV_ROUND_UP(p->header_length, sizeof *d);
1473
1474         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
1475         if (d == NULL)
1476                 return -ENOMEM;
1477
1478         if (!p->skip) {
1479                 d[0].control   = cpu_to_le16(descriptor_key_immediate);
1480                 d[0].req_count = cpu_to_le16(8);
1481
1482                 header = (__le32 *) &d[1];
1483                 header[0] = cpu_to_le32(it_header_sy(p->sy) |
1484                                         it_header_tag(p->tag) |
1485                                         it_header_tcode(TCODE_STREAM_DATA) |
1486                                         it_header_channel(ctx->base.channel) |
1487                                         it_header_speed(ctx->base.speed));
1488                 header[1] =
1489                         cpu_to_le32(it_header_data_length(p->header_length +
1490                                                           p->payload_length));
1491         }
1492
1493         if (p->header_length > 0) {
1494                 d[2].req_count    = cpu_to_le16(p->header_length);
1495                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof *d);
1496                 memcpy(&d[z], p->header, p->header_length);
1497         }
1498
1499         pd = d + z - payload_z;
1500         payload_end_index = payload_index + p->payload_length;
1501         for (i = 0; i < payload_z; i++) {
1502                 page               = payload_index >> PAGE_SHIFT;
1503                 offset             = payload_index & ~PAGE_MASK;
1504                 next_page_index    = (page + 1) << PAGE_SHIFT;
1505                 length             =
1506                         min(next_page_index, payload_end_index) - payload_index;
1507                 pd[i].req_count    = cpu_to_le16(length);
1508
1509                 page_bus = page_private(buffer->pages[page]);
1510                 pd[i].data_address = cpu_to_le32(page_bus + offset);
1511
1512                 payload_index += length;
1513         }
1514
1515         if (p->interrupt)
1516                 irq = descriptor_irq_always;
1517         else
1518                 irq = descriptor_no_irq;
1519
1520         last = z == 2 ? d : d + z - 1;
1521         last->control |= cpu_to_le16(descriptor_output_last |
1522                                      descriptor_status |
1523                                      descriptor_branch_always |
1524                                      irq);
1525
1526         context_append(&ctx->context, d, z, header_z);
1527
1528         return 0;
1529 }
1530
1531 static int
1532 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
1533                                   struct fw_iso_packet *packet,
1534                                   struct fw_iso_buffer *buffer,
1535                                   unsigned long payload)
1536 {
1537         struct iso_context *ctx = container_of(base, struct iso_context, base);
1538         struct db_descriptor *db = NULL;
1539         struct descriptor *d;
1540         struct fw_iso_packet *p;
1541         dma_addr_t d_bus, page_bus;
1542         u32 z, header_z, length, rest;
1543         int page, offset, packet_count, header_size;
1544
1545         /* FIXME: Cycle lost behavior should be configurable: lose
1546          * packet, retransmit or terminate.. */
1547
1548         if (packet->skip) {
1549                 d = context_get_descriptors(&ctx->context, 2, &d_bus);
1550                 if (d == NULL)
1551                         return -ENOMEM;
1552
1553                 db = (struct db_descriptor *) d;
1554                 db->control = cpu_to_le16(descriptor_status |
1555                                           descriptor_branch_always |
1556                                           descriptor_wait);
1557                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1558                 context_append(&ctx->context, d, 2, 0);
1559         }
1560
1561         p = packet;
1562         z = 2;
1563
1564         /* The OHCI controller puts the status word in the header
1565          * buffer too, so we need 4 extra bytes per packet. */
1566         packet_count = p->header_length / ctx->base.header_size;
1567         header_size = packet_count * (ctx->base.header_size + 4);
1568
1569         /* Get header size in number of descriptors. */
1570         header_z = DIV_ROUND_UP(header_size, sizeof *d);
1571         page     = payload >> PAGE_SHIFT;
1572         offset   = payload & ~PAGE_MASK;
1573         rest     = p->payload_length;
1574
1575         /* FIXME: OHCI 1.0 doesn't support dual buffer receive */
1576         /* FIXME: make packet-per-buffer/dual-buffer a context option */
1577         while (rest > 0) {
1578                 d = context_get_descriptors(&ctx->context,
1579                                             z + header_z, &d_bus);
1580                 if (d == NULL)
1581                         return -ENOMEM;
1582
1583                 db = (struct db_descriptor *) d;
1584                 db->control = cpu_to_le16(descriptor_status |
1585                                           descriptor_branch_always);
1586                 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
1587                 db->first_req_count = cpu_to_le16(header_size);
1588                 db->first_res_count = db->first_req_count;
1589                 db->first_buffer = cpu_to_le32(d_bus + sizeof *db);
1590
1591                 if (offset + rest < PAGE_SIZE)
1592                         length = rest;
1593                 else
1594                         length = PAGE_SIZE - offset;
1595
1596                 db->second_req_count = cpu_to_le16(length);
1597                 db->second_res_count = db->second_req_count;
1598                 page_bus = page_private(buffer->pages[page]);
1599                 db->second_buffer = cpu_to_le32(page_bus + offset);
1600
1601                 if (p->interrupt && length == rest)
1602                         db->control |= cpu_to_le16(descriptor_irq_always);
1603
1604                 context_append(&ctx->context, d, z, header_z);
1605                 offset = (offset + length) & ~PAGE_MASK;
1606                 rest -= length;
1607                 page++;
1608         }
1609
1610         return 0;
1611 }
1612
1613 static int
1614 ohci_queue_iso(struct fw_iso_context *base,
1615                struct fw_iso_packet *packet,
1616                struct fw_iso_buffer *buffer,
1617                unsigned long payload)
1618 {
1619         struct iso_context *ctx = container_of(base, struct iso_context, base);
1620
1621         if (base->type == FW_ISO_CONTEXT_TRANSMIT)
1622                 return ohci_queue_iso_transmit(base, packet, buffer, payload);
1623         else if (ctx->context.ohci->version >= OHCI_VERSION_1_1)
1624                 return ohci_queue_iso_receive_dualbuffer(base, packet,
1625                                                          buffer, payload);
1626         else
1627                 /* FIXME: Implement fallback for OHCI 1.0 controllers. */
1628                 return -EINVAL;
1629 }
1630
1631 static const struct fw_card_driver ohci_driver = {
1632         .name                   = ohci_driver_name,
1633         .enable                 = ohci_enable,
1634         .update_phy_reg         = ohci_update_phy_reg,
1635         .set_config_rom         = ohci_set_config_rom,
1636         .send_request           = ohci_send_request,
1637         .send_response          = ohci_send_response,
1638         .cancel_packet          = ohci_cancel_packet,
1639         .enable_phys_dma        = ohci_enable_phys_dma,
1640         .get_bus_time           = ohci_get_bus_time,
1641
1642         .allocate_iso_context   = ohci_allocate_iso_context,
1643         .free_iso_context       = ohci_free_iso_context,
1644         .queue_iso              = ohci_queue_iso,
1645         .start_iso              = ohci_start_iso,
1646         .stop_iso               = ohci_stop_iso,
1647 };
1648
1649 static int software_reset(struct fw_ohci *ohci)
1650 {
1651         int i;
1652
1653         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1654
1655         for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1656                 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1657                      OHCI1394_HCControl_softReset) == 0)
1658                         return 0;
1659                 msleep(1);
1660         }
1661
1662         return -EBUSY;
1663 }
1664
1665 /* ---------- pci subsystem interface ---------- */
1666
1667 enum {
1668         CLEANUP_SELF_ID,
1669         CLEANUP_REGISTERS,
1670         CLEANUP_IOMEM,
1671         CLEANUP_DISABLE,
1672         CLEANUP_PUT_CARD,
1673 };
1674
1675 static int cleanup(struct fw_ohci *ohci, int stage, int code)
1676 {
1677         struct pci_dev *dev = to_pci_dev(ohci->card.device);
1678
1679         switch (stage) {
1680         case CLEANUP_SELF_ID:
1681                 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
1682                                   ohci->self_id_cpu, ohci->self_id_bus);
1683         case CLEANUP_REGISTERS:
1684                 kfree(ohci->it_context_list);
1685                 kfree(ohci->ir_context_list);
1686                 pci_iounmap(dev, ohci->registers);
1687         case CLEANUP_IOMEM:
1688                 pci_release_region(dev, 0);
1689         case CLEANUP_DISABLE:
1690                 pci_disable_device(dev);
1691         case CLEANUP_PUT_CARD:
1692                 fw_card_put(&ohci->card);
1693         }
1694
1695         return code;
1696 }
1697
1698 static int __devinit
1699 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1700 {
1701         struct fw_ohci *ohci;
1702         u32 bus_options, max_receive, link_speed;
1703         u64 guid;
1704         int error_code;
1705         size_t size;
1706
1707         ohci = kzalloc(sizeof *ohci, GFP_KERNEL);
1708         if (ohci == NULL) {
1709                 fw_error("Could not malloc fw_ohci data.\n");
1710                 return -ENOMEM;
1711         }
1712
1713         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
1714
1715         if (pci_enable_device(dev)) {
1716                 fw_error("Failed to enable OHCI hardware.\n");
1717                 return cleanup(ohci, CLEANUP_PUT_CARD, -ENODEV);
1718         }
1719
1720         pci_set_master(dev);
1721         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
1722         pci_set_drvdata(dev, ohci);
1723
1724         spin_lock_init(&ohci->lock);
1725
1726         tasklet_init(&ohci->bus_reset_tasklet,
1727                      bus_reset_tasklet, (unsigned long)ohci);
1728
1729         if (pci_request_region(dev, 0, ohci_driver_name)) {
1730                 fw_error("MMIO resource unavailable\n");
1731                 return cleanup(ohci, CLEANUP_DISABLE, -EBUSY);
1732         }
1733
1734         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
1735         if (ohci->registers == NULL) {
1736                 fw_error("Failed to remap registers\n");
1737                 return cleanup(ohci, CLEANUP_IOMEM, -ENXIO);
1738         }
1739
1740         if (software_reset(ohci)) {
1741                 fw_error("Failed to reset ohci card.\n");
1742                 return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY);
1743         }
1744
1745         /* Now enable LPS, which we need in order to start accessing
1746          * most of the registers.  In fact, on some cards (ALI M5251),
1747          * accessing registers in the SClk domain without LPS enabled
1748          * will lock up the machine.  Wait 50msec to make sure we have
1749          * full link enabled.  */
1750         reg_write(ohci, OHCI1394_HCControlSet,
1751                   OHCI1394_HCControl_LPS |
1752                   OHCI1394_HCControl_postedWriteEnable);
1753         flush_writes(ohci);
1754         msleep(50);
1755
1756         reg_write(ohci, OHCI1394_HCControlClear,
1757                   OHCI1394_HCControl_noByteSwapData);
1758
1759         reg_write(ohci, OHCI1394_LinkControlSet,
1760                   OHCI1394_LinkControl_rcvSelfID |
1761                   OHCI1394_LinkControl_cycleTimerEnable |
1762                   OHCI1394_LinkControl_cycleMaster);
1763
1764         ar_context_init(&ohci->ar_request_ctx, ohci,
1765                         OHCI1394_AsReqRcvContextControlSet);
1766
1767         ar_context_init(&ohci->ar_response_ctx, ohci,
1768                         OHCI1394_AsRspRcvContextControlSet);
1769
1770         context_init(&ohci->at_request_ctx, ohci, AT_BUFFER_SIZE,
1771                      OHCI1394_AsReqTrContextControlSet, handle_at_packet);
1772
1773         context_init(&ohci->at_response_ctx, ohci, AT_BUFFER_SIZE,
1774                      OHCI1394_AsRspTrContextControlSet, handle_at_packet);
1775
1776         reg_write(ohci, OHCI1394_ATRetries,
1777                   OHCI1394_MAX_AT_REQ_RETRIES |
1778                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1779                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1780
1781         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
1782         ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
1783         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
1784         size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
1785         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
1786
1787         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
1788         ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
1789         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
1790         size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
1791         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
1792
1793         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
1794                 fw_error("Out of memory for it/ir contexts.\n");
1795                 return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
1796         }
1797
1798         /* self-id dma buffer allocation */
1799         ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
1800                                                SELF_ID_BUF_SIZE,
1801                                                &ohci->self_id_bus,
1802                                                GFP_KERNEL);
1803         if (ohci->self_id_cpu == NULL) {
1804                 fw_error("Out of memory for self ID buffer.\n");
1805                 return cleanup(ohci, CLEANUP_REGISTERS, -ENOMEM);
1806         }
1807
1808         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1809         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1810         reg_write(ohci, OHCI1394_IntEventClear, ~0);
1811         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1812         reg_write(ohci, OHCI1394_IntMaskSet,
1813                   OHCI1394_selfIDComplete |
1814                   OHCI1394_RQPkt | OHCI1394_RSPkt |
1815                   OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1816                   OHCI1394_isochRx | OHCI1394_isochTx |
1817                   OHCI1394_masterIntEnable |
1818                   OHCI1394_cycle64Seconds);
1819
1820         bus_options = reg_read(ohci, OHCI1394_BusOptions);
1821         max_receive = (bus_options >> 12) & 0xf;
1822         link_speed = bus_options & 0x7;
1823         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
1824                 reg_read(ohci, OHCI1394_GUIDLo);
1825
1826         error_code = fw_card_add(&ohci->card, max_receive, link_speed, guid);
1827         if (error_code < 0)
1828                 return cleanup(ohci, CLEANUP_SELF_ID, error_code);
1829
1830         ohci->version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1831         fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
1832                   dev->dev.bus_id, ohci->version >> 16, ohci->version & 0xff);
1833
1834         return 0;
1835 }
1836
1837 static void pci_remove(struct pci_dev *dev)
1838 {
1839         struct fw_ohci *ohci;
1840
1841         ohci = pci_get_drvdata(dev);
1842         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1843         flush_writes(ohci);
1844         fw_core_remove_card(&ohci->card);
1845
1846         /* FIXME: Fail all pending packets here, now that the upper
1847          * layers can't queue any more. */
1848
1849         software_reset(ohci);
1850         free_irq(dev->irq, ohci);
1851         cleanup(ohci, CLEANUP_SELF_ID, 0);
1852
1853         fw_notify("Removed fw-ohci device.\n");
1854 }
1855
1856 static struct pci_device_id pci_table[] = {
1857         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
1858         { }
1859 };
1860
1861 MODULE_DEVICE_TABLE(pci, pci_table);
1862
1863 static struct pci_driver fw_ohci_pci_driver = {
1864         .name           = ohci_driver_name,
1865         .id_table       = pci_table,
1866         .probe          = pci_probe,
1867         .remove         = pci_remove,
1868 };
1869
1870 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
1871 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
1872 MODULE_LICENSE("GPL");
1873
1874 static int __init fw_ohci_init(void)
1875 {
1876         return pci_register_driver(&fw_ohci_pci_driver);
1877 }
1878
1879 static void __exit fw_ohci_cleanup(void)
1880 {
1881         pci_unregister_driver(&fw_ohci_pci_driver);
1882 }
1883
1884 module_init(fw_ohci_init);
1885 module_exit(fw_ohci_cleanup);