2 * twl4030_gpio.c -- access to GPIOs on TWL4030/TPS659x0 chips
4 * Copyright (C) 2006-2007 Texas Instruments, Inc.
5 * Copyright (C) 2006 MontaVista Software, Inc.
7 * Code re-arranged and cleaned up by:
8 * Syed Mohammed Khasim <x0khasim@ti.com>
11 * Andy Lowe / Nishanth Menon
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/module.h>
29 #include <linux/kernel_stat.h>
30 #include <linux/init.h>
31 #include <linux/time.h>
32 #include <linux/interrupt.h>
33 #include <linux/device.h>
34 #include <linux/kthread.h>
35 #include <linux/irq.h>
36 #include <linux/gpio.h>
37 #include <linux/platform_device.h>
38 #include <linux/slab.h>
40 #include <linux/i2c/twl4030.h>
41 #include <linux/i2c/twl4030-gpio.h>
44 static inline void activate_irq(int irq)
47 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
48 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
50 set_irq_flags(irq, IRQF_VALID);
52 /* same effect on other architectures */
57 static struct gpio_chip twl_gpiochip;
58 static int twl4030_gpio_irq_base;
59 static int twl4030_gpio_irq_end;
61 /* genirq interfaces are not available to modules */
63 #define is_module() true
65 #define is_module() false
68 /* BitField Definitions */
70 /* Data banks : 3 banks for 8 gpios each */
71 #define DATA_BANK_MAX 8
72 #define GET_GPIO_DATA_BANK(x) ((x)/DATA_BANK_MAX)
73 #define GET_GPIO_DATA_OFF(x) ((x)%DATA_BANK_MAX)
75 /* GPIODATADIR Fields each block 0-7 */
76 #define BIT_GPIODATADIR_GPIOxDIR(x) (x)
77 #define MASK_GPIODATADIR_GPIOxDIR(x) (0x01 << (x))
79 /* GPIODATAIN Fields each block 0-7 */
80 #define BIT_GPIODATAIN_GPIOxIN(x) (x)
81 #define MASK_GPIODATAIN_GPIOxIN(x) (0x01 << (x))
83 /* GPIODATAOUT Fields each block 0-7 */
84 #define BIT_GPIODATAOUT_GPIOxOUT(x) (x)
85 #define MASK_GPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
87 /* CLEARGPIODATAOUT Fields */
88 #define BIT_CLEARGPIODATAOUT_GPIOxOUT(x) (x)
89 #define MASK_CLEARGPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
91 /* SETGPIODATAOUT Fields */
92 #define BIT_SETGPIODATAOUT_GPIOxOUT(x) (x)
93 #define MASK_SETGPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
95 /* GPIO_DEBEN Fields */
96 #define BIT_GPIO_DEBEN_GPIOxDEB(x) (x)
97 #define MASK_GPIO_DEBEN_GPIOxDEB(x) (0x01 << (x))
99 /* GPIO_ISR1A Fields */
100 #define BIT_GPIO_ISR_GPIOxISR(x) (x)
101 #define MASK_GPIO_ISR_GPIOxISR(x) (0x01 << (x))
103 /* GPIO_IMR1A Fields */
104 #define BIT_GPIO_IMR1A_GPIOxIMR(x) (x)
105 #define MASK_GPIO_IMR1A_GPIOxIMR(x) (0x01 << (x))
107 /* GPIO_SIR1 Fields */
108 #define BIT_GPIO_SIR1_GPIOxSIR(x) (x)
109 #define MASK_GPIO_SIR1_GPIO0SIR (0x01 << (x))
112 /* Control banks : 5 banks for 4 gpios each */
113 #define DATA_CTL_MAX 4
114 #define GET_GPIO_CTL_BANK(x) ((x)/DATA_CTL_MAX)
115 #define GET_GPIO_CTL_OFF(x) ((x)%DATA_CTL_MAX)
116 #define GPIO_BANK_MAX GET_GPIO_CTL_BANK(TWL4030_GPIO_MAX)
118 /* GPIOPUPDCTRx Fields 5 banks of 4 gpios each */
119 #define BIT_GPIOPUPDCTR1_GPIOxPD(x) (2 * (x))
120 #define MASK_GPIOPUPDCTR1_GPIOxPD(x) (0x01 << (2 * (x)))
121 #define BIT_GPIOPUPDCTR1_GPIOxPU(x) ((x) + 1)
122 #define MASK_GPIOPUPDCTR1_GPIOxPU(x) (0x01 << (((2 * (x)) + 1)))
124 /* GPIO_EDR1 Fields */
125 #define BIT_GPIO_EDR1_GPIOxFALLING(x) (2 * (x))
126 #define MASK_GPIO_EDR1_GPIOxFALLING(x) (0x01 << (2 * (x)))
127 #define BIT_GPIO_EDR1_GPIOxRISING(x) ((x) + 1)
128 #define MASK_GPIO_EDR1_GPIOxRISING(x) (0x01 << (((2 * (x)) + 1)))
130 /* GPIO_SIH_CTRL Fields */
131 #define BIT_GPIO_SIH_CTRL_EXCLEN (0x000)
132 #define MASK_GPIO_SIH_CTRL_EXCLEN (0x00000001)
133 #define BIT_GPIO_SIH_CTRL_PENDDIS (0x001)
134 #define MASK_GPIO_SIH_CTRL_PENDDIS (0x00000002)
135 #define BIT_GPIO_SIH_CTRL_COR (0x002)
136 #define MASK_GPIO_SIH_CTRL_COR (0x00000004)
138 /* GPIO_CTRL Fields */
139 #define BIT_GPIO_CTRL_GPIO0CD1 (0x000)
140 #define MASK_GPIO_CTRL_GPIO0CD1 (0x00000001)
141 #define BIT_GPIO_CTRL_GPIO1CD2 (0x001)
142 #define MASK_GPIO_CTRL_GPIO1CD2 (0x00000002)
143 #define BIT_GPIO_CTRL_GPIO_ON (0x002)
144 #define MASK_GPIO_CTRL_GPIO_ON (0x00000004)
146 /* Mask for GPIO registers when aggregated into a 32-bit integer */
147 #define GPIO_32_MASK 0x0003ffff
149 /* Data structures */
150 static DEFINE_MUTEX(gpio_lock);
152 /* store usage of each GPIO. - each bit represents one GPIO */
153 static unsigned int gpio_usage_count;
155 /* shadow the imr register */
156 static unsigned int gpio_imr_shadow;
158 /* bitmask of pending requests to unmask gpio interrupts */
159 static unsigned int gpio_pending_unmask;
161 /* bitmask of requests to set gpio irq trigger type */
162 static unsigned int gpio_pending_trigger;
164 /* pointer to gpio unmask thread struct */
165 static struct task_struct *gpio_unmask_thread;
168 * Helper functions to read and write the GPIO ISR and IMR registers as
169 * 32-bit integers. Functions return 0 on success, non-zero otherwise.
170 * The caller must hold gpio_lock.
173 static int gpio_read_isr(unsigned int *isr)
178 ret = twl4030_i2c_read(TWL4030_MODULE_GPIO, (u8 *) isr,
181 *isr &= GPIO_32_MASK;
186 static int gpio_write_isr(unsigned int isr)
190 * The buffer passed to the twl4030_i2c_write() routine must have an
191 * extra byte at the beginning reserved for its internal use.
194 isr = cpu_to_le32(isr);
195 return twl4030_i2c_write(TWL4030_MODULE_GPIO, (u8 *) &isr,
199 static int gpio_write_imr(unsigned int imr)
203 * The buffer passed to the twl4030_i2c_write() routine must have an
204 * extra byte at the beginning reserved for its internal use.
207 imr = cpu_to_le32(imr);
208 return twl4030_i2c_write(TWL4030_MODULE_GPIO, (u8 *) &imr,
213 * These routines are analagous to the irqchip methods, but they are designed
214 * to be called from thread context with cpu interrupts enabled and with no
215 * locked spinlocks. We call these routines from our custom IRQ handler
216 * instead of the usual irqchip methods.
218 static void twl4030_gpio_mask_and_ack(unsigned int irq)
220 int gpio = irq - twl4030_gpio_irq_base;
222 mutex_lock(&gpio_lock);
224 gpio_imr_shadow |= (1 << gpio);
225 gpio_write_imr(gpio_imr_shadow);
227 gpio_write_isr(1 << gpio);
228 mutex_unlock(&gpio_lock);
231 static void twl4030_gpio_unmask(unsigned int irq)
233 int gpio = irq - twl4030_gpio_irq_base;
235 mutex_lock(&gpio_lock);
236 gpio_imr_shadow &= ~(1 << gpio);
237 gpio_write_imr(gpio_imr_shadow);
238 mutex_unlock(&gpio_lock);
242 * These are the irqchip methods for the TWL4030 GPIO interrupts.
243 * Our IRQ handle method doesn't call these, but they will be called by
244 * other routines such as setup_irq() and enable_irq(). They are called
245 * with cpu interrupts disabled and with a lock on the irq_controller_lock
246 * spinlock. This complicates matters, because accessing the TWL4030 GPIO
247 * interrupt controller requires I2C bus transactions that can't be initiated
248 * in this context. Our solution is to defer accessing the interrupt
249 * controller to a kernel thread. We only need to support the unmask method.
252 static void twl4030_gpio_irq_mask_and_ack(unsigned int irq)
256 static void twl4030_gpio_irq_mask(unsigned int irq)
260 static void twl4030_gpio_irq_unmask(unsigned int irq)
262 int gpio = irq - twl4030_gpio_irq_base;
264 gpio_pending_unmask |= (1 << gpio);
265 if (gpio_unmask_thread && gpio_unmask_thread->state != TASK_RUNNING)
266 wake_up_process(gpio_unmask_thread);
269 static int twl4030_gpio_irq_set_type(unsigned int irq, unsigned trigger)
271 struct irq_desc *desc = irq_desc + irq;
272 int gpio = irq - twl4030_gpio_irq_base;
274 trigger &= IRQ_TYPE_SENSE_MASK;
275 if (trigger & ~IRQ_TYPE_EDGE_BOTH)
277 if ((desc->status & IRQ_TYPE_SENSE_MASK) == trigger)
280 desc->status &= ~IRQ_TYPE_SENSE_MASK;
281 desc->status |= trigger;
283 /* REVISIT This makes the "unmask" thread do double duty,
284 * updating IRQ trigger modes too. Rename appropriately...
286 gpio_pending_trigger |= (1 << gpio);
287 if (gpio_unmask_thread && gpio_unmask_thread->state != TASK_RUNNING)
288 wake_up_process(gpio_unmask_thread);
293 static struct irq_chip twl4030_gpio_irq_chip = {
295 .ack = twl4030_gpio_irq_mask_and_ack,
296 .mask = twl4030_gpio_irq_mask,
297 .unmask = twl4030_gpio_irq_unmask,
298 .set_type = twl4030_gpio_irq_set_type,
302 * These are the irqchip methods for the TWL4030 PIH GPIO module interrupt.
303 * The PIH module doesn't have interrupt masking capability, so these
306 static void twl4030_gpio_module_ack(unsigned int irq) {}
307 static void twl4030_gpio_module_mask(unsigned int irq) {}
308 static void twl4030_gpio_module_unmask(unsigned int irq) {}
309 static struct irq_chip twl4030_gpio_module_irq_chip = {
310 .ack = twl4030_gpio_module_ack,
311 .mask = twl4030_gpio_module_mask,
312 .unmask = twl4030_gpio_module_unmask,
316 * To configure TWL4030 GPIO module registers
318 static inline int gpio_twl4030_write(u8 address, u8 data)
322 ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, data, address);
327 * To read a TWL4030 GPIO module register
329 static inline int gpio_twl4030_read(u8 address)
334 ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &data, address);
341 * twl4030 GPIO request function
343 int twl4030_request_gpio(int gpio)
347 if (unlikely(gpio >= TWL4030_GPIO_MAX))
350 ret = gpio_request(twl_gpiochip.base + gpio, NULL);
354 mutex_lock(&gpio_lock);
355 if (gpio_usage_count & (0x1 << gpio)) {
358 /* First time usage? - switch on GPIO module */
359 if (!gpio_usage_count) {
360 ret = gpio_twl4030_write(REG_GPIO_CTRL,
361 MASK_GPIO_CTRL_GPIO_ON);
362 ret = gpio_twl4030_write(REG_GPIO_SIH_CTRL, 0x00);
365 gpio_usage_count |= (0x1 << gpio);
367 gpio_free(twl_gpiochip.base + gpio);
369 mutex_unlock(&gpio_lock);
372 EXPORT_SYMBOL(twl4030_request_gpio);
375 * TWL4030 GPIO free module
377 int twl4030_free_gpio(int gpio)
381 if (unlikely(gpio >= TWL4030_GPIO_MAX))
384 mutex_lock(&gpio_lock);
386 if ((gpio_usage_count & (0x1 << gpio)) == 0) {
389 gpio_usage_count &= ~(0x1 << gpio);
390 gpio_free(twl_gpiochip.base + gpio);
393 /* Last time usage? - switch off GPIO module */
394 if (ret == 0 && !gpio_usage_count)
395 ret = gpio_twl4030_write(REG_GPIO_CTRL, 0x0);
397 mutex_unlock(&gpio_lock);
400 EXPORT_SYMBOL(twl4030_free_gpio);
403 * Set direction for TWL4030 GPIO
405 static int twl4030_set_gpio_direction(int gpio, int is_input)
407 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
408 u8 d_msk = MASK_GPIODATADIR_GPIOxDIR(GET_GPIO_DATA_OFF(gpio));
410 u8 base = REG_GPIODATADIR1 + d_bnk;
413 if (unlikely(!(gpio_usage_count & (0x1 << gpio))))
416 mutex_lock(&gpio_lock);
417 ret = gpio_twl4030_read(base);
420 reg = (u8) ((ret) & ~(d_msk));
422 reg = (u8) ((ret) | (d_msk));
424 ret = gpio_twl4030_write(base, reg);
426 mutex_unlock(&gpio_lock);
431 * To enable/disable GPIO pin on TWL4030
433 static int twl4030_set_gpio_dataout(int gpio, int enable)
435 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
436 u8 d_msk = MASK_GPIODATAOUT_GPIOxOUT(GET_GPIO_DATA_OFF(gpio));
440 if (unlikely(!(gpio_usage_count & (0x1 << gpio))))
444 base = REG_SETGPIODATAOUT1 + d_bnk;
446 base = REG_CLEARGPIODATAOUT1 + d_bnk;
448 mutex_lock(&gpio_lock);
449 ret = gpio_twl4030_write(base, d_msk);
450 mutex_unlock(&gpio_lock);
455 * To get the status of a GPIO pin on TWL4030
457 int twl4030_get_gpio_datain(int gpio)
459 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
460 u8 d_off = BIT_GPIODATAIN_GPIOxIN(GET_GPIO_DATA_OFF(gpio));
464 if (unlikely((gpio >= TWL4030_GPIO_MAX)
465 || !(gpio_usage_count & (0x1 << gpio))))
468 base = REG_GPIODATAIN1 + d_bnk;
469 mutex_lock(&gpio_lock);
470 ret = gpio_twl4030_read(base);
471 mutex_unlock(&gpio_lock);
473 ret = (ret >> d_off) & 0x1;
477 EXPORT_SYMBOL(twl4030_get_gpio_datain);
481 * Configure PULL type for a GPIO pin on TWL4030
483 int twl4030_set_gpio_pull(int gpio, int pull_dircn)
485 u8 c_bnk = GET_GPIO_CTL_BANK(gpio);
486 u8 c_off = GET_GPIO_CTL_OFF(gpio);
492 if (unlikely((gpio >= TWL4030_GPIO_MAX) ||
493 !(gpio_usage_count & (0x1 << gpio))))
496 base = REG_GPIOPUPDCTR1 + c_bnk;
497 if (pull_dircn == TWL4030_GPIO_PULL_DOWN)
498 c_msk = MASK_GPIOPUPDCTR1_GPIOxPD(c_off);
499 else if (pull_dircn == TWL4030_GPIO_PULL_UP)
500 c_msk = MASK_GPIOPUPDCTR1_GPIOxPU(c_off);
502 mutex_lock(&gpio_lock);
503 ret = gpio_twl4030_read(base);
505 /* clear the previous up/down values */
507 reg &= ~(MASK_GPIOPUPDCTR1_GPIOxPU(c_off) |
508 MASK_GPIOPUPDCTR1_GPIOxPD(c_off));
510 ret = gpio_twl4030_write(base, reg);
512 mutex_unlock(&gpio_lock);
517 static int twl4030_set_gpio_edge_ctrl(int gpio, int edge)
519 u8 c_bnk = GET_GPIO_CTL_BANK(gpio);
520 u8 c_off = GET_GPIO_CTL_OFF(gpio);
526 base = REG_GPIO_EDR1 + c_bnk;
528 if (edge & IRQ_TYPE_EDGE_RISING)
529 c_msk |= MASK_GPIO_EDR1_GPIOxRISING(c_off);
530 if (edge & IRQ_TYPE_EDGE_FALLING)
531 c_msk |= MASK_GPIO_EDR1_GPIOxFALLING(c_off);
533 mutex_lock(&gpio_lock);
534 ret = gpio_twl4030_read(base);
536 /* clear the previous rising/falling values */
538 reg &= ~(MASK_GPIO_EDR1_GPIOxFALLING(c_off)
539 | MASK_GPIO_EDR1_GPIOxRISING(c_off));
541 ret = gpio_twl4030_write(base, reg);
543 mutex_unlock(&gpio_lock);
548 * Configure debounce timing value for a GPIO pin on TWL4030
550 int twl4030_set_gpio_debounce(int gpio, int enable)
552 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
553 u8 d_msk = MASK_GPIO_DEBEN_GPIOxDEB(GET_GPIO_DATA_OFF(gpio));
558 if (unlikely((gpio >= TWL4030_GPIO_MAX)
559 || !(gpio_usage_count & (0x1 << gpio))))
562 base = REG_GPIO_DEBEN1 + d_bnk;
563 mutex_lock(&gpio_lock);
564 ret = gpio_twl4030_read(base);
567 reg = (u8) ((ret) | (d_msk));
569 reg = (u8) ((ret) & ~(d_msk));
571 ret = gpio_twl4030_write(base, reg);
573 mutex_unlock(&gpio_lock);
576 EXPORT_SYMBOL(twl4030_set_gpio_debounce);
580 * Configure Card detect for GPIO pin on TWL4030
582 int twl4030_set_gpio_card_detect(int gpio, int enable)
585 u8 msk = (1 << gpio);
588 /* Only GPIO 0 or 1 can be used for CD feature.. */
589 if (unlikely((gpio >= TWL4030_GPIO_MAX)
590 || !(gpio_usage_count & (0x1 << gpio))
591 || (gpio >= TWL4030_GPIO_MAX_CD))) {
595 mutex_lock(&gpio_lock);
596 ret = gpio_twl4030_read(REG_GPIO_CTRL);
599 reg = (u8) (ret | msk);
601 reg = (u8) (ret & ~msk);
603 ret = gpio_twl4030_write(REG_GPIO_CTRL, reg);
605 mutex_unlock(&gpio_lock);
610 /* MODULE FUNCTIONS */
613 * gpio_unmask_thread() runs as a kernel thread. It is awakened by the unmask
614 * method for the GPIO interrupts. It unmasks all of the GPIO interrupts
615 * specified in the gpio_pending_unmask bitmask. We have to do the unmasking
616 * in a kernel thread rather than directly in the unmask method because of the
617 * need to access the TWL4030 via the I2C bus. Note that we don't need to be
618 * concerned about race conditions where the request to unmask a GPIO interrupt
619 * has already been cancelled before this thread does the unmasking. If a GPIO
620 * interrupt is improperly unmasked, then the IRQ handler for it will mask it
621 * when an interrupt occurs.
623 static int twl4030_gpio_unmask_thread(void *data)
625 current->flags |= PF_NOFREEZE;
627 while (!kthread_should_stop()) {
629 unsigned int gpio_unmask;
630 unsigned int gpio_trigger;
633 gpio_unmask = gpio_pending_unmask;
634 gpio_pending_unmask = 0;
636 gpio_trigger = gpio_pending_trigger;
637 gpio_pending_trigger = 0;
640 for (irq = twl4030_gpio_irq_base; 0 != gpio_unmask;
641 gpio_unmask >>= 1, irq++) {
642 if (gpio_unmask & 0x1)
643 twl4030_gpio_unmask(irq);
646 for (irq = twl4030_gpio_irq_base;
648 gpio_trigger >>= 1, irq++) {
649 struct irq_desc *desc;
652 if (!(gpio_trigger & 0x1))
655 desc = irq_desc + irq;
656 spin_lock_irq(&desc->lock);
657 type = desc->status & IRQ_TYPE_SENSE_MASK;
658 spin_unlock_irq(&desc->lock);
660 twl4030_set_gpio_edge_ctrl(irq - twl4030_gpio_irq_base,
665 if (!gpio_pending_unmask && !gpio_pending_trigger)
666 set_current_state(TASK_INTERRUPTIBLE);
671 set_current_state(TASK_RUNNING);
676 * do_twl4030_gpio_irq() is the desc->handle method for each of the twl4030
677 * gpio interrupts. It executes in kernel thread context.
678 * On entry, cpu interrupts are enabled.
680 static void do_twl4030_gpio_irq(unsigned int irq, irq_desc_t *desc)
682 struct irqaction *action;
683 const unsigned int cpu = smp_processor_id();
685 desc->status |= IRQ_LEVEL;
688 * Acknowledge, clear _AND_ disable the interrupt.
690 twl4030_gpio_mask_and_ack(irq);
693 kstat_cpu(cpu).irqs[irq]++;
695 action = desc->action;
701 /* Call the ISR with cpu interrupts enabled. */
702 ret = action->handler(irq, action->dev_id);
703 if (ret == IRQ_HANDLED)
704 status |= action->flags;
706 action = action->next;
709 if (retval != IRQ_HANDLED)
710 printk(KERN_ERR "ISR for TWL4030 GPIO"
711 " irq %d can't handle interrupt\n",
715 twl4030_gpio_unmask(irq);
721 * do_twl4030_gpio_module_irq() is the desc->handle method for the twl4030 gpio
722 * module interrupt. It executes in kernel thread context.
723 * This is a chained interrupt, so there is no desc->action method for it.
724 * We query the gpio module interrupt controller in the twl4030 to determine
725 * which gpio lines are generating interrupt requests, and then call the
726 * desc->handle method for each gpio that needs service.
727 * On entry, cpu interrupts are disabled.
729 static void do_twl4030_gpio_module_irq(unsigned int irq, irq_desc_t *desc)
731 const unsigned int cpu = smp_processor_id();
733 desc->status |= IRQ_LEVEL;
735 * The desc->handle method would normally call the desc->chip->ack
736 * method here, but we won't bother since our ack method is NULL.
740 unsigned int gpio_isr;
742 kstat_cpu(cpu).irqs[irq]++;
745 mutex_lock(&gpio_lock);
746 if (gpio_read_isr(&gpio_isr))
748 mutex_unlock(&gpio_lock);
750 for (gpio_irq = twl4030_gpio_irq_base; 0 != gpio_isr;
751 gpio_isr >>= 1, gpio_irq++) {
752 if (gpio_isr & 0x1) {
753 irq_desc_t *d = irq_desc + gpio_irq;
754 d->handle_irq(gpio_irq, d);
760 * Here is where we should call the unmask method, but again we
761 * won't bother since it is NULL.
766 /*----------------------------------------------------------------------*/
768 static int twl_direction_in(struct gpio_chip *chip, unsigned offset)
770 return twl4030_set_gpio_direction(offset, 1);
773 static int twl_get(struct gpio_chip *chip, unsigned offset)
775 int status = twl4030_get_gpio_datain(offset);
777 return (status < 0) ? 0 : status;
780 static int twl_direction_out(struct gpio_chip *chip, unsigned offset, int value)
782 twl4030_set_gpio_dataout(offset, value);
783 return twl4030_set_gpio_direction(offset, 0);
786 static void twl_set(struct gpio_chip *chip, unsigned offset, int value)
788 twl4030_set_gpio_dataout(offset, value);
791 static struct gpio_chip twl_gpiochip = {
793 .owner = THIS_MODULE,
794 .direction_input = twl_direction_in,
796 .direction_output = twl_direction_out,
801 /*----------------------------------------------------------------------*/
803 static int gpio_twl4030_remove(struct platform_device *pdev);
805 static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
807 struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
811 /* All GPIO interrupts are initially masked */
812 gpio_pending_unmask = 0;
813 gpio_imr_shadow = GPIO_32_MASK;
814 ret = gpio_write_imr(gpio_imr_shadow);
816 twl4030_gpio_irq_base = pdata->irq_base;
817 twl4030_gpio_irq_end = pdata->irq_end;
819 if ((twl4030_gpio_irq_end - twl4030_gpio_irq_base) > 0) {
822 "can't dispatch IRQs from modules\n");
825 if (twl4030_gpio_irq_end > NR_IRQS) {
827 "last IRQ is too large: %d\n",
828 twl4030_gpio_irq_end);
832 dev_notice(&pdev->dev,
833 "no IRQs being dispatched\n");
839 * Create a kernel thread to handle deferred unmasking of gpio
842 gpio_unmask_thread = kthread_create(twl4030_gpio_unmask_thread,
843 NULL, "twl4030 gpio");
844 if (!gpio_unmask_thread) {
846 "could not create twl4030 gpio unmask"
853 /* install an irq handler for each of the gpio interrupts */
854 for (irq = twl4030_gpio_irq_base; irq < twl4030_gpio_irq_end;
856 set_irq_chip_and_handler(irq, &twl4030_gpio_irq_chip,
857 do_twl4030_gpio_irq);
861 /* gpio module IRQ */
862 irq = platform_get_irq(pdev, 0);
865 * Install an irq handler to demultiplex the gpio module
868 set_irq_chip(irq, &twl4030_gpio_module_irq_chip);
869 set_irq_chained_handler(irq, do_twl4030_gpio_module_irq);
870 wake_up_process(gpio_unmask_thread);
872 dev_info(&pdev->dev, "IRQ %d chains IRQs %d..%d\n", irq,
873 twl4030_gpio_irq_base, twl4030_gpio_irq_end - 1);
878 twl_gpiochip.base = pdata->gpio_base;
879 twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
880 twl_gpiochip.dev = &pdev->dev;
882 ret = gpiochip_add(&twl_gpiochip);
885 "could not register gpiochip, %d\n",
887 twl_gpiochip.ngpio = 0;
888 gpio_twl4030_remove(pdev);
889 } else if (pdata->setup) {
892 status = pdata->setup(&pdev->dev,
893 pdata->gpio_base, TWL4030_GPIO_MAX);
895 dev_dbg(&pdev->dev, "setup --> %d\n", status);
902 static int __devexit gpio_twl4030_remove(struct platform_device *pdev)
904 struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
908 if (pdata->teardown) {
909 status = pdata->teardown(&pdev->dev,
910 pdata->gpio_base, TWL4030_GPIO_MAX);
912 dev_dbg(&pdev->dev, "teardown --> %d\n", status);
917 status = gpiochip_remove(&twl_gpiochip);
921 if (is_module() || (twl4030_gpio_irq_end - twl4030_gpio_irq_base) <= 0)
924 /* uninstall the gpio demultiplexing interrupt handler */
925 irq = platform_get_irq(pdev, 0);
926 set_irq_handler(irq, NULL);
928 /* uninstall the irq handler for each of the gpio interrupts */
929 for (irq = twl4030_gpio_irq_base; irq < twl4030_gpio_irq_end; irq++)
930 set_irq_handler(irq, NULL);
932 /* stop the gpio unmask kernel thread */
933 if (gpio_unmask_thread) {
934 kthread_stop(gpio_unmask_thread);
935 gpio_unmask_thread = NULL;
941 /* Note: this hardware lives inside an I2C-based multi-function device. */
942 MODULE_ALIAS("platform:twl4030_gpio");
944 static struct platform_driver gpio_twl4030_driver = {
945 .driver.name = "twl4030_gpio",
946 .driver.owner = THIS_MODULE,
947 .probe = gpio_twl4030_probe,
948 .remove = __devexit_p(gpio_twl4030_remove),
951 static int __init gpio_twl4030_init(void)
953 return platform_driver_register(&gpio_twl4030_driver);
955 subsys_initcall(gpio_twl4030_init);
957 static void __exit gpio_twl4030_exit(void)
959 platform_driver_unregister(&gpio_twl4030_driver);
961 module_exit(gpio_twl4030_exit);
963 MODULE_AUTHOR("Texas Instruments, Inc.");
964 MODULE_DESCRIPTION("GPIO interface for TWL4030");
965 MODULE_LICENSE("GPL");