2 * Blackfin On-Chip Two Wire Interface Driver
4 * Copyright 2005-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/i2c.h>
16 #include <linux/timer.h>
17 #include <linux/spinlock.h>
18 #include <linux/completion.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
22 #include <asm/blackfin.h>
23 #include <asm/portmux.h>
26 #define POLL_TIMEOUT (2 * HZ)
29 #define TWI_I2C_MODE_STANDARD 1
30 #define TWI_I2C_MODE_STANDARDSUB 2
31 #define TWI_I2C_MODE_COMBINED 3
32 #define TWI_I2C_MODE_REPEAT 4
34 struct bfin_twi_iface {
46 struct timer_list timeout_timer;
47 struct i2c_adapter adap;
48 struct completion complete;
52 void __iomem *regs_base;
56 #define DEFINE_TWI_REG(reg, off) \
57 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
58 { return bfin_read16(iface->regs_base + (off)); } \
59 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
60 { bfin_write16(iface->regs_base + (off), v); }
62 DEFINE_TWI_REG(CLKDIV, 0x00)
63 DEFINE_TWI_REG(CONTROL, 0x04)
64 DEFINE_TWI_REG(SLAVE_CTL, 0x08)
65 DEFINE_TWI_REG(SLAVE_STAT, 0x0C)
66 DEFINE_TWI_REG(SLAVE_ADDR, 0x10)
67 DEFINE_TWI_REG(MASTER_CTL, 0x14)
68 DEFINE_TWI_REG(MASTER_STAT, 0x18)
69 DEFINE_TWI_REG(MASTER_ADDR, 0x1C)
70 DEFINE_TWI_REG(INT_STAT, 0x20)
71 DEFINE_TWI_REG(INT_MASK, 0x24)
72 DEFINE_TWI_REG(FIFO_CTL, 0x28)
73 DEFINE_TWI_REG(FIFO_STAT, 0x2C)
74 DEFINE_TWI_REG(XMT_DATA8, 0x80)
75 DEFINE_TWI_REG(XMT_DATA16, 0x84)
76 DEFINE_TWI_REG(RCV_DATA8, 0x88)
77 DEFINE_TWI_REG(RCV_DATA16, 0x8C)
79 static const u16 pin_req[2][3] = {
80 {P_TWI0_SCL, P_TWI0_SDA, 0},
81 {P_TWI1_SCL, P_TWI1_SDA, 0},
84 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface)
86 unsigned short twi_int_status = read_INT_STAT(iface);
87 unsigned short mast_stat = read_MASTER_STAT(iface);
89 if (twi_int_status & XMTSERV) {
90 /* Transmit next data */
91 if (iface->writeNum > 0) {
92 write_XMT_DATA8(iface, *(iface->transPtr++));
95 /* start receive immediately after complete sending in
98 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
99 write_MASTER_CTL(iface,
100 read_MASTER_CTL(iface) | MDIR | RSTART);
101 else if (iface->manual_stop)
102 write_MASTER_CTL(iface,
103 read_MASTER_CTL(iface) | STOP);
104 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
105 iface->cur_msg+1 < iface->msg_num)
106 write_MASTER_CTL(iface,
107 read_MASTER_CTL(iface) | RSTART);
110 write_INT_STAT(iface, XMTSERV);
113 if (twi_int_status & RCVSERV) {
114 if (iface->readNum > 0) {
115 /* Receive next data */
116 *(iface->transPtr) = read_RCV_DATA8(iface);
117 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
118 /* Change combine mode into sub mode after
121 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
122 /* Get read number from first byte in block
125 if (iface->readNum == 1 && iface->manual_stop)
126 iface->readNum = *iface->transPtr + 1;
130 } else if (iface->manual_stop) {
131 write_MASTER_CTL(iface,
132 read_MASTER_CTL(iface) | STOP);
134 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
135 iface->cur_msg+1 < iface->msg_num) {
136 write_MASTER_CTL(iface,
137 read_MASTER_CTL(iface) | RSTART);
140 /* Clear interrupt source */
141 write_INT_STAT(iface, RCVSERV);
144 if (twi_int_status & MERR) {
145 write_INT_STAT(iface, MERR);
146 write_INT_MASK(iface, 0);
147 write_MASTER_STAT(iface, 0x3e);
148 write_MASTER_CTL(iface, 0);
150 iface->result = -EIO;
151 /* if both err and complete int stats are set, return proper
154 if (twi_int_status & MCOMP) {
155 write_INT_STAT(iface, MCOMP);
156 write_INT_MASK(iface, 0);
157 write_MASTER_CTL(iface, 0);
159 /* If it is a quick transfer, only address bug no data,
160 * not an err, return 1.
162 if (iface->writeNum == 0 && (mast_stat & BUFRDERR))
164 /* If address not acknowledged return -1,
167 else if (!(mast_stat & ANAK))
170 complete(&iface->complete);
173 if (twi_int_status & MCOMP) {
174 write_INT_STAT(iface, MCOMP);
176 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
177 if (iface->readNum == 0) {
178 /* set the read number to 1 and ask for manual
179 * stop in block combine mode
182 iface->manual_stop = 1;
183 write_MASTER_CTL(iface,
184 read_MASTER_CTL(iface) | (0xff << 6));
186 /* set the readd number in other
189 write_MASTER_CTL(iface,
190 (read_MASTER_CTL(iface) &
192 (iface->readNum << 6));
194 /* remove restart bit and enable master receive */
195 write_MASTER_CTL(iface,
196 read_MASTER_CTL(iface) & ~RSTART);
197 write_MASTER_CTL(iface,
198 read_MASTER_CTL(iface) | MEN | MDIR);
200 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
201 iface->cur_msg+1 < iface->msg_num) {
203 iface->transPtr = iface->pmsg[iface->cur_msg].buf;
204 iface->writeNum = iface->readNum =
205 iface->pmsg[iface->cur_msg].len;
206 /* Set Transmit device address */
207 write_MASTER_ADDR(iface,
208 iface->pmsg[iface->cur_msg].addr);
209 if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
210 iface->read_write = I2C_SMBUS_READ;
212 iface->read_write = I2C_SMBUS_WRITE;
213 /* Transmit first data */
214 if (iface->writeNum > 0) {
215 write_XMT_DATA8(iface,
216 *(iface->transPtr++));
222 if (iface->pmsg[iface->cur_msg].len <= 255)
223 write_MASTER_CTL(iface,
224 iface->pmsg[iface->cur_msg].len << 6);
226 write_MASTER_CTL(iface, 0xff << 6);
227 iface->manual_stop = 1;
229 /* remove restart bit and enable master receive */
230 write_MASTER_CTL(iface,
231 read_MASTER_CTL(iface) & ~RSTART);
232 write_MASTER_CTL(iface, read_MASTER_CTL(iface) |
233 MEN | ((iface->read_write == I2C_SMBUS_READ) ?
238 write_INT_MASK(iface, 0);
239 write_MASTER_CTL(iface, 0);
241 complete(&iface->complete);
246 /* Interrupt handler */
247 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
249 struct bfin_twi_iface *iface = dev_id;
252 spin_lock_irqsave(&iface->lock, flags);
253 del_timer(&iface->timeout_timer);
254 bfin_twi_handle_interrupt(iface);
255 spin_unlock_irqrestore(&iface->lock, flags);
259 static void bfin_twi_timeout(unsigned long data)
261 struct bfin_twi_iface *iface = (struct bfin_twi_iface *)data;
264 spin_lock_irqsave(&iface->lock, flags);
265 bfin_twi_handle_interrupt(iface);
266 if (iface->result == 0) {
267 iface->timeout_count--;
268 if (iface->timeout_count > 0) {
269 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
270 add_timer(&iface->timeout_timer);
273 complete(&iface->complete);
276 spin_unlock_irqrestore(&iface->lock, flags);
280 * Generic i2c master transfer entrypoint
282 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
283 struct i2c_msg *msgs, int num)
285 struct bfin_twi_iface *iface = adap->algo_data;
286 struct i2c_msg *pmsg;
289 if (!(read_CONTROL(iface) & TWI_ENA))
292 while (read_MASTER_STAT(iface) & BUSBUSY)
296 iface->msg_num = num;
300 if (pmsg->flags & I2C_M_TEN) {
301 dev_err(&adap->dev, "10 bits addr not supported!\n");
305 iface->cur_mode = TWI_I2C_MODE_REPEAT;
306 iface->manual_stop = 0;
307 iface->transPtr = pmsg->buf;
308 iface->writeNum = iface->readNum = pmsg->len;
310 iface->timeout_count = 10;
311 init_completion(&(iface->complete));
312 /* Set Transmit device address */
313 write_MASTER_ADDR(iface, pmsg->addr);
315 /* FIFO Initiation. Data in FIFO should be
316 * discarded before start a new operation.
318 write_FIFO_CTL(iface, 0x3);
320 write_FIFO_CTL(iface, 0);
323 if (pmsg->flags & I2C_M_RD)
324 iface->read_write = I2C_SMBUS_READ;
326 iface->read_write = I2C_SMBUS_WRITE;
327 /* Transmit first data */
328 if (iface->writeNum > 0) {
329 write_XMT_DATA8(iface, *(iface->transPtr++));
336 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
338 /* Interrupt mask . Enable XMT, RCV interrupt */
339 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
342 if (pmsg->len <= 255)
343 write_MASTER_CTL(iface, pmsg->len << 6);
345 write_MASTER_CTL(iface, 0xff << 6);
346 iface->manual_stop = 1;
349 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
350 add_timer(&iface->timeout_timer);
353 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
354 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
355 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
358 wait_for_completion(&iface->complete);
369 * SMBus type transfer entrypoint
372 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
373 unsigned short flags, char read_write,
374 u8 command, int size, union i2c_smbus_data *data)
376 struct bfin_twi_iface *iface = adap->algo_data;
379 if (!(read_CONTROL(iface) & TWI_ENA))
382 while (read_MASTER_STAT(iface) & BUSBUSY)
388 /* Prepare datas & select mode */
390 case I2C_SMBUS_QUICK:
391 iface->transPtr = NULL;
392 iface->cur_mode = TWI_I2C_MODE_STANDARD;
396 iface->transPtr = NULL;
398 if (read_write == I2C_SMBUS_READ)
402 iface->transPtr = &data->byte;
404 iface->cur_mode = TWI_I2C_MODE_STANDARD;
406 case I2C_SMBUS_BYTE_DATA:
407 if (read_write == I2C_SMBUS_READ) {
409 iface->cur_mode = TWI_I2C_MODE_COMBINED;
412 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
414 iface->transPtr = &data->byte;
416 case I2C_SMBUS_WORD_DATA:
417 if (read_write == I2C_SMBUS_READ) {
419 iface->cur_mode = TWI_I2C_MODE_COMBINED;
422 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
424 iface->transPtr = (u8 *)&data->word;
426 case I2C_SMBUS_PROC_CALL:
429 iface->cur_mode = TWI_I2C_MODE_COMBINED;
430 iface->transPtr = (u8 *)&data->word;
432 case I2C_SMBUS_BLOCK_DATA:
433 if (read_write == I2C_SMBUS_READ) {
435 iface->cur_mode = TWI_I2C_MODE_COMBINED;
437 iface->writeNum = data->block[0] + 1;
438 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
440 iface->transPtr = data->block;
447 iface->manual_stop = 0;
448 iface->read_write = read_write;
449 iface->command = command;
450 iface->timeout_count = 10;
451 init_completion(&(iface->complete));
453 /* FIFO Initiation. Data in FIFO should be discarded before
454 * start a new operation.
456 write_FIFO_CTL(iface, 0x3);
458 write_FIFO_CTL(iface, 0);
461 write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
463 /* Set Transmit device address */
464 write_MASTER_ADDR(iface, addr);
467 iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
468 add_timer(&iface->timeout_timer);
470 switch (iface->cur_mode) {
471 case TWI_I2C_MODE_STANDARDSUB:
472 write_XMT_DATA8(iface, iface->command);
473 write_INT_MASK(iface, MCOMP | MERR |
474 ((iface->read_write == I2C_SMBUS_READ) ?
478 if (iface->writeNum + 1 <= 255)
479 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
481 write_MASTER_CTL(iface, 0xff << 6);
482 iface->manual_stop = 1;
485 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
486 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
488 case TWI_I2C_MODE_COMBINED:
489 write_XMT_DATA8(iface, iface->command);
490 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
493 if (iface->writeNum > 0)
494 write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
496 write_MASTER_CTL(iface, 0x1 << 6);
498 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
499 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
502 write_MASTER_CTL(iface, 0);
503 if (size != I2C_SMBUS_QUICK) {
504 /* Don't access xmit data register when this is a
507 if (iface->read_write != I2C_SMBUS_READ) {
508 if (iface->writeNum > 0) {
509 write_XMT_DATA8(iface,
510 *(iface->transPtr++));
511 if (iface->writeNum <= 255)
512 write_MASTER_CTL(iface,
513 iface->writeNum << 6);
515 write_MASTER_CTL(iface,
517 iface->manual_stop = 1;
521 write_XMT_DATA8(iface, iface->command);
522 write_MASTER_CTL(iface, 1 << 6);
525 if (iface->readNum > 0 && iface->readNum <= 255)
526 write_MASTER_CTL(iface,
527 iface->readNum << 6);
528 else if (iface->readNum > 255) {
529 write_MASTER_CTL(iface, 0xff << 6);
530 iface->manual_stop = 1;
532 del_timer(&iface->timeout_timer);
537 write_INT_MASK(iface, MCOMP | MERR |
538 ((iface->read_write == I2C_SMBUS_READ) ?
543 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
544 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
545 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
550 wait_for_completion(&iface->complete);
552 rc = (iface->result >= 0) ? 0 : -1;
558 * Return what the adapter supports
560 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
562 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
563 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
564 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
569 static struct i2c_algorithm bfin_twi_algorithm = {
570 .master_xfer = bfin_twi_master_xfer,
571 .smbus_xfer = bfin_twi_smbus_xfer,
572 .functionality = bfin_twi_functionality,
576 static int i2c_bfin_twi_suspend(struct platform_device *dev, pm_message_t state)
578 struct bfin_twi_iface *iface = platform_get_drvdata(dev);
581 write_CONTROL(iface, read_CONTROL(iface) & ~TWI_ENA);
587 static int i2c_bfin_twi_resume(struct platform_device *dev)
589 struct bfin_twi_iface *iface = platform_get_drvdata(dev);
592 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
598 static int i2c_bfin_twi_probe(struct platform_device *pdev)
600 struct bfin_twi_iface *iface;
601 struct i2c_adapter *p_adap;
602 struct resource *res;
605 iface = kzalloc(sizeof(struct bfin_twi_iface), GFP_KERNEL);
607 dev_err(&pdev->dev, "Cannot allocate memory\n");
609 goto out_error_nomem;
612 spin_lock_init(&(iface->lock));
614 /* Find and map our resources */
615 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
617 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
619 goto out_error_get_res;
622 iface->regs_base = ioremap(res->start, res->end - res->start + 1);
623 if (iface->regs_base == NULL) {
624 dev_err(&pdev->dev, "Cannot map IO\n");
626 goto out_error_ioremap;
629 iface->irq = platform_get_irq(pdev, 0);
630 if (iface->irq < 0) {
631 dev_err(&pdev->dev, "No IRQ specified\n");
633 goto out_error_no_irq;
636 init_timer(&(iface->timeout_timer));
637 iface->timeout_timer.function = bfin_twi_timeout;
638 iface->timeout_timer.data = (unsigned long)iface;
640 p_adap = &iface->adap;
641 p_adap->id = I2C_HW_BLACKFIN;
642 p_adap->nr = pdev->id;
643 strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
644 p_adap->algo = &bfin_twi_algorithm;
645 p_adap->algo_data = iface;
646 p_adap->class = I2C_CLASS_ALL;
647 p_adap->dev.parent = &pdev->dev;
649 rc = peripheral_request_list(pin_req[pdev->id], "i2c-bfin-twi");
651 dev_err(&pdev->dev, "Can't setup pin mux!\n");
652 goto out_error_pin_mux;
655 rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
656 IRQF_DISABLED, pdev->name, iface);
658 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
660 goto out_error_req_irq;
663 /* Set TWI internal clock as 10MHz */
664 write_CONTROL(iface, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
666 /* Set Twi interface clock as specified */
667 write_CLKDIV(iface, ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
668 << 8) | ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ)
672 write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
675 rc = i2c_add_numbered_adapter(p_adap);
677 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
678 goto out_error_add_adapter;
681 platform_set_drvdata(pdev, iface);
683 dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Contoller, "
684 "regs_base@%p\n", iface->regs_base);
688 out_error_add_adapter:
689 free_irq(iface->irq, iface);
692 peripheral_free_list(pin_req[pdev->id]);
694 iounmap(iface->regs_base);
702 static int i2c_bfin_twi_remove(struct platform_device *pdev)
704 struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
706 platform_set_drvdata(pdev, NULL);
708 i2c_del_adapter(&(iface->adap));
709 free_irq(iface->irq, iface);
710 peripheral_free_list(pin_req[pdev->id]);
711 iounmap(iface->regs_base);
717 static struct platform_driver i2c_bfin_twi_driver = {
718 .probe = i2c_bfin_twi_probe,
719 .remove = i2c_bfin_twi_remove,
720 .suspend = i2c_bfin_twi_suspend,
721 .resume = i2c_bfin_twi_resume,
723 .name = "i2c-bfin-twi",
724 .owner = THIS_MODULE,
728 static int __init i2c_bfin_twi_init(void)
730 return platform_driver_register(&i2c_bfin_twi_driver);
733 static void __exit i2c_bfin_twi_exit(void)
735 platform_driver_unregister(&i2c_bfin_twi_driver);
738 module_init(i2c_bfin_twi_init);
739 module_exit(i2c_bfin_twi_exit);
741 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
742 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
743 MODULE_LICENSE("GPL");
744 MODULE_ALIAS("platform:i2c-bfin-twi");