1 /* ------------------------------------------------------------------------- */
2 /* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
3 /* ------------------------------------------------------------------------- */
4 /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
5 * <Peter dot Milne at D hyphen TACQ dot com>
7 * With acknowledgements to i2c-algo-ibm_ocp.c by
8 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
10 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
12 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
14 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
15 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
17 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
19 * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
20 * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
21 * - Make it work with IXP46x chips
22 * - Cleanup function names, coding style, etc
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License as published by
26 * the Free Software Foundation, version 2.
29 #include <linux/interrupt.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <linux/init.h>
35 #include <linux/errno.h>
36 #include <linux/sched.h>
37 #include <linux/platform_device.h>
38 #include <linux/i2c.h>
42 #include "i2c-iop3xx.h"
44 /* global unit counter */
47 static inline unsigned char
48 iic_cook_addr(struct i2c_msg *msg)
52 addr = (msg->addr << 1);
54 if (msg->flags & I2C_M_RD)
60 if (msg->flags & I2C_M_REV_DIR_ADDR)
67 iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
69 /* Follows devman 9.3 */
70 __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
71 __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
72 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
76 iop3xx_i2c_set_slave_addr(struct i2c_algo_iop3xx_data *iop3xx_adap)
78 __raw_writel(MYSAR, iop3xx_adap->ioaddr + SAR_OFFSET);
82 iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
84 u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;
87 * Every time unit enable is asserted, GPOD needs to be cleared
88 * on IOP321 to avoid data corruption on the bus.
90 #ifdef CONFIG_ARCH_IOP321
91 #define IOP321_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */
92 #define IOP321_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */
94 *IOP321_GPOD &= (iop3xx_adap->id == 0) ? ~IOP321_GPOD_I2C0 :
97 /* NB SR bits not same position as CR IE bits :-( */
98 iop3xx_adap->SR_enabled =
99 IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
100 IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;
102 cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
103 IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE;
105 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
109 iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
111 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
113 cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
114 IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);
116 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
120 * NB: the handler has to clear the source of the interrupt!
121 * Then it passes the SR flags of interest to BH via adap data
124 iop3xx_i2c_irq_handler(int this_irq, void *dev_id, struct pt_regs *regs)
126 struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
127 u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
129 if ((sr &= iop3xx_adap->SR_enabled)) {
130 __raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
131 iop3xx_adap->SR_received |= sr;
132 wake_up_interruptible(&iop3xx_adap->waitq);
137 /* check all error conditions, clear them , report most important */
139 iop3xx_i2c_error(u32 sr)
143 if ((sr & IOP3XX_ISR_BERRD)) {
144 if ( !rc ) rc = -I2C_ERR_BERR;
146 if ((sr & IOP3XX_ISR_ALD)) {
147 if ( !rc ) rc = -I2C_ERR_ALD;
153 iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
158 spin_lock_irqsave(&iop3xx_adap->lock, flags);
159 sr = iop3xx_adap->SR_received;
160 iop3xx_adap->SR_received = 0;
161 spin_unlock_irqrestore(&iop3xx_adap->lock, flags);
167 * sleep until interrupted, then recover and analyse the SR
170 typedef int (* compare_func)(unsigned test, unsigned mask);
171 /* returns 1 on correct comparison */
174 iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
175 unsigned flags, unsigned* status,
176 compare_func compare)
184 interrupted = wait_event_interruptible_timeout (
186 (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
189 if ((rc = iop3xx_i2c_error(sr)) < 0) {
192 } else if (!interrupted) {
204 * Concrete compare_funcs
207 all_bits_clear(unsigned test, unsigned mask)
209 return (test & mask) == 0;
213 any_bits_set(unsigned test, unsigned mask)
215 return (test & mask) != 0;
219 iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
221 return iop3xx_i2c_wait_event(
223 IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
224 status, any_bits_set);
228 iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
230 return iop3xx_i2c_wait_event(
232 IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
233 status, any_bits_set);
237 iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
239 return iop3xx_i2c_wait_event(
240 iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
244 iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
247 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
251 __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
253 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
254 cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;
256 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
257 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
263 iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
266 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
270 __raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
271 cr &= ~IOP3XX_ICR_MSTART;
273 cr |= IOP3XX_ICR_MSTOP;
275 cr &= ~IOP3XX_ICR_MSTOP;
277 cr |= IOP3XX_ICR_TBYTE;
278 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
279 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
285 iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
288 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
292 cr &= ~IOP3XX_ICR_MSTART;
295 cr |= IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK;
297 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
299 cr |= IOP3XX_ICR_TBYTE;
300 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
302 rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);
304 *byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);
310 iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
312 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
316 for (ii = 0; rc == 0 && ii != count; ++ii)
317 rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
322 iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
324 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
328 for (ii = 0; rc == 0 && ii != count; ++ii)
329 rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
335 * Description: This function implements combined transactions. Combined
336 * transactions consist of combinations of reading and writing blocks of data.
337 * FROM THE SAME ADDRESS
338 * Each transfer (i.e. a read or a write) is separated by a repeated start
342 iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
344 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
347 rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
352 if ((pmsg->flags&I2C_M_RD)) {
353 return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
355 return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
360 * master_xfer() - main read/write entry
363 iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
366 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
371 iop3xx_i2c_wait_idle(iop3xx_adap, &status);
372 iop3xx_i2c_reset(iop3xx_adap);
373 iop3xx_i2c_enable(iop3xx_adap);
375 for (im = 0; ret == 0 && im != num; im++) {
376 ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
379 iop3xx_i2c_transaction_cleanup(iop3xx_adap);
388 iop3xx_i2c_algo_control(struct i2c_adapter *adapter, unsigned int cmd,
395 iop3xx_i2c_func(struct i2c_adapter *adap)
397 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
400 static struct i2c_algorithm iop3xx_i2c_algo = {
401 .master_xfer = iop3xx_i2c_master_xfer,
402 .algo_control = iop3xx_i2c_algo_control,
403 .functionality = iop3xx_i2c_func,
407 iop3xx_i2c_remove(struct platform_device *pdev)
409 struct i2c_adapter *padapter = platform_get_drvdata(pdev);
410 struct i2c_algo_iop3xx_data *adapter_data =
411 (struct i2c_algo_iop3xx_data *)padapter->algo_data;
412 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
413 unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
416 * Disable the actual HW unit
418 cr &= ~(IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
419 IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE);
420 __raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
422 iounmap((void __iomem*)adapter_data->ioaddr);
423 release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
427 platform_set_drvdata(pdev, NULL);
433 iop3xx_i2c_probe(struct platform_device *pdev)
435 struct resource *res;
437 struct i2c_adapter *new_adapter;
438 struct i2c_algo_iop3xx_data *adapter_data;
440 new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
446 adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
452 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
458 if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
463 /* set the adapter enumeration # */
464 adapter_data->id = i2c_id++;
466 adapter_data->ioaddr = (u32)ioremap(res->start, IOP3XX_I2C_IO_SIZE);
467 if (!adapter_data->ioaddr) {
472 irq = platform_get_irq(pdev, 0);
477 ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
478 pdev->name, adapter_data);
485 memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
486 new_adapter->id = I2C_HW_IOP3XX;
487 new_adapter->owner = THIS_MODULE;
488 new_adapter->dev.parent = &pdev->dev;
491 * Default values...should these come in from board code?
493 new_adapter->timeout = 100;
494 new_adapter->retries = 3;
495 new_adapter->algo = &iop3xx_i2c_algo;
497 init_waitqueue_head(&adapter_data->waitq);
498 spin_lock_init(&adapter_data->lock);
500 iop3xx_i2c_reset(adapter_data);
501 iop3xx_i2c_set_slave_addr(adapter_data);
502 iop3xx_i2c_enable(adapter_data);
504 platform_set_drvdata(pdev, new_adapter);
505 new_adapter->algo_data = adapter_data;
507 i2c_add_adapter(new_adapter);
512 iounmap((void __iomem*)adapter_data->ioaddr);
515 release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
528 static struct platform_driver iop3xx_i2c_driver = {
529 .probe = iop3xx_i2c_probe,
530 .remove = iop3xx_i2c_remove,
532 .owner = THIS_MODULE,
533 .name = "IOP3xx-I2C",
538 i2c_iop3xx_init (void)
540 return platform_driver_register(&iop3xx_i2c_driver);
544 i2c_iop3xx_exit (void)
546 platform_driver_unregister(&iop3xx_i2c_driver);
550 module_init (i2c_iop3xx_init);
551 module_exit (i2c_iop3xx_exit);
553 MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
554 MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
555 MODULE_LICENSE("GPL");