2 * TI OMAP I2C master mode driver
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
41 /* I2C controller revisions */
42 #define OMAP_I2C_REV_2 0x20
44 /* I2C controller revisions present on specific hardware */
45 #define OMAP_I2C_REV_ON_2430 0x36
46 #define OMAP_I2C_REV_ON_3430 0x3C
48 /* timeout waiting for the controller to respond */
49 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
51 #define OMAP_I2C_REV_REG 0x00
52 #define OMAP_I2C_IE_REG 0x04
53 #define OMAP_I2C_STAT_REG 0x08
54 #define OMAP_I2C_IV_REG 0x0c
55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56 #define OMAP_I2C_WE_REG 0x0c
57 #define OMAP_I2C_SYSS_REG 0x10
58 #define OMAP_I2C_BUF_REG 0x14
59 #define OMAP_I2C_CNT_REG 0x18
60 #define OMAP_I2C_DATA_REG 0x1c
61 #define OMAP_I2C_SYSC_REG 0x20
62 #define OMAP_I2C_CON_REG 0x24
63 #define OMAP_I2C_OA_REG 0x28
64 #define OMAP_I2C_SA_REG 0x2c
65 #define OMAP_I2C_PSC_REG 0x30
66 #define OMAP_I2C_SCLL_REG 0x34
67 #define OMAP_I2C_SCLH_REG 0x38
68 #define OMAP_I2C_SYSTEST_REG 0x3c
69 #define OMAP_I2C_BUFSTAT_REG 0x40
71 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
72 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
73 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
74 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
75 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
76 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
77 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
78 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
80 /* I2C Status Register (OMAP_I2C_STAT): */
81 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
82 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
83 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
84 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
85 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
86 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
87 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
88 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
89 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
90 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
91 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
92 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
94 /* I2C WE wakeup enable register */
95 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
96 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
97 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
98 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
99 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
100 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
101 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
102 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
103 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
104 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
106 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
107 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
108 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
109 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
110 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
112 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
113 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
114 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
115 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
116 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
118 /* I2C Configuration Register (OMAP_I2C_CON): */
119 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
120 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
121 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
122 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
123 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
124 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
125 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
126 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
127 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
128 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
130 /* I2C SCL time value when Master */
131 #define OMAP_I2C_SCLL_HSSCLL 8
132 #define OMAP_I2C_SCLH_HSSCLH 8
134 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
136 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
137 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
138 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
139 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
140 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
141 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
142 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
143 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
146 /* OCP_SYSSTATUS bit definitions */
147 #define SYSS_RESETDONE_MASK (1 << 0)
149 /* OCP_SYSCONFIG bit definitions */
150 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
151 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
152 #define SYSC_ENAWAKEUP_MASK (1 << 2)
153 #define SYSC_SOFTRESET_MASK (1 << 1)
154 #define SYSC_AUTOIDLE_MASK (1 << 0)
156 #define SYSC_IDLEMODE_SMART 0x2
157 #define SYSC_CLOCKACTIVITY_FCLK 0x2
160 struct omap_i2c_dev {
162 void __iomem *base; /* virtual */
164 struct clk *iclk; /* Interface clock */
165 struct clk *fclk; /* Functional clock */
166 struct completion cmd_complete;
167 struct resource *ioarea;
168 u32 speed; /* Speed of bus in Khz */
172 struct i2c_adapter adapter;
173 u8 fifo_size; /* use as flag and value
174 * fifo_size==0 implies no fifo
175 * if set, should be trsh+1
178 unsigned b_hw:1; /* bad h/w fixes */
180 u16 iestate; /* Saved interrupt register */
183 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
186 __raw_writew(val, i2c_dev->base + reg);
189 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
191 return __raw_readw(i2c_dev->base + reg);
194 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
196 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
197 dev->iclk = clk_get(dev->dev, "i2c_ick");
198 if (IS_ERR(dev->iclk)) {
204 dev->fclk = clk_get(dev->dev, "i2c_fck");
205 if (IS_ERR(dev->fclk)) {
206 if (dev->iclk != NULL) {
217 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
221 if (dev->iclk != NULL) {
227 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
231 if (dev->iclk != NULL)
232 clk_enable(dev->iclk);
233 clk_enable(dev->fclk);
236 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
239 static void omap_i2c_idle(struct omap_i2c_dev *dev)
245 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
246 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
247 if (dev->rev < OMAP_I2C_REV_2) {
248 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
250 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
252 /* Flush posted write before the dev->idle store occurs */
253 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
256 clk_disable(dev->fclk);
257 if (dev->iclk != NULL)
258 clk_disable(dev->iclk);
261 static int omap_i2c_init(struct omap_i2c_dev *dev)
263 u16 psc = 0, scll = 0, sclh = 0;
264 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
265 unsigned long fclk_rate = 12000000;
266 unsigned long timeout;
267 unsigned long internal_clk = 0;
269 if (dev->rev >= OMAP_I2C_REV_2) {
270 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
271 /* For some reason we need to set the EN bit before the
272 * reset done bit gets set. */
273 timeout = jiffies + OMAP_I2C_TIMEOUT;
274 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
275 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
276 SYSS_RESETDONE_MASK)) {
277 if (time_after(jiffies, timeout)) {
278 dev_warn(dev->dev, "timeout waiting "
279 "for controller reset\n");
285 /* SYSC register is cleared by the reset; rewrite it */
286 if (dev->rev == OMAP_I2C_REV_ON_2430) {
288 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
291 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
294 v = SYSC_AUTOIDLE_MASK;
295 v |= SYSC_ENAWAKEUP_MASK;
296 v |= (SYSC_IDLEMODE_SMART <<
297 __ffs(SYSC_SIDLEMODE_MASK));
298 v |= (SYSC_CLOCKACTIVITY_FCLK <<
299 __ffs(SYSC_CLOCKACTIVITY_MASK));
301 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, v);
303 * Enabling all wakup sources to stop I2C freezing on
305 * REVISIT: Some wkup sources might not be needed.
307 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
312 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
314 if (cpu_class_is_omap1()) {
315 struct clk *armxor_ck;
317 armxor_ck = clk_get(NULL, "armxor_ck");
318 if (IS_ERR(armxor_ck))
319 dev_warn(dev->dev, "Could not get armxor_ck\n");
321 fclk_rate = clk_get_rate(armxor_ck);
324 /* TRM for 5912 says the I2C clock must be prescaled to be
325 * between 7 - 12 MHz. The XOR input clock is typically
326 * 12, 13 or 19.2 MHz. So we should have code that produces:
328 * XOR MHz Divider Prescaler
333 if (fclk_rate > 12000000)
334 psc = fclk_rate / 12000000;
337 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
339 /* HSI2C controller internal clk rate should be 19.2 Mhz */
340 if (dev->speed > 400)
341 internal_clk = 19200;
342 else if (dev->speed > 100)
347 fclk_rate = clk_get_rate(dev->fclk) / 1000;
349 /* Compute prescaler divisor */
350 psc = fclk_rate / internal_clk;
353 /* If configured for High Speed */
354 if (dev->speed > 400) {
355 /* For first phase of HS mode */
356 fsscll = internal_clk / (400 * 2) - 6;
357 fssclh = internal_clk / (400 * 2) - 6;
359 /* For second phase of HS mode */
360 hsscll = fclk_rate / (dev->speed * 2) - 6;
361 hssclh = fclk_rate / (dev->speed * 2) - 6;
363 /* To handle F/S modes */
364 fsscll = internal_clk / (dev->speed * 2) - 3;
365 fssclh = internal_clk / (dev->speed * 2) - 9;
367 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
368 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
370 /* Program desired operating rate */
371 fclk_rate /= (psc + 1) * 1000;
374 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
375 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
378 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
379 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
381 /* SCL low and high time values */
382 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
383 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
386 /* Note: setup required fifo size - 1 */
387 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
388 (dev->fifo_size - 1) << 8 | /* RTRSH */
389 OMAP_I2C_BUF_RXFIF_CLR |
390 (dev->fifo_size - 1) | /* XTRSH */
391 OMAP_I2C_BUF_TXFIF_CLR);
393 /* Take the I2C module out of reset: */
394 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
396 /* Enable interrupts */
397 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
398 (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
399 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
400 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
401 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
406 * Waiting on Bus Busy
408 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
410 unsigned long timeout;
412 timeout = jiffies + OMAP_I2C_TIMEOUT;
413 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
414 if (time_after(jiffies, timeout)) {
415 dev_warn(dev->dev, "timeout waiting for bus ready\n");
425 * Low level master read/write transaction.
427 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
428 struct i2c_msg *msg, int stop)
430 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
434 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
435 msg->addr, msg->len, msg->flags, stop);
440 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
442 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
444 dev->buf_len = msg->len;
446 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
448 /* Clear the FIFO Buffers */
449 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
450 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
451 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
453 init_completion(&dev->cmd_complete);
456 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
458 /* High speed configuration */
459 if (dev->speed > 400)
460 w |= OMAP_I2C_CON_OPMODE_HS;
462 if (msg->flags & I2C_M_TEN)
463 w |= OMAP_I2C_CON_XA;
464 if (!(msg->flags & I2C_M_RD))
465 w |= OMAP_I2C_CON_TRX;
467 if (!dev->b_hw && stop)
468 w |= OMAP_I2C_CON_STP;
470 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
473 * Don't write stt and stp together on some hardware.
475 if (dev->b_hw && stop) {
476 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
477 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
478 while (con & OMAP_I2C_CON_STT) {
479 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
481 /* Let the user know if i2c is in a bad state */
482 if (time_after(jiffies, delay)) {
483 dev_err(dev->dev, "controller timed out "
484 "waiting for start condition to finish\n");
490 w |= OMAP_I2C_CON_STP;
491 w &= ~OMAP_I2C_CON_STT;
492 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
496 * REVISIT: We should abort the transfer on signals, but the bus goes
497 * into arbitration and we're currently unable to recover from it.
499 r = wait_for_completion_timeout(&dev->cmd_complete,
505 dev_err(dev->dev, "controller timed out\n");
510 if (likely(!dev->cmd_err))
513 /* We have an error */
514 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
515 OMAP_I2C_STAT_XUDF)) {
520 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
521 if (msg->flags & I2C_M_IGNORE_NAK)
524 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
525 w |= OMAP_I2C_CON_STP;
526 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
535 * Prepare controller for a transaction and call omap_i2c_xfer_msg
536 * to do the work during IRQ processing.
539 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
541 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
545 omap_i2c_unidle(dev);
547 r = omap_i2c_wait_for_bb(dev);
551 for (i = 0; i < num; i++) {
552 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
565 omap_i2c_func(struct i2c_adapter *adap)
567 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
571 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
574 complete(&dev->cmd_complete);
578 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
580 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
583 /* rev1 devices are apparently only on some 15xx */
584 #ifdef CONFIG_ARCH_OMAP15XX
587 omap_i2c_rev1_isr(int this_irq, void *dev_id)
589 struct omap_i2c_dev *dev = dev_id;
595 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
597 case 0x00: /* None */
599 case 0x01: /* Arbitration lost */
600 dev_err(dev->dev, "Arbitration lost\n");
601 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
603 case 0x02: /* No acknowledgement */
604 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
605 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
607 case 0x03: /* Register access ready */
608 omap_i2c_complete_cmd(dev, 0);
610 case 0x04: /* Receive data ready */
612 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
616 *dev->buf++ = w >> 8;
620 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
622 case 0x05: /* Transmit data ready */
627 w |= *dev->buf++ << 8;
630 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
632 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
641 #define omap_i2c_rev1_isr NULL
645 omap_i2c_isr(int this_irq, void *dev_id)
647 struct omap_i2c_dev *dev = dev_id;
655 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
656 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
657 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
658 if (count++ == 100) {
659 dev_warn(dev->dev, "Too much work in one IRQ\n");
663 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
666 if (stat & OMAP_I2C_STAT_NACK) {
667 err |= OMAP_I2C_STAT_NACK;
668 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
671 if (stat & OMAP_I2C_STAT_AL) {
672 dev_err(dev->dev, "Arbitration lost\n");
673 err |= OMAP_I2C_STAT_AL;
675 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
677 omap_i2c_complete_cmd(dev, err);
678 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
680 if (dev->fifo_size) {
681 if (stat & OMAP_I2C_STAT_RRDY)
682 num_bytes = dev->fifo_size;
684 num_bytes = (omap_i2c_read_reg(dev,
685 OMAP_I2C_BUFSTAT_REG)
690 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
694 /* Data reg from 2430 is 8 bit wide */
695 if (!cpu_is_omap2430() &&
696 !cpu_is_omap34xx()) {
698 *dev->buf++ = w >> 8;
703 if (stat & OMAP_I2C_STAT_RRDY)
705 "RRDY IRQ while no data"
707 if (stat & OMAP_I2C_STAT_RDR)
709 "RDR IRQ while no data"
714 omap_i2c_ack_stat(dev,
715 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
718 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
720 if (dev->fifo_size) {
721 if (stat & OMAP_I2C_STAT_XRDY)
722 num_bytes = dev->fifo_size;
724 num_bytes = (omap_i2c_read_reg(dev,
725 OMAP_I2C_BUFSTAT_REG))
734 /* Data reg from 2430 is 8 bit wide */
735 if (!cpu_is_omap2430() &&
736 !cpu_is_omap34xx()) {
738 w |= *dev->buf++ << 8;
743 if (stat & OMAP_I2C_STAT_XRDY)
747 if (stat & OMAP_I2C_STAT_XDR)
753 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
755 omap_i2c_ack_stat(dev,
756 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
759 if (stat & OMAP_I2C_STAT_ROVR) {
760 dev_err(dev->dev, "Receive overrun\n");
761 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
763 if (stat & OMAP_I2C_STAT_XUDF) {
764 dev_err(dev->dev, "Transmit underflow\n");
765 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
769 return count ? IRQ_HANDLED : IRQ_NONE;
772 static const struct i2c_algorithm omap_i2c_algo = {
773 .master_xfer = omap_i2c_xfer,
774 .functionality = omap_i2c_func,
778 omap_i2c_probe(struct platform_device *pdev)
780 struct omap_i2c_dev *dev;
781 struct i2c_adapter *adap;
782 struct resource *mem, *irq, *ioarea;
787 /* NOTE: driver uses the static register mapping */
788 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
790 dev_err(&pdev->dev, "no mem resource?\n");
793 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
795 dev_err(&pdev->dev, "no irq resource?\n");
799 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
802 dev_err(&pdev->dev, "I2C region already claimed\n");
806 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
809 goto err_release_region;
812 if (pdev->dev.platform_data != NULL)
813 speed = *(u32 *)pdev->dev.platform_data;
815 speed = 100; /* Defualt speed */
819 dev->dev = &pdev->dev;
820 dev->irq = irq->start;
821 dev->base = ioremap(mem->start, mem->end - mem->start + 1);
827 platform_set_drvdata(pdev, dev);
829 if ((r = omap_i2c_get_clocks(dev)) != 0)
832 omap_i2c_unidle(dev);
834 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
836 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
839 /* Set up the fifo size - Get total size */
840 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
841 dev->fifo_size = 0x8 << s;
844 * Set up notification threshold as half the total available
845 * size. This is to ensure that we can handle the status on int
846 * call back latencies.
848 dev->fifo_size = (dev->fifo_size / 2);
849 dev->b_hw = 1; /* Enable hardware fixes */
852 /* reset ASAP, clearing any IRQs */
855 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
856 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
859 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
860 goto err_unuse_clocks;
863 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
864 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
868 adap = &dev->adapter;
869 i2c_set_adapdata(adap, dev);
870 adap->owner = THIS_MODULE;
871 adap->class = I2C_CLASS_HWMON;
872 strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
873 adap->algo = &omap_i2c_algo;
874 adap->dev.parent = &pdev->dev;
876 /* i2c device drivers may be active on return from add_adapter() */
878 r = i2c_add_numbered_adapter(adap);
880 dev_err(dev->dev, "failure adding adapter\n");
887 free_irq(dev->irq, dev);
889 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
891 omap_i2c_put_clocks(dev);
895 platform_set_drvdata(pdev, NULL);
898 release_mem_region(mem->start, (mem->end - mem->start) + 1);
904 omap_i2c_remove(struct platform_device *pdev)
906 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
907 struct resource *mem;
909 platform_set_drvdata(pdev, NULL);
911 free_irq(dev->irq, dev);
912 i2c_del_adapter(&dev->adapter);
913 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
914 omap_i2c_put_clocks(dev);
917 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
918 release_mem_region(mem->start, (mem->end - mem->start) + 1);
922 static struct platform_driver omap_i2c_driver = {
923 .probe = omap_i2c_probe,
924 .remove = omap_i2c_remove,
927 .owner = THIS_MODULE,
931 /* I2C may be needed to bring up other drivers */
933 omap_i2c_init_driver(void)
935 return platform_driver_register(&omap_i2c_driver);
937 subsys_initcall(omap_i2c_init_driver);
939 static void __exit omap_i2c_exit_driver(void)
941 platform_driver_unregister(&omap_i2c_driver);
943 module_exit(omap_i2c_exit_driver);
945 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
946 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
947 MODULE_LICENSE("GPL");
948 MODULE_ALIAS("platform:i2c_omap");