2 piix4.c - Part of lm_sensors, Linux kernel modules for hardware
4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
5 Philip Edelbrock <phil@netroedge.com>
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Serverworks OSB4, CSB5, CSB6, HT-1000
26 ATI IXP200, IXP300, IXP400, SB600, SB700, SB800
29 Note: we assume there can only be one device, with one SMBus interface.
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/pci.h>
35 #include <linux/kernel.h>
36 #include <linux/delay.h>
37 #include <linux/stddef.h>
38 #include <linux/ioport.h>
39 #include <linux/i2c.h>
40 #include <linux/init.h>
41 #include <linux/dmi.h>
45 /* PIIX4 SMBus address offsets */
46 #define SMBHSTSTS (0 + piix4_smba)
47 #define SMBHSLVSTS (1 + piix4_smba)
48 #define SMBHSTCNT (2 + piix4_smba)
49 #define SMBHSTCMD (3 + piix4_smba)
50 #define SMBHSTADD (4 + piix4_smba)
51 #define SMBHSTDAT0 (5 + piix4_smba)
52 #define SMBHSTDAT1 (6 + piix4_smba)
53 #define SMBBLKDAT (7 + piix4_smba)
54 #define SMBSLVCNT (8 + piix4_smba)
55 #define SMBSHDWCMD (9 + piix4_smba)
56 #define SMBSLVEVT (0xA + piix4_smba)
57 #define SMBSLVDAT (0xC + piix4_smba)
59 /* count for request_region */
62 /* PCI Address Constants */
64 #define SMBHSTCFG 0x0D2
66 #define SMBSHDW1 0x0D4
67 #define SMBSHDW2 0x0D5
71 #define MAX_TIMEOUT 500
75 #define PIIX4_QUICK 0x00
76 #define PIIX4_BYTE 0x04
77 #define PIIX4_BYTE_DATA 0x08
78 #define PIIX4_WORD_DATA 0x0C
79 #define PIIX4_BLOCK_DATA 0x14
81 /* insmod parameters */
83 /* If force is set to anything different from 0, we forcibly enable the
86 module_param (force, int, 0);
87 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
89 /* If force_addr is set to anything different from 0, we forcibly enable
90 the PIIX4 at the given address. VERY DANGEROUS! */
91 static int force_addr;
92 module_param (force_addr, int, 0);
93 MODULE_PARM_DESC(force_addr,
94 "Forcibly enable the PIIX4 at the given address. "
95 "EXTREMELY DANGEROUS!");
97 static unsigned short piix4_smba;
98 static int srvrworks_csb5_delay;
99 static struct pci_driver piix4_driver;
100 static struct i2c_adapter piix4_adapter;
102 static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = {
104 .ident = "Sapphire AM2RD790",
106 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
107 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
111 .ident = "DFI Lanparty UT 790FX",
113 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
114 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
120 /* The IBM entry is in a separate table because we only check it
121 on Intel-based systems */
122 static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = {
125 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
130 static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
131 const struct pci_device_id *id)
135 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
136 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
137 srvrworks_csb5_delay = 1;
139 /* On some motherboards, it was reported that accessing the SMBus
140 caused severe hardware problems */
141 if (dmi_check_system(piix4_dmi_blacklist)) {
142 dev_err(&PIIX4_dev->dev,
143 "Accessing the SMBus on this system is unsafe!\n");
147 /* Don't access SMBus on IBM systems which get corrupted eeproms */
148 if (dmi_check_system(piix4_dmi_ibm) &&
149 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
150 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
151 "may corrupt your serial eeprom! Refusing to load "
156 /* Determine the address of the SMBus areas */
158 piix4_smba = force_addr & 0xfff0;
161 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
162 piix4_smba &= 0xfff0;
163 if(piix4_smba == 0) {
164 dev_err(&PIIX4_dev->dev, "SMBus base address "
165 "uninitialized - upgrade BIOS or use "
166 "force_addr=0xaddr\n");
171 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
172 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
177 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
179 /* If force_addr is set, we program the new address here. Just to make
180 sure, we disable the PIIX4 first. */
182 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
183 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
184 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
185 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
186 "new address %04x!\n", piix4_smba);
187 } else if ((temp & 1) == 0) {
189 /* This should never need to be done, but has been
190 * noted that many Dell machines have the SMBus
191 * interface on the PIIX4 disabled!? NOTE: This assumes
192 * I/O space and other allocations WERE done by the
193 * Bios! Don't complain if your hardware does weird
194 * things after enabling this. :') Check for Bios
195 * updates before resorting to this.
197 pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
199 dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
200 "WARNING: SMBus interface has been "
201 "FORCEFULLY ENABLED!\n");
203 dev_err(&PIIX4_dev->dev,
204 "Host SMBus controller not enabled!\n");
205 release_region(piix4_smba, SMBIOSIZE);
211 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
212 dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
213 else if ((temp & 0x0E) == 0)
214 dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
216 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
217 "(or code out of date)!\n");
219 pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
220 dev_info(&PIIX4_dev->dev,
221 "SMBus Host Controller at 0x%x, revision %d\n",
227 static int piix4_transaction(void)
233 dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
234 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
235 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
238 /* Make sure the SMBus host is ready to start transmitting */
239 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
240 dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). "
241 "Resetting...\n", temp);
242 outb_p(temp, SMBHSTSTS);
243 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
244 dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp);
247 dev_dbg(&piix4_adapter.dev, "Successful!\n");
251 /* start the transaction by setting bit 6 */
252 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
254 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
255 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
260 while ((timeout++ < MAX_TIMEOUT) &&
261 ((temp = inb_p(SMBHSTSTS)) & 0x01))
264 /* If the SMBus is still busy, we give up */
265 if (timeout >= MAX_TIMEOUT) {
266 dev_err(&piix4_adapter.dev, "SMBus Timeout!\n");
272 dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n");
277 dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be "
278 "locked until next hard reset. (sorry!)\n");
279 /* Clock stops and slave is stuck in mid-transmission */
284 dev_dbg(&piix4_adapter.dev, "Error: no response!\n");
287 if (inb_p(SMBHSTSTS) != 0x00)
288 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
290 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
291 dev_err(&piix4_adapter.dev, "Failed reset at end of "
292 "transaction (%02x)\n", temp);
294 dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
295 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
296 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
301 /* Return negative errno on error. */
302 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
303 unsigned short flags, char read_write,
304 u8 command, int size, union i2c_smbus_data * data)
310 case I2C_SMBUS_QUICK:
311 outb_p((addr << 1) | read_write,
316 outb_p((addr << 1) | read_write,
318 if (read_write == I2C_SMBUS_WRITE)
319 outb_p(command, SMBHSTCMD);
322 case I2C_SMBUS_BYTE_DATA:
323 outb_p((addr << 1) | read_write,
325 outb_p(command, SMBHSTCMD);
326 if (read_write == I2C_SMBUS_WRITE)
327 outb_p(data->byte, SMBHSTDAT0);
328 size = PIIX4_BYTE_DATA;
330 case I2C_SMBUS_WORD_DATA:
331 outb_p((addr << 1) | read_write,
333 outb_p(command, SMBHSTCMD);
334 if (read_write == I2C_SMBUS_WRITE) {
335 outb_p(data->word & 0xff, SMBHSTDAT0);
336 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
338 size = PIIX4_WORD_DATA;
340 case I2C_SMBUS_BLOCK_DATA:
341 outb_p((addr << 1) | read_write,
343 outb_p(command, SMBHSTCMD);
344 if (read_write == I2C_SMBUS_WRITE) {
345 len = data->block[0];
346 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
348 outb_p(len, SMBHSTDAT0);
349 i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
350 for (i = 1; i <= len; i++)
351 outb_p(data->block[i], SMBBLKDAT);
353 size = PIIX4_BLOCK_DATA;
356 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
360 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
362 status = piix4_transaction();
366 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
372 case PIIX4_BYTE_DATA:
373 data->byte = inb_p(SMBHSTDAT0);
375 case PIIX4_WORD_DATA:
376 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
378 case PIIX4_BLOCK_DATA:
379 data->block[0] = inb_p(SMBHSTDAT0);
380 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
382 i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
383 for (i = 1; i <= data->block[0]; i++)
384 data->block[i] = inb_p(SMBBLKDAT);
390 static u32 piix4_func(struct i2c_adapter *adapter)
392 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
393 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
394 I2C_FUNC_SMBUS_BLOCK_DATA;
397 static const struct i2c_algorithm smbus_algorithm = {
398 .smbus_xfer = piix4_access,
399 .functionality = piix4_func,
402 static struct i2c_adapter piix4_adapter = {
403 .owner = THIS_MODULE,
404 .id = I2C_HW_SMBUS_PIIX4,
405 .class = I2C_CLASS_HWMON,
406 .algo = &smbus_algorithm,
409 static struct pci_device_id piix4_ids[] = {
410 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
411 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
412 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
413 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
414 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
415 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
416 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
417 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
418 PCI_DEVICE_ID_SERVERWORKS_OSB4) },
419 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
420 PCI_DEVICE_ID_SERVERWORKS_CSB5) },
421 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
422 PCI_DEVICE_ID_SERVERWORKS_CSB6) },
423 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
424 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
428 MODULE_DEVICE_TABLE (pci, piix4_ids);
430 static int __devinit piix4_probe(struct pci_dev *dev,
431 const struct pci_device_id *id)
435 retval = piix4_setup(dev, id);
439 /* set up the sysfs linkage to our parent device */
440 piix4_adapter.dev.parent = &dev->dev;
442 snprintf(piix4_adapter.name, sizeof(piix4_adapter.name),
443 "SMBus PIIX4 adapter at %04x", piix4_smba);
445 if ((retval = i2c_add_adapter(&piix4_adapter))) {
446 dev_err(&dev->dev, "Couldn't register adapter!\n");
447 release_region(piix4_smba, SMBIOSIZE);
454 static void __devexit piix4_remove(struct pci_dev *dev)
457 i2c_del_adapter(&piix4_adapter);
458 release_region(piix4_smba, SMBIOSIZE);
463 static struct pci_driver piix4_driver = {
464 .name = "piix4_smbus",
465 .id_table = piix4_ids,
466 .probe = piix4_probe,
467 .remove = __devexit_p(piix4_remove),
470 static int __init i2c_piix4_init(void)
472 return pci_register_driver(&piix4_driver);
475 static void __exit i2c_piix4_exit(void)
477 pci_unregister_driver(&piix4_driver);
480 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
481 "Philip Edelbrock <phil@netroedge.com>");
482 MODULE_DESCRIPTION("PIIX4 SMBus driver");
483 MODULE_LICENSE("GPL");
485 module_init(i2c_piix4_init);
486 module_exit(i2c_piix4_exit);