2 * linux/drivers/ide/mips/au1xxx-ide.c version 01.30.00 Aug. 02 2005
4 * BRIEF MODULE DESCRIPTION
5 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
7 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
9 * This program is free software; you can redistribute it and/or modify it under
10 * the terms of the GNU General Public License as published by the Free Software
11 * Foundation; either version 2 of the License, or (at your option) any later
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23 * POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along with
26 * this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30 * Interface and Linux Device Driver" Application Note.
32 #include <linux/types.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/platform_device.h>
38 #include <linux/init.h>
39 #include <linux/ide.h>
40 #include <linux/sysdev.h>
42 #include <linux/dma-mapping.h>
44 #include "ide-timing.h"
47 #include <asm/mach-au1x00/au1xxx.h>
48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
50 #include <asm/mach-au1x00/au1xxx_ide.h>
52 #define DRV_NAME "au1200-ide"
53 #define DRV_VERSION "1.0"
54 #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
56 /* enable the burstmode in the dbdma */
57 #define IDE_AU1XXX_BURSTMODE 1
59 static _auide_hwif auide_hwif;
60 static int dbdma_init_done;
62 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
64 void auide_insw(unsigned long port, void *addr, u32 count)
66 _auide_hwif *ahwif = &auide_hwif;
70 if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
72 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
75 ctp = *((chan_tab_t **)ahwif->rx_chan);
77 while (dp->dscr_cmd0 & DSCR_CMD0_V)
79 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
82 void auide_outsw(unsigned long port, void *addr, u32 count)
84 _auide_hwif *ahwif = &auide_hwif;
88 if(!put_source_flags(ahwif->tx_chan, (void*)addr,
89 count << 1, DDMA_FLAGS_NOIE)) {
90 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
93 ctp = *((chan_tab_t **)ahwif->tx_chan);
95 while (dp->dscr_cmd0 & DSCR_CMD0_V)
97 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
104 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
109 mem_sttime = SBC_IDE_TIMING(PIO0);
111 /* set configuration for RCS2# */
112 mem_stcfg |= TS_MASK;
113 mem_stcfg &= ~TCSOE_MASK;
114 mem_stcfg &= ~TOECS_MASK;
115 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
119 mem_sttime = SBC_IDE_TIMING(PIO1);
121 /* set configuration for RCS2# */
122 mem_stcfg |= TS_MASK;
123 mem_stcfg &= ~TCSOE_MASK;
124 mem_stcfg &= ~TOECS_MASK;
125 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
129 mem_sttime = SBC_IDE_TIMING(PIO2);
131 /* set configuration for RCS2# */
132 mem_stcfg &= ~TS_MASK;
133 mem_stcfg &= ~TCSOE_MASK;
134 mem_stcfg &= ~TOECS_MASK;
135 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
139 mem_sttime = SBC_IDE_TIMING(PIO3);
141 /* set configuration for RCS2# */
142 mem_stcfg &= ~TS_MASK;
143 mem_stcfg &= ~TCSOE_MASK;
144 mem_stcfg &= ~TOECS_MASK;
145 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
150 mem_sttime = SBC_IDE_TIMING(PIO4);
152 /* set configuration for RCS2# */
153 mem_stcfg &= ~TS_MASK;
154 mem_stcfg &= ~TCSOE_MASK;
155 mem_stcfg &= ~TOECS_MASK;
156 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
160 au_writel(mem_sttime,MEM_STTIME2);
161 au_writel(mem_stcfg,MEM_STCFG2);
164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
166 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
171 mem_sttime = SBC_IDE_TIMING(MDMA2);
173 /* set configuration for RCS2# */
174 mem_stcfg &= ~TS_MASK;
175 mem_stcfg &= ~TCSOE_MASK;
176 mem_stcfg &= ~TOECS_MASK;
177 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
181 mem_sttime = SBC_IDE_TIMING(MDMA1);
183 /* set configuration for RCS2# */
184 mem_stcfg &= ~TS_MASK;
185 mem_stcfg &= ~TCSOE_MASK;
186 mem_stcfg &= ~TOECS_MASK;
187 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
191 mem_sttime = SBC_IDE_TIMING(MDMA0);
193 /* set configuration for RCS2# */
194 mem_stcfg |= TS_MASK;
195 mem_stcfg &= ~TCSOE_MASK;
196 mem_stcfg &= ~TOECS_MASK;
197 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
205 au_writel(mem_sttime,MEM_STTIME2);
206 au_writel(mem_stcfg,MEM_STCFG2);
210 * Multi-Word DMA + DbDMA functions
213 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
215 static int auide_build_sglist(ide_drive_t *drive, struct request *rq)
217 ide_hwif_t *hwif = drive->hwif;
218 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
219 struct scatterlist *sg = hwif->sg_table;
221 ide_map_sg(drive, rq);
223 if (rq_data_dir(rq) == READ)
224 hwif->sg_dma_direction = DMA_FROM_DEVICE;
226 hwif->sg_dma_direction = DMA_TO_DEVICE;
228 return dma_map_sg(ahwif->dev, sg, hwif->sg_nents,
229 hwif->sg_dma_direction);
232 static int auide_build_dmatable(ide_drive_t *drive)
234 int i, iswrite, count = 0;
235 ide_hwif_t *hwif = HWIF(drive);
237 struct request *rq = HWGROUP(drive)->rq;
239 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
240 struct scatterlist *sg;
242 iswrite = (rq_data_dir(rq) == WRITE);
243 /* Save for interrupt context */
244 ahwif->drive = drive;
247 hwif->sg_nents = i = auide_build_sglist(drive, rq);
252 /* fill the descriptors */
254 while (i && sg_dma_len(sg)) {
258 cur_addr = sg_dma_address(sg);
259 cur_len = sg_dma_len(sg);
262 u32 flags = DDMA_FLAGS_NOIE;
263 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
265 if (++count >= PRD_ENTRIES) {
266 printk(KERN_WARNING "%s: DMA table too small\n",
268 goto use_pio_instead;
271 /* Lets enable intr for the last descriptor only */
273 flags = DDMA_FLAGS_IE;
275 flags = DDMA_FLAGS_NOIE;
278 if(!put_source_flags(ahwif->tx_chan,
279 (void*)(page_address(sg->page)
282 printk(KERN_ERR "%s failed %d\n",
283 __FUNCTION__, __LINE__);
287 if(!put_dest_flags(ahwif->rx_chan,
288 (void*)(page_address(sg->page)
291 printk(KERN_ERR "%s failed %d\n",
292 __FUNCTION__, __LINE__);
307 dma_unmap_sg(ahwif->dev,
310 hwif->sg_dma_direction);
312 return 0; /* revert to PIO for this request */
315 static int auide_dma_end(ide_drive_t *drive)
317 ide_hwif_t *hwif = HWIF(drive);
318 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
320 if (hwif->sg_nents) {
321 dma_unmap_sg(ahwif->dev, hwif->sg_table, hwif->sg_nents,
322 hwif->sg_dma_direction);
329 static void auide_dma_start(ide_drive_t *drive )
334 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
336 /* issue cmd to drive */
337 ide_execute_command(drive, command, &ide_dma_intr,
341 static int auide_dma_setup(ide_drive_t *drive)
343 struct request *rq = HWGROUP(drive)->rq;
345 if (!auide_build_dmatable(drive)) {
346 ide_map_sg(drive, rq);
350 drive->waiting_for_dma = 1;
354 static int auide_dma_check(ide_drive_t *drive)
356 u8 speed = ide_max_dma_mode(drive);
358 if( dbdma_init_done == 0 ){
359 auide_hwif.white_list = ide_in_drive_list(drive->id,
361 auide_hwif.black_list = ide_in_drive_list(drive->id,
363 auide_hwif.drive = drive;
364 auide_ddma_init(&auide_hwif);
368 /* Is the drive in our DMA black list? */
370 if ( auide_hwif.black_list ) {
371 drive->using_dma = 0;
373 /* Borrowed the warning message from ide-dma.c */
375 printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
376 drive->name, drive->id->model);
379 drive->using_dma = 1;
381 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
387 static int auide_dma_test_irq(ide_drive_t *drive)
389 if (drive->waiting_for_dma == 0)
390 printk(KERN_WARNING "%s: ide_dma_test_irq \
391 called while not waiting\n", drive->name);
393 /* If dbdma didn't execute the STOP command yet, the
394 * active bit is still set
396 drive->waiting_for_dma++;
397 if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
398 printk(KERN_WARNING "%s: timeout waiting for ddma to \
399 complete\n", drive->name);
406 static void auide_dma_host_on(ide_drive_t *drive)
410 static int auide_dma_on(ide_drive_t *drive)
412 drive->using_dma = 1;
417 static void auide_dma_host_off(ide_drive_t *drive)
421 static void auide_dma_off_quietly(ide_drive_t *drive)
423 drive->using_dma = 0;
426 static void auide_dma_lost_irq(ide_drive_t *drive)
428 printk(KERN_ERR "%s: IRQ lost\n", drive->name);
431 static void auide_ddma_tx_callback(int irq, void *param)
433 _auide_hwif *ahwif = (_auide_hwif*)param;
434 ahwif->drive->waiting_for_dma = 0;
437 static void auide_ddma_rx_callback(int irq, void *param)
439 _auide_hwif *ahwif = (_auide_hwif*)param;
440 ahwif->drive->waiting_for_dma = 0;
443 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
445 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
447 dev->dev_id = dev_id;
448 dev->dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
449 dev->dev_intlevel = 0;
450 dev->dev_intpolarity = 0;
451 dev->dev_tsize = tsize;
452 dev->dev_devwidth = devwidth;
453 dev->dev_flags = flags;
456 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
458 static void auide_dma_timeout(ide_drive_t *drive)
460 ide_hwif_t *hwif = HWIF(drive);
462 printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
464 if (hwif->ide_dma_test_irq(drive))
467 hwif->ide_dma_end(drive);
471 static int auide_ddma_init(_auide_hwif *auide) {
473 dbdev_tab_t source_dev_tab, target_dev_tab;
474 u32 dev_id, tsize, devwidth, flags;
475 ide_hwif_t *hwif = auide->hwif;
477 dev_id = AU1XXX_ATA_DDMA_REQ;
479 if (auide->white_list || auide->black_list) {
487 printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model);
488 printk(KERN_ERR " please read 'Documentation/mips/AU1xxx_IDE.README'");
491 #ifdef IDE_AU1XXX_BURSTMODE
492 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
494 flags = DEV_FLAGS_SYNC;
497 /* setup dev_tab for tx channel */
498 auide_init_dbdma_dev( &source_dev_tab,
500 tsize, devwidth, DEV_FLAGS_OUT | flags);
501 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
503 auide_init_dbdma_dev( &source_dev_tab,
505 tsize, devwidth, DEV_FLAGS_IN | flags);
506 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
508 /* We also need to add a target device for the DMA */
509 auide_init_dbdma_dev( &target_dev_tab,
510 (u32)DSCR_CMD0_ALWAYS,
511 tsize, devwidth, DEV_FLAGS_ANYUSE);
512 auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
514 /* Get a channel for TX */
515 auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
517 auide_ddma_tx_callback,
520 /* Get a channel for RX */
521 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
522 auide->target_dev_id,
523 auide_ddma_rx_callback,
526 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
528 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
531 hwif->dmatable_cpu = dma_alloc_coherent(auide->dev,
532 PRD_ENTRIES * PRD_BYTES, /* 1 Page */
533 &hwif->dmatable_dma, GFP_KERNEL);
535 au1xxx_dbdma_start( auide->tx_chan );
536 au1xxx_dbdma_start( auide->rx_chan );
542 static int auide_ddma_init( _auide_hwif *auide )
544 dbdev_tab_t source_dev_tab;
547 #ifdef IDE_AU1XXX_BURSTMODE
548 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
550 flags = DEV_FLAGS_SYNC;
553 /* setup dev_tab for tx channel */
554 auide_init_dbdma_dev( &source_dev_tab,
555 (u32)DSCR_CMD0_ALWAYS,
556 8, 32, DEV_FLAGS_OUT | flags);
557 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
559 auide_init_dbdma_dev( &source_dev_tab,
560 (u32)DSCR_CMD0_ALWAYS,
561 8, 32, DEV_FLAGS_IN | flags);
562 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
564 /* Get a channel for TX */
565 auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
570 /* Get a channel for RX */
571 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
576 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
578 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
581 au1xxx_dbdma_start( auide->tx_chan );
582 au1xxx_dbdma_start( auide->rx_chan );
588 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
591 unsigned long *ata_regs = hw->io_ports;
594 for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
595 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
598 /* set the Alternative Status register */
599 *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
602 static int au_ide_probe(struct device *dev)
604 struct platform_device *pdev = to_platform_device(dev);
605 _auide_hwif *ahwif = &auide_hwif;
607 struct resource *res;
611 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
612 char *mode = "MWDMA2";
613 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
614 char *mode = "PIO+DDMA(offload)";
617 memset(&auide_hwif, 0, sizeof(_auide_hwif));
621 ahwif->irq = platform_get_irq(pdev, 0);
623 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
626 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
630 if (ahwif->irq < 0) {
631 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
636 if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
637 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
642 ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
643 if (ahwif->regbase == 0) {
648 /* FIXME: This might possibly break PCMCIA IDE devices */
650 hwif = &ide_hwifs[pdev->id];
652 hwif->irq = hw->irq = ahwif->irq;
653 hwif->chipset = ide_au1xxx;
655 auide_setup_ports(hw, ahwif);
656 memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
658 hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
659 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
660 hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */
661 hwif->swdma_mask = 0x00;
663 hwif->mwdma_mask = 0x0;
664 hwif->swdma_mask = 0x0;
667 hwif->pio_mask = ATA_PIO4;
668 hwif->host_flags = IDE_HFLAG_POST_SET_MODE;
671 hwif->drives[0].unmask = 1;
672 hwif->drives[1].unmask = 1;
674 /* hold should be on in all cases */
679 /* If the user has selected DDMA assisted copies,
680 then set up a few local I/O function entry points
683 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
684 hwif->INSW = auide_insw;
685 hwif->OUTSW = auide_outsw;
688 hwif->set_pio_mode = &au1xxx_set_pio_mode;
689 hwif->set_dma_mode = &auide_set_dma_mode;
691 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
692 hwif->dma_off_quietly = &auide_dma_off_quietly;
693 hwif->dma_timeout = &auide_dma_timeout;
695 hwif->ide_dma_check = &auide_dma_check;
696 hwif->dma_exec_cmd = &auide_dma_exec_cmd;
697 hwif->dma_start = &auide_dma_start;
698 hwif->ide_dma_end = &auide_dma_end;
699 hwif->dma_setup = &auide_dma_setup;
700 hwif->ide_dma_test_irq = &auide_dma_test_irq;
701 hwif->dma_host_off = &auide_dma_host_off;
702 hwif->dma_host_on = &auide_dma_host_on;
703 hwif->dma_lost_irq = &auide_dma_lost_irq;
704 hwif->ide_dma_on = &auide_dma_on;
707 hwif->drives[0].autodma = hwif->autodma;
708 hwif->drives[1].autodma = hwif->autodma;
711 #else /* !CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
715 hwif->select_data = 0; /* no chipset-specific code */
716 hwif->config_data = 0; /* no chipset-specific code */
718 hwif->drives[0].autodma = 0;
719 hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */
721 hwif->drives[0].no_io_32bit = 1;
723 auide_hwif.hwif = hwif;
724 hwif->hwif_data = &auide_hwif;
726 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
727 auide_ddma_init(&auide_hwif);
731 probe_hwif_init(hwif);
733 ide_proc_register_port(hwif);
735 dev_set_drvdata(dev, hwif);
737 printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
743 static int au_ide_remove(struct device *dev)
745 struct platform_device *pdev = to_platform_device(dev);
746 struct resource *res;
747 ide_hwif_t *hwif = dev_get_drvdata(dev);
748 _auide_hwif *ahwif = &auide_hwif;
750 ide_unregister(hwif - ide_hwifs);
752 iounmap((void *)ahwif->regbase);
754 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
755 release_mem_region(res->start, res->end - res->start);
760 static struct device_driver au1200_ide_driver = {
761 .name = "au1200-ide",
762 .bus = &platform_bus_type,
763 .probe = au_ide_probe,
764 .remove = au_ide_remove,
767 static int __init au_ide_init(void)
769 return driver_register(&au1200_ide_driver);
772 static void __exit au_ide_exit(void)
774 driver_unregister(&au1200_ide_driver);
777 MODULE_LICENSE("GPL");
778 MODULE_DESCRIPTION("AU1200 IDE driver");
780 module_init(au_ide_init);
781 module_exit(au_ide_exit);