2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2006-2007 MontaVista Software, Inc.
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
7 * compiled into the kernel if you have more than one card installed.
8 * Note that BIOS v1.29 is reported to fix the problem. Since this is
9 * safe chipset tuning, including this support is harmless
11 * Promise Ultra66 cards with BIOS v1.11 this
12 * compiled into the kernel if you have more than one card installed.
14 * Promise Ultra100 cards.
16 * The latest chipset code will support the following ::
17 * Three Ultra33 controllers and 12 drives.
18 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
19 * The 8/4 ratio is a BIOS code limit by promise.
21 * UNLESS you enable "CONFIG_PDC202XX_BURST"
26 * Portions Copyright (C) 1999 Promise Technology, Inc.
27 * Author: Frank Tiernan (frankt@promise.com)
28 * Released under terms of General Public License
31 #include <linux/types.h>
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/delay.h>
35 #include <linux/timer.h>
37 #include <linux/ioport.h>
38 #include <linux/blkdev.h>
39 #include <linux/hdreg.h>
40 #include <linux/interrupt.h>
41 #include <linux/pci.h>
42 #include <linux/init.h>
43 #include <linux/ide.h>
48 #define PDC202XX_DEBUG_DRIVE_INFO 0
50 static const char *pdc_quirk_drives[] = {
51 "QUANTUM FIREBALLlct08 08",
52 "QUANTUM FIREBALLP KA6.4",
53 "QUANTUM FIREBALLP KA9.1",
54 "QUANTUM FIREBALLP LM20.4",
55 "QUANTUM FIREBALLP KX13.6",
56 "QUANTUM FIREBALLP KX20.5",
57 "QUANTUM FIREBALLP KX27.3",
58 "QUANTUM FIREBALLP LM20.5",
62 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
64 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
66 ide_hwif_t *hwif = HWIF(drive);
67 struct pci_dev *dev = to_pci_dev(hwif->dev);
68 u8 drive_pci = 0x60 + (drive->dn << 2);
70 u8 AP = 0, BP = 0, CP = 0;
71 u8 TA = 0, TB = 0, TC = 0;
73 #if PDC202XX_DEBUG_DRIVE_INFO
75 pci_read_config_dword(dev, drive_pci, &drive_conf);
79 * TODO: do this once per channel
81 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
82 pdc_old_disable_66MHz_clock(hwif);
84 pci_read_config_byte(dev, drive_pci, &AP);
85 pci_read_config_byte(dev, drive_pci + 1, &BP);
86 pci_read_config_byte(dev, drive_pci + 2, &CP);
90 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
91 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
93 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
95 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
96 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
97 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
98 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
99 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
100 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
101 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
103 default: TA = 0x09; TB = 0x13; break;
106 if (speed < XFER_SW_DMA_0) {
108 * preserve SYNC_INT / ERDDY_EN bits while clearing
109 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
112 if (drive->id->capability & 4)
113 AP |= 0x20; /* set IORDY_EN bit */
114 if (drive->media == ide_disk)
115 AP |= 0x10; /* set Prefetch_EN bit */
116 /* clear PB[4:0] bits of register B */
118 pci_write_config_byte(dev, drive_pci, AP | TA);
119 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
121 /* clear MB[2:0] bits of register B */
123 /* clear MC[3:0] bits of register C */
125 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
126 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
129 #if PDC202XX_DEBUG_DRIVE_INFO
130 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
131 drive->name, ide_xfer_verbose(speed),
132 drive->dn, drive_conf);
133 pci_read_config_dword(dev, drive_pci, &drive_conf);
134 printk("0x%08x\n", drive_conf);
138 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
140 pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
143 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
145 struct pci_dev *dev = to_pci_dev(hwif->dev);
146 u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
148 pci_read_config_word(dev, 0x50, &CIS);
150 return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
154 * Set the control register to use the 66MHz system
155 * clock for UDMA 3/4/5 mode operation when necessary.
157 * FIXME: this register is shared by both channels, some locking is needed
159 * It may also be possible to leave the 66MHz clock on
160 * and readjust the timing parameters.
162 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
164 unsigned long clock_reg = hwif->extra_base + 0x01;
165 u8 clock = inb(clock_reg);
167 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
170 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
172 unsigned long clock_reg = hwif->extra_base + 0x01;
173 u8 clock = inb(clock_reg);
175 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
178 static void pdc202xx_quirkproc(ide_drive_t *drive)
180 const char **list, *model = drive->id->model;
182 for (list = pdc_quirk_drives; *list != NULL; list++)
183 if (strstr(model, *list) != NULL) {
184 drive->quirk_list = 2;
188 drive->quirk_list = 0;
191 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
193 if (drive->current_speed > XFER_UDMA_2)
194 pdc_old_enable_66MHz_clock(drive->hwif);
195 if (drive->media != ide_disk || drive->addressing == 1) {
196 struct request *rq = HWGROUP(drive)->rq;
197 ide_hwif_t *hwif = HWIF(drive);
198 unsigned long high_16 = hwif->extra_base - 16;
199 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
201 u8 clock = inb(high_16 + 0x11);
203 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
204 word_count = (rq->nr_sectors << 8);
205 word_count = (rq_data_dir(rq) == READ) ?
206 word_count | 0x05000000 :
207 word_count | 0x06000000;
208 outl(word_count, atapi_reg);
210 ide_dma_start(drive);
213 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
215 if (drive->media != ide_disk || drive->addressing == 1) {
216 ide_hwif_t *hwif = HWIF(drive);
217 unsigned long high_16 = hwif->extra_base - 16;
218 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
221 outl(0, atapi_reg); /* zero out extra */
222 clock = inb(high_16 + 0x11);
223 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
225 if (drive->current_speed > XFER_UDMA_2)
226 pdc_old_disable_66MHz_clock(drive->hwif);
227 return __ide_dma_end(drive);
230 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
232 ide_hwif_t *hwif = HWIF(drive);
233 unsigned long high_16 = hwif->extra_base - 16;
234 u8 dma_stat = inb(hwif->dma_status);
235 u8 sc1d = inb(high_16 + 0x001d);
238 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
239 if ((sc1d & 0x50) == 0x50)
241 else if ((sc1d & 0x40) == 0x40)
242 return (dma_stat & 4) == 4;
244 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
245 if ((sc1d & 0x05) == 0x05)
247 else if ((sc1d & 0x04) == 0x04)
248 return (dma_stat & 4) == 4;
251 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
254 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
256 ide_hwif_t *hwif = HWIF(drive);
258 if (hwif->resetproc != NULL)
259 hwif->resetproc(drive);
261 ide_dma_lost_irq(drive);
264 static void pdc202xx_dma_timeout(ide_drive_t *drive)
266 ide_hwif_t *hwif = HWIF(drive);
268 if (hwif->resetproc != NULL)
269 hwif->resetproc(drive);
271 ide_dma_timeout(drive);
274 static void pdc202xx_reset_host (ide_hwif_t *hwif)
276 unsigned long high_16 = hwif->extra_base - 16;
277 u8 udma_speed_flag = inb(high_16 | 0x001f);
279 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
281 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
282 mdelay(2000); /* 2 seconds ?! */
284 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
285 hwif->channel ? "Secondary" : "Primary");
288 static void pdc202xx_reset (ide_drive_t *drive)
290 ide_hwif_t *hwif = HWIF(drive);
291 ide_hwif_t *mate = hwif->mate;
293 pdc202xx_reset_host(hwif);
294 pdc202xx_reset_host(mate);
296 ide_set_max_pio(drive);
299 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
305 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
307 struct pci_dev *dev = to_pci_dev(hwif->dev);
309 hwif->set_pio_mode = &pdc202xx_set_pio_mode;
310 hwif->set_dma_mode = &pdc202xx_set_mode;
312 hwif->quirkproc = &pdc202xx_quirkproc;
314 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
315 hwif->resetproc = &pdc202xx_reset;
317 if (hwif->dma_base == 0)
320 hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
321 hwif->dma_timeout = &pdc202xx_dma_timeout;
323 if (dev->device != PCI_DEVICE_ID_PROMISE_20246) {
324 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
325 hwif->cbl = pdc202xx_old_cable_detect(hwif);
327 hwif->dma_start = &pdc202xx_old_ide_dma_start;
328 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
330 hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
333 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
335 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
338 ide_setup_dma(hwif, dmabase);
342 udma_speed_flag = inb(dmabase | 0x1f);
343 primary_mode = inb(dmabase | 0x1a);
344 secondary_mode = inb(dmabase | 0x1b);
345 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
347 "Secondary %s Mode.\n", hwif->cds->name,
348 (udma_speed_flag & 1) ? "EN" : "DIS",
349 (primary_mode & 1) ? "MASTER" : "PCI",
350 (secondary_mode & 1) ? "MASTER" : "PCI" );
352 #ifdef CONFIG_PDC202XX_BURST
353 if (!(udma_speed_flag & 1)) {
354 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
355 hwif->cds->name, udma_speed_flag,
356 (udma_speed_flag|1));
357 outb(udma_speed_flag | 1, dmabase | 0x1f);
358 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
360 #endif /* CONFIG_PDC202XX_BURST */
362 ide_setup_dma(hwif, dmabase);
365 static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
368 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
369 u8 irq = 0, irq2 = 0;
370 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
372 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
374 pci_write_config_byte(dev,
375 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
376 printk(KERN_INFO "%s: PCI config space interrupt "
377 "mirror fixed\n", name);
382 #define IDE_HFLAGS_PDC202XX \
383 (IDE_HFLAG_ERROR_STOPS_FIFO | \
384 IDE_HFLAG_ABUSE_SET_DMA_MODE | \
387 #define DECLARE_PDC2026X_DEV(name_str, udma, extra_flags) \
390 .init_chipset = init_chipset_pdc202xx, \
391 .init_hwif = init_hwif_pdc202xx, \
392 .init_dma = init_dma_pdc202xx, \
394 .host_flags = IDE_HFLAGS_PDC202XX | extra_flags, \
395 .pio_mask = ATA_PIO4, \
396 .mwdma_mask = ATA_MWDMA2, \
400 static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
403 .init_chipset = init_chipset_pdc202xx,
404 .init_hwif = init_hwif_pdc202xx,
405 .init_dma = init_dma_pdc202xx,
407 .host_flags = IDE_HFLAGS_PDC202XX,
408 .pio_mask = ATA_PIO4,
409 .mwdma_mask = ATA_MWDMA2,
410 .udma_mask = ATA_UDMA2,
413 /* 1 */ DECLARE_PDC2026X_DEV("PDC20262", ATA_UDMA4, 0),
414 /* 2 */ DECLARE_PDC2026X_DEV("PDC20263", ATA_UDMA4, 0),
415 /* 3 */ DECLARE_PDC2026X_DEV("PDC20265", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
416 /* 4 */ DECLARE_PDC2026X_DEV("PDC20267", ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
420 * pdc202xx_init_one - called when a PDC202xx is found
421 * @dev: the pdc202xx device
422 * @id: the matching pci id
424 * Called when the PCI registration layer (or the IDE initialization)
425 * finds a device matching our IDE device tables.
428 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
430 const struct ide_port_info *d;
431 u8 idx = id->driver_data;
433 d = &pdc202xx_chipsets[idx];
436 pdc202ata4_fixup_irq(dev, d->name);
439 struct pci_dev *bridge = dev->bus->self;
442 bridge->vendor == PCI_VENDOR_ID_INTEL &&
443 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
444 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
445 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
446 "attached to I2O RAID controller\n");
451 return ide_setup_pci_device(dev, d);
454 static const struct pci_device_id pdc202xx_pci_tbl[] = {
455 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
456 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
457 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
458 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
459 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
462 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
464 static struct pci_driver driver = {
465 .name = "Promise_Old_IDE",
466 .id_table = pdc202xx_pci_tbl,
467 .probe = pdc202xx_init_one,
470 static int __init pdc202xx_ide_init(void)
472 return ide_pci_register_driver(&driver);
475 module_init(pdc202xx_ide_init);
477 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
478 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
479 MODULE_LICENSE("GPL");